TW200834877A - Structure of memory card and the method of the same - Google Patents

Structure of memory card and the method of the same Download PDF

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Publication number
TW200834877A
TW200834877A TW097101851A TW97101851A TW200834877A TW 200834877 A TW200834877 A TW 200834877A TW 097101851 A TW097101851 A TW 097101851A TW 97101851 A TW97101851 A TW 97101851A TW 200834877 A TW200834877 A TW 200834877A
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Taiwan
Prior art keywords
die
dielectric layer
layer
dielectric
substrate
Prior art date
Application number
TW097101851A
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English (en)
Inventor
Wen-Kun Yang
Chun-Hui Yu
Chih-Wei Lin
Chao-Nan Chou
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Advanced Chip Eng Tech Inc
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Publication date
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Publication of TW200834877A publication Critical patent/TW200834877A/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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200834877 I } 九、發明說明： 【發明所屬之技術領域】 本發明係㈣-種記憶卡結構，特別 容納凹槽以配置晶粒之基底。 一有3曰位 【先前技術】 在半導體裝置領域中，裝置之密度持續增加，且體積 逐漸減小。高密度褒置之封裝或交互連接技術的需求亦日 益增加，以符合上述情況。一般而言，在覆晶接合方法 (fhp-Chlp attachment meth〇d)中，銲錫凸塊陣列係形成於晶 粒表面上。銲錫凸塊之形成係利用銲錫合成材料通過錫球 罩幕（solder mask)，以產生所需銲錫凸塊之圖案。粒封穿 之功能包含電源分配（pGwer distHbu，、訊號分配 distribution)、散熱（heat dissipati〇n)、保護及支撐等。由於 半導體結構趨向複雜化，而一般傳統技術，例如導線架封 裝（lead frame package)、軟性封裝（flex package)、剛 2封 裝（rigid package)技術，已無法達成於晶粒上產生具有高穷 度元件之小型晶粒。 ^ 回山 與半導體同時發展的還有一種名為電子電路卡 (electronic circuit card)的產品。記憶卡係應用於個人電 腦、手機、個人數位助理（PDA)、數位相機、數位攝影機电 隨身聽以及其他裝置上以儲存資料。隨著電子卡規格的發 展也產生了許多不同種類的記憶卡。記憶卡較窄的二邊^ 一電子接頭。 記憶卡係一可坎入主裝置的延伸卡。典型的記憶卡可 6 200834877 I » 供高速讀取以及廣大的記憶體容量。^^來，記憶卡的容 量已發展到以GB(Giga-Bytes)為單位。目前有眾多不同的 記憶卡可供選擇。快閃記憶卡可藉由電子處理來清除。因 此，快閃記憶體可以替代硬碟應用於攜帶型電腦中。快閃 記憶卡被廣泛應用於各種裝置中以儲存與複製資料。 圖-提供了若干比較常見之記憶卡圖式。如圖所示 -普通MMC+ i係包含控制器3及快閃晶粒$單元，其 控制益3單TL與快閃晶粒5單it係分開配置的；一小尺寸 MMC卡7則包含控制器晶粒9及快閃晶粒u單元，其控 制器晶粒9係堆疊在快閃晶粒u單元上，故所需面積較 小。普通MMC卡的垂直架構21如圖中的下方所示，包含 了- 64 UELP控制器23、快閃晶粒乃及快閃晶粒27。圖 中所示另-種小尺寸MMC卡則為三晶片堆疊式（3响 stack)結構！3 ’包含了控制器、15、快閃晶粒i7及快閃晶粒 19等單元。而先前技術之缺點在於因為受到打線接合㈤代 bonding)外形的限制，令其難以提供較薄的封襄。採用打 線接合堆疊（W/B stacking)時，由於晶粒堆疊中間需要*門 加上需要模具來保護晶片與電線，因此在提供較薄的= 上有相當程度的困難。相關製程包含了模具灌模（膠）法 (molding injection)或液體印刷法（Uquid p細㈣。盆引發 了關於良率的問題。Micro SD卡所需要的整體厚度^ 0.7mm +Λ 0.1mm 〇 ，因此，目前所需要的係具有可解決上述封裝厚度問題 亚擁有簡易製程之高階記憶卡結構。 7 200834877
i I 【發明内容】 本發明之-目的係在於提供—種超薄及小尺寸（疆n form factor)的記憶卡。 本發明之另一目的係在於提供一種擁有簡易製程以及 低成本方案的可靠產品。 記憶卡的結構包含了一上表面具有晶粒容納凹槽之基 底:-通孔結構及形成於基底之佈線。一第一晶粒配置於 •曰曰粒:，凹槽。—第—介電層形成於第一晶粒與基底之 上 第重佈層（re-distribution layer, RDL)形成於第一 介電層上，其中第一重佈層係搞合至第一晶粒與佈線。一 第二介電層形成於第一重佈層上。一第二晶粒配置於第二 介電層=上。一第三介電層形成於第二介電層與第二晶粒 上。一第二重佈層形成於第三介電層上，其中第二重佈層 係麵合至第二晶粒盘第一 f德爲 咕 一 ^日日弟重佈層。一弟四介電層形成於第 :重佈層上…第三晶粒形成於第四介電層之上並轉合至 _第重佈層。一第五介電層形成於第三晶粒周圍（當第三晶 粒係採用覆晶形式（flip chip type)時，此步驟可略過），並 由一塑膠蓋罩住第一、第二及第三晶粒。 ^另外包3 了被動70件（Passive device)形成於該第四介 電層上。在一實施例中’第三晶粒係由覆晶配置法即”峋 _啊ation)所形成的。在另—實施例中，第三晶粒係連 、=於該第四介電層之上’而第三重佈層係形成於第五介電 層上並耦合至該第二重佈層。 第、第一、第二、第四及第五介電層其中之一包含 8 200834877 ! * 一彈性介電層（elastic dielectric layer)。第一、第二、第三、 第四及第五介電層其中之一包含一以矽酮介電（siHcone dielectric)為主的材質、苯環丁烯（benzo-cyclo_butene，BCB) 或聚亞醯胺（polyimide，PI)。以矽酮介電為主的材質包含了 砍氧烧聚合物（SINR)、矽酮氧化物、秒酮氮化物或其合成 物。弟一、弟一、弟二、第四及第五介電層其中之一包含 一感光層（photosensitive layer)。由第一及第二晶粒擴散出 (fan out)第一及第二重佈層。 *【實施方式】 本發明將配合其較佳實施例與後附之圖式詳述於下。 應可理解，本發明中之較佳實施例係僅用以說明，而非用 以限定本發明。此外，除文中之較佳實施例外，本發明亦 可廣泛應用於其他實施例，並且本發明並不限定於任何實 施例，而應視後附之申請專利範圍而定。 本發明揭露一種晶圓級封裝（wafer level package， 籲WLP)之結構，其基底具有預定凹槽，並有通孔形成於基 底。感光層係塗佈於晶粒及預形成基底之上。較佳的情況 下’感光層之材料係由彈性材料所形成。 圖一係為預形成之基底，圖三及圖四係為記憶卡之結 構，而圖五則係根據本發明所實施的一例之流程。如圖二、 0 一 乂及圊五⑷戶斤示’此結構包含具有晶粒容納凹槽*之 基底2得以配置晶粒。複數的通孔8以及佈線❻計於基 底2之中或之上。通孔8係形成於基底2之上表面至基底 2之下表面。一導電材質將填入於通孔8之中以利電子連 9 200834877 j » 接。一端點墊56形成於基底2之下表面。 一第一晶粒1 〇係配置於基底2的晶粒容納凹槽4之中 亚藉由黏著性材質12加以固定。如熟知該項技術者所熟 知，接觸墊（連接墊（bonding pads))14係形成於晶粒之 上，而接觸墊16則形成於基底2之上。填充材質22係裝 填於晶粒及晶粒容納凹槽4侧壁間之空隙，此填充材質可 與上述之黏著性材質12相同。一感光層（ph〇t〇sejJtive layer)或介電層18係形成於晶粒之上並填入晶粒ι〇以及晶 粒容納凹槽4牆壁間之空隙（以保持相同之表面層）。於微 影製程（lithography process)或曝光製程（exp〇s⑽ procedure)中，複數開口將形成於介電層18之内。複數開 口係分別經由通孔8對準（aligned)接觸，以及對準接觸或 輸入/輸出墊（I/O pad)14。重佈層（仏細仙此⑽一叫 RDL)20,亦可稱為金屬佈線，係藉由移除部份形成於介電 層=上之金屬層而形成於介電層18之上，其中重佈層汕 •係藉由輸入/輸出墊14以與晶粒10保持電性連接 (eleCtrically c〇nnected)。部份重佈層之材質將重新填入介 電曰18之開口，因此藉由通孔8上的金屬以及墊μ上的 金屬而形成接觸。如圖三以及圖五（c)所示，另一介電層24 係覆蓋於重佈層2〇之上。 請參照圖三以及圖五⑷七），介電層18係形成於晶粒 10以及基底之頂上並填滿晶粒2周遭的空間。一第二晶粒 %係藉由黏著性材質28而裝配於第二介電層24之上。同 樣地，第三介電層或感光層30係形成於第二晶粒％之上 10 200834877 i > 並填入鄰接晶粒26之空間。於料岑制扣斗、3 门於谜衫製程或曝光製程中，複 ，開口將形成於介電層30之内。複數開口係分別經由第二 之輸入/輸出塾36而對準接觸。一第二重佈層 係糟由移除部份形成於介電層上之金屬層而形成 !層30之上’其中重佈層32係藉由輸入/輸出塾… =晶粒26保持電性連接。—第四介電層Μ覆蓋於第二 Y層32之上。複數開口形成於第四介電層中。 _ —請參照圖三以及圖五（fHg)，一第三晶粒38係袭配於 :四介電層34之上並藉由第四介電層34之開口以及第三 :¾粒38之凸塊而耦合至第二重佈層32。較佳的情況下， 第三晶粒38係藉由覆晶配置法(flip _ _以刪_而 耦合。另外，至少一被動元件（passivedevice)4〇可藉由表 面黏著技術（surface mount techn〇1〇gy，SMT)耦合至第二重 佈層32。最後，一頂層42係被形成來覆蓋住被動元件仂 並至J包圍住第三晶粒38(在本發明中，此過程係可略 •過）、。在一實施例中，晶粒38之上表面得為無遮蔽，以藉 此減少厚度並增強散熱（thermal dissipati〇n)效果。第二重 佈層32係藉由通孔結構44與第一重佈層2〇相連。 在另一情況下，如圖六及圖五（h)-(i)所示，第三晶粒 38並非藉由覆晶配置法而係藉由黏著性材質46裝配於第 二重佈層上。一第五介電層48係被形成來覆蓋被動元件 40以及第二晶粒38。一第三重佈層50係形成於第五介電 層48上並連結至第三晶粒、被動元件以及第二重佈層以。 如圖五（h)-(i)所示，一頂層52係形成於第三重佈層5〇之 11 200834877 s ， 上。由於其他結構與圖五（a)-(e)相似，因此省略了相關敘 述。圖四及圖七標明了記憶卡結構的尺寸。如圖所示，本 發明之尺寸較先前技術之尺寸為薄。 圖八描述了記憶卡之最終結構。一預形成之塑膠蓋54 罩住眾多晶粒。標誌可以標於上蓋之上，錫球罩幕（solder mask)則形成於封裝結構之下藉以露出端點墊5 6。 較佳的情況下，基底2之材料係為有機基底例如 FR5、BT、FR4、具有已定義凹槽（defined cavity)之印刷電 ⑩路板（PCB)或具有預蝕刻電路（pre_etching circuit)之 Alloy42。具有高玻璃轉移溫度（glass transition temperature, Tg)之有機基底係為環氧化物型（epoxy type) FR5或BT (Bismaleimide triazine)型基底。Alloy42 係由鎳（42%)以及 鐵（58%)所組成。也可使用柯華合金（Kovar)，其成份為鎳 (29%)、鈷（17%)以及鐵（54%)。玻璃、陶瓷、矽酮亦可做為 基底。凹槽4之厚度可以比晶粒10稍微厚一點。而深度也 φ可以更深一點。 基底可為圓形（round type)，例如晶圓型（wafer type)， 且其直徑（diameter)可為200、300 mm或更高。也可以採 用矩形（rectangular type)，例如面板型（panel form)。在本 發明之一實施例中，本發明之介電層在較佳情況下係以矽 酮介電（silicone dielectric)為主之彈性材質，其包含矽氧烷 聚合物（SINR)、矽酮氧化物、矽酮氮化物或其合成物。在 另一實施例中，介電層係由包含笨環丁烯（BCB)、環氧化 物（epoxy)、聚亞醯胺（PI)或樹脂。在較佳的情況下，為了 12 200834877 製程的簡便，其將採用感光層。 在本發明之一實施例中，上述彈性介電層係為一種熱 膨脹係數（CTE)大於 100(ρριη/°〇、延伸速率（elongation rate) 約40 % (較佳的為30 %至50 % )及硬度（hardness)介於塑 膠與橡膠間之材質。彈性介電層18之厚度係依照溫度循環 試驗（temperature cycling test)期間重佈層/介電層介面中所 累積之應力（stress)而決定。 在本發明之一實施例中，重佈層之材質包含鈦/銅/金 •合金（Ti/Cu/Au alloy)或鈦 / 銅 / 鎳 / 金合金（Ti/Cu/Ni/Au alloy);重佈層之厚度係介於2μπι及15μιη之間。鈦/銅合 金（Ti/Cu alloy)係利用濺鍍（sputtering)技術所形成，例如晶 種金屬層（seed metal layers)，而銅/金（Cu/Au)或銅/鎳/金合 金（Cu/Ni/Au alloy)係由電鍍（electroplating)技術所形成， 利用電鏡製程形成重佈層可使重佈層具有足夠之厚度以容 忍溫度循私期間之熱膨服係數不相符（mismatching)。金屬 _墊可為鋁或銅或其組合。 如圖五（a)-(g)所示，重佈層係由晶粒擴散，並且往下 與佈線6連接。連接佈線係經由通孔8穿過基底2。因此 可縮減晶粒封裝之厚度。本發明之封裝將較先前技術為 薄。再者，基底係於封裝前預先形成。凹槽4以及佈線6 也係預先形成的。因此，生產率（throughput)可較以往更為 增進。本發明揭露一種不需在重佈層上堆疊增層（built_up layers)之擴散式晶圓級封裝（WLP)技術。 本發明之優點詳述如下： 13 200834877 超濤封裝及小尺寸（small form fact〇r):封裝之厚度係 約450μιη至600μπι，而封裝尺寸（form factor)可以只較晶 片尺寸稍微大一點。其可輕易控制包含塑膠蓋之完成品之 總厚度。晶粒之厚度可控制在約5〇μπι至ι〇〇μπι，並可藉 由在封裝内堆疊晶粒而達成較高密度之記憶體。 較可罪的產品：晶片係完整包裝於封裝内。至少丨 子之I氧化物材貝形成於晶片的兩面。晶片係配置於凹槽 中而彈〖生材貝則充填於晶片周圍及凹槽壁面之中，用以 吸收晶片及基底（FR5之熱膨脹係數約為17至2〇)之間熱膨 脹係數不相符所產生之機械應力（mechankai Mass)。再 者’介電層係採用彈性材質故可以吸收溫度循環期間之機 械應力。晶片可以堆疊在第—晶片上，解決熱膨脹係數不 間易製程以及低成本方案：本發明利用具有晶粒容納
Γ二t Ϊ底(FR5)以及其中所形成之電路。塊板(piece panel) 或批二人式（batch type)之「封裂」製造係採用增層㈣ layers)步驟。晶粒係藉由板 以祖处^ A 面連、、、口（Panel bonding)步驟裝配 以提供較尚的準確性。封步 八 (A.. 、之刀口1丨係採用晶粒切割步驟 ( =aW㈣叫來使「封農」分離。並採用-預形成 之塑膠蓋以完成最終產品。 ,1Χ ^ ^明可根據板面層級hanel 1叫來職FGS產品崎低戰成本。日、物撕1 本發明以較佳實施例說明 菸昍糾+并^ 上然其亚非用以限定本 申請專利範圍及其等同領域而、/利保相圍當視後附之 一 疋凡‘悉此領域之技藝 200834877 < ,* 更動或潤飾， 受或設計，且 者，在不脫離本專利精神或範圍内，所作之 均屬於本發明所揭示精神下所完成之等效改 應包含在下述之申請專利範圍内。 【圖式簡單說明】 圖一係為根據先前技術之記憶卡結構之剖面圖。 圖=係為根據本發明之基底結構之剖面圖。 圖二係為根據本發明之結構之剖面圖。 φ 圖四係為根據本發明之結構之剖面圖。 圖=(a) - (i)係為根據本發明之記憶卡製程之流程圖。 圖六係為根據本發明之結構之剖面圖。 圖七係為根據本發明之結構之剖面圖。 圖八係為根據本發明之結構之剖面圖。 【主要元件符號說明】 1普通MMC卡 2基底 3控制器 4晶粒容納凹槽 5快閃晶粒 6佈線 七尺寸MMC卡 9控制器晶粒 10第一晶粒 U快閃晶粒 15 200834877 12黏著性材質 13二晶片堆豐式結構 14輸入/輸出墊 15控制器 16接觸墊 17快閃晶粒 18第一介電層 19快閃晶粒 20第一重佈層 21普通MMC卡垂直架構 22填充材質 23 64 UELP控制器 24第二介電層 25快閃晶粒 26第二晶粒 27快閃晶粒 28黏著性材質 30第三介電層 32第二重佈層 34第四介電層 36輸入/輸出墊 38第三晶粒 40被動元件 42頂層 16 200834877 44通孔 48第五介電層 50第三重佈層 54預形成之塑膠蓋 56端點墊
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Claims (1)

  1. 200834877 十、申請專利範圍： 1· 一種記憶卡結構，包含： 一基底具有一晶粒容納凹槽位於該基底之上表面、一通 孔結構及一形成於該基底之佈線； 一第一晶粒配置於該晶粒容納凹槽之内； 第一介電層形成於該第一晶粒與該基底之上； 第重佈層形成於該第一介電層之上，其中該第一重 佈層係耦合至該第一晶粒與該佈線； 一第一介電層形成於該第一重佈層； 弟一晶粒配置於該第二介電層· 一=三介電層形成於該第二介電層與該第二晶粒之上； 一第二重佈層形成於該第三介電層之上，其中該第二重 佈層係耦合至該第二晶粒與該第一重佈層； 苐四介電層形成於該第二重佈層之上； 一第三晶粒形成於該第四介電層之上並耦合至該第二 重佈層； ^ 一 一第五介電層形成於該第三晶粒之周圍；及 一塑膠蓋罩住讓第一、第二及第三晶粒。 2‘如請求項1所述之結構，更包含形成於該第四介電層之 被動元件。
    如請求項1所述之結構， 法所形成。 其中該第三晶粒係由覆晶配置 18 200834877 4.如請求項丨所述之結構，其中該第三晶粒係附屬於該第 四介電層之上，而一第三重佈層係形成於該第五介電層 之上並轉合至該第二重佈層。 5·如請求項1所述之結構，其中該第一、第二、第三、第 四及第五介電層中有一層包含一彈性介電層。 6·如睛求項1所述之結構，其中該第一、第二、第三、第 四及第五介電層中有一層包含一以石夕嗣介電為主的材 質、笨環丁烯（BCB)或聚亞醯胺（ρι)。 7.如請求項6所述之結構，其中該以㈣介電為主的材質 匕3石夕氧烧聚合物（SINR)、石夕酮氧化物、石夕酮氮化物或 其合成物。 8.如請^項1所述之結構，其中該第-、第二、第三、第 四及第五介電層中有-層包含-感光層。 9’ ：：：項1所述之結構’其中該第一及第二重佈層係由 L 3鈦/銅/金或鈦/銅/鎳/金之合金所組成。 該第一及第二晶粒擴散出 10·如5月求項1所述之結構，其中 該第一及第二重佈層。 19 200834877 11 ·如明求項1所述之結構，其中该基底之材質包含環氧化 物型FR5及FR4。 12·如明求項1所述之結構，其中違基底之材質包含bt。 Π•如請求項1所述之結構，其中該基底之材質包含印刷電 路板。 14·如請求項丨所述之結構，其中該基底之材質包含合金或 金屬。 15·如請求項14所述之結構，其中該基底之材質包含 Alloy42 (42%鎳-58%鐵）或 Kovar (29%鎳_17%钻 _54% 鐵）。 16.如請求項1所述之結構，其中該基底之材質包含玻璃。 17·如請求項丨所述之結構，其中該基底之材質包含矽酮。 18 ·如明求項1所述之結構，其中該基底之材質包含陶竟。 19· 一種形成半導體裝置封裝之方法，包含： 提供—基底具有一晶粒容納凹槽位於該基底之上表面 20 200834877 ^通孔結構’其中—傳導佈線形成於該基底之上或之 中； 人〜 提供-第-晶粒配置於該晶粒容納凹槽之内 形成-第-介電層於該第—晶粒與該基底之上； :::第-重佈層於該第—介電層之上，其中該第一重 布曰係耦合至該第一晶粒與該佈線； 形成一第二介電層於該第一重佈層;’ 形成一第二晶粒配置於該第二介;層； 第三介電層於該第二介電層與該第二晶粒之上； 形成-第二重佈層於該第三介電層之上，其中該第二重 佈層係耦合至該第二晶粒與該第一重佈層； 形成一第四介電層於該第二重佈層之上.， 第三晶粒於該第四介電層a之上並耦合至該第二 更怖層； 开:成-第五介電層於該第三晶粒之周圍;及 提供—塑膠蓋罩住該第_ 第二及第 粒 20.=求項19所述之方法，更包含了—提供被動元件於 成弟四介電層之上之步驟。 弟二晶粒係由覆晶配 21·如請求項19所述之方法，其中該 置法所形成。 该弟二晶粒係裝配於該 22·如請求項19所述之方法，其中 21 200834877 第四介電層之上，而該第三重佈層係形成於該第五介電 層之上並耦合至該第二重佈層。 23·如請求項19所述之方法，其中該第一、第二、第三、 第四及第五介電層中有一層包含一彈性介電層。 24·如請求項19所述之方法，其中該第一、第二、第三、 第四及第五介電層中有一層包含一以矽酮介電為主之 _ 材質、苯環丁烯（BCB)或聚亞醯胺（PI)。 25·如請求項24所述之方法，其中該以矽酮介電為主的材 質包含矽氧烷聚合物（SINR)、矽酮氧化物、矽酮氮化物 或其合成物。 26·如請求項19所述之方法，其中該第一、第二、第二、 φ 第四及第五介電層中有一層包含一感光層。 27·如請求項19所述之方法，其中該第一及第二重佈層係 由一包含鈦/銅/金或鈦/銅/鎳/金之合金所組成。 28.如請求項19所述之、方法，其中該基底之材質包含環氧 化物型FR5、fr4、bt、印刷電路板（PCB)、玻璃、^ 究、石夕_、合金、或金屬。 22 200834877 29·如請求項28所述之方法，其中該基底之材質包含 Alloy42 (42%鎳-58%鐵）或 Kovar(29%鎳-17%鈷-54% 鐵）。
    23
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