CN110085558A - 密封材料组合物、半导体封装及其制造方法 - Google Patents

密封材料组合物、半导体封装及其制造方法 Download PDF

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Publication number
CN110085558A
CN110085558A CN201811172434.4A CN201811172434A CN110085558A CN 110085558 A CN110085558 A CN 110085558A CN 201811172434 A CN201811172434 A CN 201811172434A CN 110085558 A CN110085558 A CN 110085558A
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Prior art keywords
encapulant composition
composition
encapulant
layer
conductive path
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CN201811172434.4A
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王铭毅
黄崑永
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种密封材料组合物及半导体封装。适于密封半导体管芯的密封材料组合物包括感光性介电材料及可极化的化合物，可极化的化合物悬浮于感光性介电材料中。可极化的化合物在感光性介电材料的预定区域中受到外部刺激的影响，在密封材料组合物的厚度方向上规则地排列以提供沿厚度方向穿透感光性介电材料的导电路径。半导体封装结构包括密封半导体管芯的密封材料组合物、第一重布线层与第二重布线层，第一及第二重布线层配置于密封材料组合物的相对的两个面上，且通过密封材料组合物彼此电性连接。本发明还提供一种半导体封装结构的制造方法。

Description

密封材料组合物、半导体封装及其制造方法
技术领域
本发明涉及一种密封材料组合物、封装结构及其制造方法，尤其涉及一种用于密封半导体管芯的密封材料组合物、包括此密封材料组合物的半导体封装及其制造方法。
背景技术
在某些类别的传统封装技术(例如扇出芯片级封装(fan-out wafer levelpackaging；FO-WLP))之中，使用电镀工艺来形成多个铜柱(copper pillars)会耗费很长的时间，此外，在电镀工艺之后，半导体芯片(chip)密封于模封化合物(molding compound)中，接着，研磨模封化合物以暴露出这些铜柱，使这些铜柱能进一步进行电性连接。然而，由于难以控制研磨的深度，所以通常不是过度研磨铜柱，就是没有将铜柱暴露出来。再者，因为模封化合物与芯片之间的材料差异，故在半导体封装的工艺过程中可能产生翘曲(warpage)问题。因此，如何在工艺中避免上述的问题实为本领域亟欲解决的重要课题。
发明内容
本发明是针对一种密封材料组合物、半导体封装及其制造方法，其可以简化封装制造和减少翘曲问题的产生。
根据本发明的实施例，一种适于密封半导体管芯的密封材料组合物，包括感光性介电材料以及可极化的化合物。可极化的化合物悬浮于感光性介电材料中，其中可极化的化合物在密封材料组合物的预定区域中受到外部刺激的影响，而在密封材料组合物的厚度方向上呈规则地排列以提供导电路径，导电路径是沿着厚度方向穿透感光性介电材料。
在根据本发明的实施例中，外部刺激包括辐射能、电能和热能。
根据本发明的实施例，一种半导体封装，包括半导体管芯、如上述的密封材料组合物、第一重布线层以及第二重布线层。密封材料组合物密封半导体管芯。第一重布线层设置于密封材料组合物的第一表面上，且第一重布线层电性连接于密封材料组合物及半导体管芯。第二重布线层设置于密封材料组合物相对于第一表面的第二表面上，且第二重布线层通过密封材料组合物与第一重布线层电性连接。
在根据本发明的实施例中，密封材料组合物的导电路径围绕半导体管芯。
在根据本发明的实施例中，半导体封装还包括导电端子，配置于第一重布线层与密封材料组合物电性连接的相对面上。
在根据本发明的实施例中，半导体管芯包括有源面以及多个导电凸块。这些导电凸块分布于有源面上，密封材料组合物暴露出至少一部分的导电凸块，且第一重布线层与一部分的导电凸块电性连接。
在根据本发明的实施例中，密封材料组合物暴露出半导体管芯相对于有源面的背面，且密封材料组合物的表面与半导体管芯的背面共平面。
根据本发明的实施例，一种半导体封装的制造方法，包括以下步骤。通过密封材料组合物密封半导体管芯，其中密封材料组合物包括感光性介电材料和与感光性介电材料混合的可极化的化合物。极化密封材料组合物的预定区域，以形成围绕半导体管芯的导电路径。形成第一重布线层于密封材料组合物的第一表面上，以电性连接半导体管芯和密封材料组合物中的导电路径。形成第二重布线层于密封材料组合物相对于第一表面的第二表面上，以电性连接密封材料组合物中的导电路径。
在根据本发明的实施例中，密封材料组合物的预定区域在经过曝光制造和极化制造之后，密封材料组合物的预定区域的电阻值低于密封材料组合物的其他区域的电阻值。
在根据本发明的实施例中，半导体管芯包括多个导电凸块，半导体封装的制造方法还包括在对密封材料组合物进行固化制造之后，薄化密封材料组合物的厚度，以暴露出半导体管芯的导电凸块。
在根据本发明的实施例中，在薄化密封材料组合物的厚度之后，形成第一重布线层，且第一重布线层电性连接至从密封材料组合物中暴露出的半导体管芯的导电凸块。
在根据本发明的实施例中，半导体封装的制造方法还包括在形成第二重布线层之前，形成导电端子在相对于密封材料组合物的第一重布线层上。
在根据本发明的实施例中，通过密封材料组合物密封半导体管芯的步骤包括配置半导体管芯于临时载板上，以及形成密封材料组合物于临时载板上以密封半导体管芯。制造方法还包括在形成第二重布线层之前移除临时载板。
基于上述，半导体管芯通过密封材料组合物密封。密封材料组合物包含可极化的化合物，其在经过特定工艺之后提供多个导电路径。因此，可省略传统的模封工艺(moldingprocess)与镀铜工艺(copper plating process)，进而达到简化半导体封装工艺以及减少翘曲问题的产生。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1A至图1N是依据本发明一实施例的半导体封装结构的制造方法的剖面示意图。
附图标号说明
10：半导体封装结构
50：第一临时载板
52：离型层
54：粘着层
60：第二临时载板
100：半导体管芯
102：有源面
104：背面
106：侧面
108：导电凸块
200、200’：密封材料组合物
202：第一表面
204：第二表面
210：感光性介电材料
220：可极化的化合物
230：导电路径
300：第一重布线路层
310、610：介电层
320、620：图案化导电层
322：晶种层
324：导电层
410：第一钝化层
410a、420a：开口
420：第二钝化层
500：导电端子
600：第二重布线路层
D：厚度方向
E：电刺激单元
M：掩膜
M1：透明部
P：水平间距
R：辐射
RS：辐射源
PR：光刻胶
PR’：图案化光刻胶层
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
图1A至图1N是依据本发明一实施例的半导体封装结构的制造方法的剖面示意图。请参照图1A，利用密封材料组合物(encapsulating composition)200密封半导体管芯100，半导体管芯100可以包括有源面102、相对于有源面102的背面104、设置于有源面102与背面104之间的侧面106以及设置于有源面102上的多个导电凸块108。半导体管芯100可以是硅管芯，硅管芯例如是特殊应用集成电路(Application-specific integrated circuit；ASIC)管芯或微机电系统(Microelectromechanical Systems；MEMS)管芯。其他适宜的有源元件也可以作为半导体管芯100。在一些实施例中，半导体管芯100附着于第一临时载板50上，第一临时载板50可以由玻璃、塑胶或其他适宜的材料所制成，只要前述的材料能够于后续的工艺中，承载形成于其上的半导体封装结构。于设置半导体管芯100于第一临时载板50前，可以先在第一临时载板50上形成离型层52，以提升于后续过程中的离型能力(releasability)。离型层52可以是光-热转换(light-to-heat-conversion；LTHC)离型层或其他合适的离型层，在一些实施例中，可以在离型层52上形成粘着层54，以加强第一临时载板50与离型层52粘着于半导体管芯100的背面104的粘着力。在一些实施例中，半导体管芯100可以直接地与第一临时载板50接触。
在第一临时载板50上设置半导体管芯100后，可以在第一临时载板50上使用沉积(deposition)工艺形成密封材料组合物200，沉积工艺例如是旋转涂布法(spin coating)或其他合适的工艺。
密封材料组合物200可以是均匀组成的均质混合物(homogeneous mixture)。在一些实施例中，密封材料组合物200可以是非均质混合物(heterogeneous mixture)。密封材料组合物200可以包括感光性介电材料(photosensitive dielectric material)210和可极化的化合物(polarizable compound)220，可极化的化合物220在初始状态可以悬浮于感光性介电材料210中。初始状态可以是指未激态(unexcited condition)。可极化的化合物220与感光性介电材料210于初始状态时可为均质地混合。可极化的化合物220可以均质地分布于整个密封材料组合物200中。在一些实施例中，密封材料组合物200可以包括相同比例的可极化的化合物220与感光性介电材料210。感光性介电材料210占密封材料组合物200的体积百分比可介于约30％至40％之间。在一些实施例中，密封材料组合物200可以包括体积百分比大于50％的更高比例的可极化的化合物220，举例来说，更高比例的可极化的化合物220的体积百分比范围约是60％至70％之间。含有更高比例的可极化的化合物220的密封材料组合物200可以具有高导电性可靠度。
在一些实施例中，感光性介电材料210可以包括聚酰亚胺(polyimide)、可固化性树脂(curable resin)或其类似者。在一些实施例中，感光性介电材料210的热膨胀系数(coefficient of the thermal expansion；CTE)可以与半导体管芯100的热膨胀系数相近，以使因热膨胀系数不匹配(mismatch)所带来的影响最小化，并减少翘曲问题的产生。可极化的化合物220可以包括异向性导电粒子(anisotropic conductive particles)、纳米结构(nanostructure)或其组合。异向性导电粒子可以只在一个方向上具有导电性，举例而言，此方向可以平行于密封材料组合物200的厚度方向D，此厚度方向D也可视为Z方向。异向性导电粒子可以具有各种形状，例如是球形、椭圆形或圆柱形，但本发明不以此为限。异向性导电粒子的平均粒径(mean particle size)的范围基本上是介于10nm至10μm之间，以于后续过程中可以具备应有的导电特性(conductive characteristics)。异向性导电粒子的平均粒径可以根据用来作为电性连接的导电路径之间的间距的设计要求而有所不同。
当纳米结构与异向性导电粒子混合时，可极化的化合物220可包含占密封材料组合物200的体积百分比约为10％的纳米结构以及占密封材料组合物200的体积百分比约为40％的异向性导电粒子。在一些实施例中，可极化的化合物220可以包含体积百分比超过10％的纳米结构，可极化的化合物220也可包含占密封材料组合物200的体积百分比浓度约为20％至35％的纳米结构以及占密封材料组合物200的体积百分比浓度约为30％至35％的异向性导电粒子。
纳米结构可经受高磁和电极化(electric polarization)工艺。所述纳米结构可以于密封材料组合物200中与异向性导电粒子混合。在一些实施例中，纳米结构可以是各种元素，包含碳元素或其他金属元素(例如Ag、Au、Cu、Al、W、Co或其类似者)。碳纳米结构可为纳米碳管，纳米碳管可采用单壁纳米碳管(single-wall nanotubes，SWNT)或多壁纳米碳管(multiple walls nanotubes，MWNT)。在一些实施例中，纳米结构的体积百分比浓度可以从0(或稍微大于0.00％，如0.01％)至大约35.0％。可极化的化合物220在密封材料组合物200中具有高体积百分比浓度，能够使可极化的化合物220在后续过程中作为更好的导电路径。密封材料组合物200的导电性可因可极化的化合物220所占的体积百分比而有所不同，并可通过可极化的化合物220所占的体积百分比来控制密封材料组合物200的导电性。密封材料组合物200的合适厚度取决于之后的应用而可有显著的不同。举例来说，在应用于半导体封装的情况下，密封材料组合物200的合适厚度范围基本上可以介于5μm至2000μm。密封材料组合物200在初始状态的时候，可以具有相对低的电阻率(electrical resistivity)，例如是介于约1M Ohm/cm2至1000M Ohm/cm2的范围。
请参考图1B，在形成密封材料组合物200之后，密封材料组合物200的预定区域受到外部刺激的影响，使这些导电路径230沿着厚度方向D穿透感光性介电材料210，此类外部刺激可以是来自于密封材料组合物200周围不同的环境刺激所造成的结果。举例而言，外部刺激可能是以电能、辐射能或热能等形式施加于密封材料组合物200。
举例而言，由电刺激单元(electrical stimulation unit)E产生涵盖所述预定区域的外部电场。金属掩膜(未示出)可用来遮蔽其他区域(例如半导体管芯100所在的区域或是其他不欲受外部电场的区域)。举例而言，金属掩膜的材料可以包含铅、铝、铜、铬、金属合金(例如是铁、锰、镍、铜、铬或其类似者)或其他合适的金属材料。在其他的实施例中，电刺激单元E中的电极化探针(未示出)可以直接移动到所述预定区域进行电极化而不涵盖到其他区域。
当外部电场被施加于密封材料组合物200的所述预定区域时，所述预定区域中的分子会获得电偶极矩，藉以造成可极化的化合物220中的元素产生位移的现象。带正电的元素会随着电场方向移动，而带负电的元素会随着相对于电场方向的方向移动。换句话说，围绕半导体管芯100的密封材料组合物200的所述预定区域被极化，以使可极化的化合物220于厚度方向D上呈规则地排列，因为可极化的化合物220具有Z方向的异向性材料(如异向性导电粒子)，因此，可以在所述预定区域上形成导电路径230。在一些实施例中，可以使用直流电场，电场强度范围实质上介于0.1V/m至100V/m之间。通过调整延时(duration time)可以调整电刺激的程度。对于相对低的刺激强度来说，可以增加延时以连续的刺激。对于相对高的刺激强度来说，可依设计的需求减少延时。于密封材料组合物200中形成的导电路径230的关键尺寸(critical dimension)是可以被调整、控制和/或最适化，以满足图案化的需求。这些导电路径230可以通过调整工艺参数来获得各种尺寸。所述预定区域在朝向半导体管芯100的边缘与半导体管芯100的侧面106之间的水平间距P的范围可以约为100μm至约1.0mm，在此水平间距P范围内可以保护半导体管芯100在电极化工艺的期间不受到影响。
于进行电极化工艺以极化密封材料组合物200的期间，在密封材料组合物200上的所述预定区域执行曝光工艺，以硬化这些导电路径230。通过使用例如光刻(lithography)系统将来自辐射源RS所发射出来的辐射R穿过掩膜(mask)M投射至密封材料组合物200，以对密封材料组合物200进行图案曝光。可以在密封材料组合物200上形成一层光刻胶(photoresist)PR。在一些实施例中，光刻胶PR可以是用于负型图案显影的负型(negative-tone)光刻胶，如图1B所示。这层光刻胶PR可以具有被辐射R所曝光的多个曝光部和没有被辐射R所曝光的多个未曝光部。掩膜M的多个透明部M1被成像(imaged)到这层光刻胶PR上，以产生相应的多个光刻胶特征，这些光刻胶特征对齐于这些曝光部。这些曝光部之间的间距是由掩膜M的这些透明部M1之间的间距决定。在一些实施例中，可视设计需求采用正型(positive-tone)光刻胶。
在电极化工艺与曝光工艺之后，对密封材料组合物200执行显影工艺(developingprocess)，其中将未被照射到的区域移除(在使用负型光刻胶的情况下)。在移除这层光刻胶PR未被照射到的区域之后，被照射的这些曝光部会形成图案，这图案从掩膜M转移到密封材料组合物200。在一些实施例中，也可以使用正型光刻胶来对密封材料组合物200执行光刻工艺(lithography process)，在此类实施例中，对密封材料组合物200执行显影工艺，其中将被照射到的区域移除。
密封材料组合物200可以被固化(cured)，而包含这些导电路径230的图案化密封材料组合物200’大致上完成。可以使用热能、紫外光或其组合来固化密封材料组合物200。举例而言，密封材料组合物200具有一固化起始温度(例如是室温至大约150℃)，小于这个固化起始温度，密封材料组合物200则不会被固化。将密封材料组合物200加热到所述固化起始温度之上时，密封材料组合物200便会开始被固化。加热温度的范围可以是从约160℃至约300℃。在一些实施例中，在对密封材料组合物200执行电极化工艺和光刻工艺以形成这些导电路径230之后，这些导电路径230具有热传导性，因此热量可以经由热传导的方式通过这些导电路径230散布在密封材料组合物200之中。在密封材料组合物200中散布的热量可以造成密封材料组合物200的温度上升至所述固化起始温度之上。在施加热量后，密封材料组合物200会进行化学键结而形成硬质刚性结构的密封材料组合物200’。在一些实施例中，在执行电极化工艺和光刻工艺之后，密封材料组合物200的所述预定区域(即导电路径230)的电阻率可实质上介于1Ohm/cm2至100Ohm/cm2之间。导电率可以通过测量在厚度方向D上的传导性能来评估。在经过上述工艺后，密封材料组合物200’中被加工过的区域可具有较高导电性，在密封材料组合物200’的其他未被加工过的区域中，可极化的化合物220可以通过感光性介电材料210被绝缘。因此，密封材料组合物200’中被加工过的区域相较于密封材料组合物200’中其他未被加工过的区域具有较低的电阻率。由于密封材料组合物200在经过上述工艺之后可以使得所述预定区域变成导电路径230，而密封材料组合物200’的其他区域则保持绝缘特性，因此可以省略传统的镀铜工艺，进而可以有效地降低制造成本和制造时间。
请参考图1C至图1G，第一重布线路层300形成于密封材料组合物200’的第一表面202上。请参考图1C至图1G，在一些实施例中，可以利用化学机械研磨工艺(chemical-mechanical polishing process；CMP process)、机械研磨工艺(mechanical grindingprocess)或其他适宜的薄化工艺，减少密封材料组合物200’的厚度以暴露出半导体管芯100上的这些导电凸块108。在密封材料组合物200’通过上述工艺暴露出这些导电凸块108之后，形成包括介电层310以及图案化导电层320的第一重布线路层300。在密封材料组合物200’的第一表面202上形成介电材料，接着，移除部分的介电材料以形成介电层310，介电层310可以暴露出至少一部分的导电路径230和至少一部分的导电凸块108。
请参考图1D至图1E，通过沉积工艺或其他适宜的工艺可以在介电层310上共形地(conformally)形成晶种层(seed layer)322。在晶种层322上可以形成图案化光刻胶层PR’来覆盖部分的晶种层322。接下来，通过电镀工艺(plating process)或其他适宜的工艺，于被图案化光刻胶层PR’暴露出的晶种层322上可以形成导电层324。在形成导电层324后，从晶种层322上剥除图案化光刻胶层PR’，如图1F所示。随后，通过刻蚀工艺(etchingprocess)或其他适宜的工艺来移除未被导电层324所覆盖的晶种层322，以形成图案化导电层320，如图1G所示。图案化导电层320可以电性连接于密封材料组合物200’中的这些导电路径230与半导体管芯100的这些导电凸块108。在一些实施例中，图案化导电层320可以在形成介电层310之前先形成。图案化导电层320以及介电层310的形成顺序可以视设计需求而定，于本发明并不加以限制。上述的步骤可以重复多次，以形成电路设计所须的多层(multi-layered)重布线路层(第一重布线路层300)。
请参考图1H至图1I，在形成第一重布线路层300之后，第一钝化层410形成在相对于密封材料组合物200’的第一重布线路层300上，以保护第一重布线路层300。第一钝化层410可以具有至少暴露出部分的图案化导电层320的多个开口410a。第一钝化层410的材料可以包含环氧树脂(epoxy resin)、聚酰亚胺(polyimide)、聚苯恶唑(polybenzoxazole；PBO)、苯并环丁烯(benzocyclobutene；BCB)或其他适宜的材料。导电端子500可以在第一钝化层410对应于这些开口410a的位置上，利用电镀工艺、植球工艺(ball placementprocess)或其他适宜的工艺来形成。在一些实施例中，导电端子500可以与图案化导电层320直接接触并电性连接至第一重布线路层300。导电端子500可以包含导电球、导电柱、导电凸块或其组合，但本发明不以此为限。导电端子500可以依据设计需求而具有其他可能的形式以及形状。在一些实施例中，可以选择性地进行焊接工艺(soldering process)以及回焊工艺(reflowing process)，以提升导电端子500与图案化导电层320之间的结合性。
请参考图1J至图1K，在形成导电端子500后，第二临时载板60可以通过粘着层54附着于导电端子500。在一些实施例中，离型层52可以被设置于粘着层54与第二临时载板60之间，以提升两者之间的离型能力。接着，可以移除第一临时载板50。在第一临时载板50与密封材料组合物200’之间可以施加例如紫外光激光、可见光或热等外部能量，来剥离两者之间的数层(例如离型层52和粘着层54)。在移除第一临时载板50后，暴露出密封材料组合物200’的第二表面204，且密封材料组合物200’的第二表面204与半导体管芯100的背面104共平面(coplanar)。
请参考图1L，在密封材料组合物200’的第二表面204上形成第二重布线路层600。第二重布线路层600可以包括介电层610以及图案化导电层620。图案化导电层620可以通过密封材料组合物200’中的这些导电路径230与第一重布线路层300电性连接。第二重布线路层600的形成方式与第一重布线路层300类似，为简洁起见，于此不再赘述。
请参考图1M，第二钝化层420可以形成在相对于密封材料组合物200’的第二重布线路层600上。在一些实施例中，第二钝化层420可以具有至少暴露出部分的图案化导电层320的多个开口420a，以作为后续进一步地电性连接。第二钝化层420的形成方式与第一钝化层410类似，为简洁起见，于此不再赘述。
请参考图1N，可以移除第二临时载板60。于此，便实质上完成半导体封装结构10的工艺。在第二临时载板60与导电端子500之间可以施加例如紫外光激光、可见光或热等外部能量来剥离两者之间的数层(例如离型层52和粘着层54)。
综合上述，在特定工艺完成后，半导体管芯被密封材料组合物所密封，而此密封材料组合物既可以作为绝缘封装材料，也可以提供导电路径。此外，可以通过调整工艺参数来获得各种尺寸的导电路径。因此，可以省略传统的镀铜工艺，进而简化半导体封装工艺。另外，密封材料组合物可以使因热膨胀系数不匹配所带来的影响最小化，进一步减少翘曲问题的产生。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种密封材料组合物，适于密封半导体管芯，所述密封材料组合物，其特征在于，包括：
感光性介电材料；以及
可极化的化合物，悬浮于所述感光性介电材料中，其中所述可极化的化合物在所述密封材料组合物的预定区域之中受到外部刺激的影响，而在所述密封材料组合物的厚度方向上呈规则地排列以提供导电路径，所述导电路径是沿着所述厚度方向穿透所述感光性介电材料。
2.根据权利要求1所述的密封材料组合物，其特征在于，其中所述可极化的化合物包括异向性导电粒子，且所述可极化的化合物占所述密封材料组合物的体积百分比介于50％至70％之间。
3.根据权利要求2所述的密封材料组合物，其特征在于，其中所述可极化的化合物还包括与所述异向性导电粒子混合的碳纳米结构。
4.一种半导体封装，其特征在于，包括：
半导体管芯；
如权利要求1所述的密封材料组合物，密封所述半导体管芯；
第一重布线层，设置于所述密封材料组合物的第一表面上，且所述第一重布线层电性连接于所述密封材料组合物及所述半导体管芯；以及
第二重布线层，设置于所述密封材料组合物相对于所述第一表面的第二表面上，且所述第二重布线层通过所述密封材料组合物与所述第一重布线层电性连接。
5.根据权利要求4所述的半导体封装，其特征在于，其中所述第一重布线层与所述第二重布线层通过所述密封材料组合物的所述导电路径电性连接，所述导电路径由受到所述外部刺激的影响的所述密封材料组合物的所述预定区域所提供。
6.一种半导体封装的制造方法，其特征在于，包括：
通过密封材料组合物密封半导体管芯，其中所述密封材料组合物包括感光性介电材料以及与所述感光性介电材料混合的可极化的化合物；
极化所述密封材料组合物的预定区域，以形成围绕所述半导体管芯的导电路径；
形成第一重布线层于所述密封材料组合物的第一表面上，以电性连接所述半导体管芯和所述密封材料组合物中的所述导电路径；以及
形成第二重布线层于所述密封材料组合物相对于所述第一表面的第二表面上，以电性连接所述密封材料组合物中的所述导电路径。
7.根据权利要求6所述的半导体封装的制造方法，其特征在于，还包括：
于极化所述密封材料组合物期间，对所述密封材料组合物的所述预定区域进行曝光制造；
于所述曝光制造之后，对所述密封材料组合物进行显影制造；以及
于所述显影制造之后，对所述密封材料组合物进行固化制造。
8.根据权利要求6所述的半导体封装的制造方法，其特征在于，其中所述半导体管芯的侧面和所述密封材料组合物的所述预定区域之间具有水平间距，于极化所述密封材料组合物期间，所述水平间距的范围约为0.5mm至1mm。
9.根据权利要求6所述的半导体封装的制造方法，其特征在于，其中在极化所述密封材料组合物的所述预定区域之前，所述可极化的化合物悬浮于所述感光性介电材料中。
10.根据权利要求6所述的半导体封装的制造方法，其特征在于，其中在极化所述密封材料组合物的所述预定区域之后，所述可极化的化合物在所述密封材料组合物的厚度方向上呈规则地排列以形成所述导电路径，所述导电路径沿着所述厚度方向穿透所述感光性介电材料。
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