CN109817595A - 集成电路封装件及其形成方法 - Google Patents

集成电路封装件及其形成方法 Download PDF

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Publication number
CN109817595A
CN109817595A CN201810438653.6A CN201810438653A CN109817595A CN 109817595 A CN109817595 A CN 109817595A CN 201810438653 A CN201810438653 A CN 201810438653A CN 109817595 A CN109817595 A CN 109817595A
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China
Prior art keywords
integrated circuit
layer
circuit die
conductive
opening
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CN201810438653.6A
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English (en)
Inventor
余振华
郭宏瑞
何明哲
李宗徽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to CN202210469408.8A priority Critical patent/CN114823610A/zh
Publication of CN109817595A publication Critical patent/CN109817595A/zh
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Abstract

本发明实施例提供了一种集成电路封装件及其形成方法。一种方法包括在载体上方形成第一再分布层，第一再分布层包括接触焊盘和接合焊盘。在接触焊盘上方形成导电柱。使用焊料接头将集成电路管芯的背面附接至接合焊盘。沿着导电柱的侧壁和集成电路管芯的侧壁形成密封剂，集成电路管芯的正面与密封剂的最顶面和导电柱的最顶面大致齐平。在集成电路管芯的正面、密封剂的最顶面和导电柱的最顶面上方形成第二再分布层。

Description

集成电路封装件及其形成方法
技术领域
本发明实施例涉及集成电路封装件及其形成方法。
背景技术
半导体器件用在诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层，并且使用光刻图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。通常，在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后，以多芯片模块或以封装的其他类型来将单独的管芯分别进行封装。
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体行业已经历了快速的发展。在很大程度上，集成密度的这种提高源自最小部件尺寸的重复减小(例如，将半导体工艺节点减小至亚20nm节点)，这允许在给定区域中集成更多的组件。由于最近对微型化、更高速度和更大带宽以及更低功耗和延迟的需求不断增长，因此亟需用于半导体管芯的更小且更具创造性的封装技术。
随着半导体技术的进一步发展，已经出现了堆叠的半导体器件(例如，三维集成电路(3DIC))作为有效替代以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，在不同半导体晶圆上制造诸如逻辑、存储器、处理器电路等的有源电路。两个或更多的半导体晶圆可以安装或堆叠在彼此的顶部上以进一步降低半导体器件的形状因数。叠层封装(POP)器件是一种类型的3DIC，其中，封装管芯并且然后将管芯与另一封装的一个管芯或多个管芯封装在一起。封装件上芯片(COP)器件是另一类型的3DIC，其中，封装管芯并且然后将管芯与另一管芯或多个管芯封装在一起。
发明内容
根据本发明的一些实施例，提供了一种形成半导体结构的方法，包括：在载体上方形成第一再分布层，所述第一再分布层包括接触焊盘和接合焊盘；在所述接触焊盘上方形成导电柱；使用焊料接头将集成电路管芯的背面附接至所述接合焊盘；沿着所述导电柱的侧壁和所述集成电路管芯的侧壁形成密封剂，所述集成电路管芯的正面与所述密封剂的最顶面和所述导电柱的最顶面齐平；以及在所述集成电路管芯的正面、所述密封剂的最顶面和所述导电柱的最顶面上方形成第二再分布层。
根据本发明的另一些实施例，还提供了一种形成半导体结构的方法，包括：在载体上方形成绝缘层；在所述绝缘层上方形成晶种层；在所述晶种层上方形成第一图案化掩模，所述第一图案化掩模具有第一开口和第二开口，所述第一开口和所述第二开口暴露所述晶种层；在所述第一开口和所述第二开口中沉积第一导电材料以在所述第一开口中形成第一导电部件并且在所述第二开口中形成第二导电部件；去除所述第一图案化掩模；在所述晶种层、所述第一导电部件和所述第二导电部件上方形成第二图案化掩模，所述第二图案化掩模具有第三开口，所述第三开口暴露所述第一导电部件；在所述第三开口中沉积第二导电材料以在所述第三开口中形成导电柱；去除所述第二图案化掩模；去除所述晶种层的暴露部分；以及使用焊料接头将集成电路管芯的背面附接至所述第二导电部件。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：集成电路管芯，所述集成电路管芯具有前侧和与所述前侧相对的背侧，所述集成电路管芯具有位于所述前侧上的多个接触部件；密封剂，沿着所述集成电路管芯的侧壁延伸；第一再分布层，位于所述集成电路管芯的背侧上，所述第一再分布层包括接触焊盘和接合焊盘；焊料接头，插接在所述集成电路管芯的背侧和所述接合焊盘之间；第二再分布层，位于所述集成电路管芯的前侧上；以及导电通孔，位于所述密封剂内，所述导电通孔从所述第一再分布层延伸至所述第二再分布层。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图10是根据一些实施例的在集成电路管芯的制造期间的各个处理步骤的截面图。
图11至图21是根据一些实施例的在集成电路封装件的制造期间的各个处理步骤的截面图。
图22至图23是根据一些实施例的在集成电路封装件的制造期间的各个处理步骤的截面图。
图24示出根据一些实施例的形成集成电路管芯的方法的流程图。
图25示出根据一些实施例的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
将相对于特定的上下文中的实施例描述实施例，即诸如集成扇出(InFO)封装件和包括InFO封装件的PoP封装件的集成电路封装件。然而，其他实施例也可以应用于其他电连接的组件，包括，但不限于，叠层封装组件、管芯至管芯组件、晶圆至晶圆组件、管芯至衬底组件、组装封装件、处理衬底、内插器等，或者安装输入组件、板、管芯或其他组件，或用于封装或安装任何类型的集成电路或电子组件的组合的连接件。
本文描述的各个实施例允许使用管芯附接方法来形成集成电路封装件，其中，管芯附接方法允许通过减少或消除管芯和下面的层(诸如下面的再分布层)之间的重叠偏移来减少或避免管芯对准问题，并且允许用于降低集成电路封装件的热阻。这里描述的各个实施例还允许直接在下面的再分布层上形成模制贯通孔，并且通过修改在形成再分布层期间使用的晶种层来降低接触电阻。这里描述的各个实施例还允许减少用于形成集成电路封装件的制造步骤的数量和制造成本。
图1至图10是根据一些实施例的在集成电路管芯的制造期间的各个处理步骤的截面图。参考图1，示出通过划线103(还称为切割线或切割区)分离的具有管芯区101的工件100的部分。如下文更详细描述的，将沿着划线103切割工件100以形成单独的集成电路管芯(诸如图9中示出的集成电路管芯901)。在一些实施例中，工件100包括衬底105、位于衬底105上的一个或多个有源和/或无源器件107以及位于衬底105和一个或多个有源和/或无源器件107上方的互连结构109。
在一些实施例中，衬底105可由硅形成，尽管它还可由诸如硅、锗、镓、砷的其他第III族、第IV族和/或第V族元素及其它们的组合形成。衬底105还可为绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(例如，掩埋氧化物等)上方的半导体材料层(例如，硅、锗等)，其中，绝缘层形成在硅衬底上。此外，可使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、它们的任何组合等。
在一些实施例中，一个或多个有源和/或无源器件107可以形成在衬底105上并且可以包括诸如晶体管、电容器、电阻器、二极管、光电二级管、熔丝等的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件。在一些实施例中，可以使用任何可接受的方法来形成一个或多个有源和/或无源器件107。本领域的普通技术人员应该理解，提供的以上实例仅是为了说明的目的，并不旨在以任何方式限制本发明。还可以形成其他电路以适当地用于给定应用。
在一些实施例中，可以在衬底105和一个或多个有源和/或无源器件107上方形成互连结构109。互连结构109电互连一个或多个有源和/或无源器件107以在工件100内形成功能电路。互连结构109可以包括一个或多个介电层(未示出)和位于相应的介电层内的一个或多个金属化层(未示出)。一个或多个介电层可以包括形成在衬底和一个或多个有源和/或无源器件上方的层间介电(ILD)层/金属间介电(IMD)层。例如，可以通过诸如，旋涂方法、化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、它们的组合等的本领域已知的任何合适的方法由诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等的低K介电材料形成ILD/IMD层。在一些实施例中，一个或多个金属化层可以包括使用例如镶嵌工艺、双镶嵌工艺、它们的组合等形成在ILD/IMD中的各个导电部件(诸如ILD中的导电接触件和IMD中的导线和通孔)。在一些实施例中，导电部件可以包括铜、铜合金、银、金、钨、钽、铝或它们的组合等。
在一些实施例中，在互连结构109上方形成接触焊盘111。接触焊盘111可以通过互连结构109的一个或多个金属化层电连接至一个或多个有源和/或无源器件107。在一些实施例中，接触焊盘111可以包括诸如铝、铜、钨、银、金、它们的组合等的导电材料。在一些实施例中，可以使用例如物理汽相沉积(PVD)、原子层沉积(ALD)、电化学镀、化学镀、它们的组合等在互连结构109上方形成导电材料。后续地，图案化导电材料以形成接触焊盘111。在一些实施例中，可使用合适的光刻和蚀刻技术来图案化导电材料。通常，光刻技术包括沉积光刻胶材料(未示出)，后续照射(曝光)和显影光刻胶材料以去除光刻胶材料的部分。剩余的光刻胶材料保护下面的材料(诸如接触焊盘111的导电材料)免于后续的诸如蚀刻的处理步骤。可以将诸如反应离子蚀刻(RIE)或其他干蚀刻、各向同性或各向异性的湿蚀刻的合适的蚀刻工艺或任何其他合适的蚀刻或图案化工艺应用于导电材料，以去除导电材料的暴露部分，从而形成接触焊盘111。后续地，可使用例如灰化工艺和之后的湿清洁工艺去除光刻胶材料。
进一步参考图1，在互连结构109和接触焊盘111上方形成钝化层113。在一些实施例中，钝化层113可以包括诸如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)、它们的组合等的一层或多层不可光图案化的介电材料，并且可以使用CVD、PVD、ALD、旋涂工艺、它们的组合等来形成。在其他实施例中，钝化层113可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化的绝缘材料，并且可以使用旋涂工艺等来形成。可使用与光刻胶材料类似的光刻方法来图案化这种可光图案化的介电材料。
在一些实施例中，在钝化层113中形成开口115以暴露接触焊盘111的部分。在其中钝化层113包括不可光图案化的介电材料的一些实施例中，可以使用合适的光刻和蚀刻方法来图案化钝化层113。在一些实施例中，在钝化层113上方形成光刻胶材料(未示出)。后续照射(曝光)和显影光刻胶材料以去除光刻胶材料的部分。后续地，使用例如合适的蚀刻工艺去除钝化层113的暴露部分以形成开口115。
参考图2，在钝化层113和接触焊盘111上方形成缓冲层201。在一些实施例中，缓冲层201可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化的绝缘材料，并且可以使用旋涂工艺等来形成。在一些实施例中，图案化缓冲层201以在缓冲层201中形成开口203并暴露接触焊盘111。在一些实施例中，可以使用合适的光刻技术以将缓冲层201暴露于光来形成开口203。在一些实施例中，在曝光之后，显影和/或固化缓冲层201。
参照图3，在缓冲层201上方且在开口203中毯式沉积晶种层301。晶种层301可以包括铜、钛、镍、金、锰、它们的组合等的一层或多层，并且可以通过ALD、PVD、溅射、它们的组合等形成。在一些实施例中，晶种层301包括形成在钛层上方的铜层。
参考图4，在晶种层301上方形成其中具有开口403的图案化掩模401。在一些实施例中，图案化掩模401包括光刻胶材料或任何可光图案化的材料。在一些实施例中，沉积图案化掩模401的材料，照射(曝光)和显影以去除部分材料并且形成开口403，由此形成图案化掩模401。在所示实施例中，开口403暴露晶种层301的形成在接触焊盘111上方且在开口203中的部分。如以下更详细讨论的，将在开口403中形成导电柱(诸如图5中所示的导电柱501)以提供至接触焊盘111的电连接。
参考图5，在由开口403和203形成的组合开口中(参见图4)形成导电柱501。在一些实施例中，使用电化学镀工艺、化学镀工艺、ALD、PVD它们的组合等用诸如铜、钨、铝、银、金、它们的组合等的导电材料填充组合开口以形成导电柱501。在一些实施例中，导电柱501部分地填充组合开口，并且组合开口的剩余部分填充有焊料材料以在导电柱501上方形成焊料层503。在一些实施例中，焊料材料可以是诸如PbSn组分的铅基焊料，包括InSb、锡、银和铜(“SAC”)组分的无铅焊料，以及具有共同熔点并且在电气应用中形成导电焊料连接件的其他共晶材料。作为实例，对于无铅焊料，可以使用组分变化的SAC焊料，诸如SAC 105(锡98.5％、银1.0％、铜0.5％)、SAC 305和SAC 405。无铅焊料还包括不使用银(Ag)的SnCu化合物和不使用铜(Cu)的SnAg化合物。在一些实施例中，可以使用蒸发、电化学镀工艺、化学镀工艺、印刷、焊料转移、它们的组合等来形成焊料层503。
参考图6，在形成导电柱501和焊料层503之后，去除图案化掩模401(参见图5)。在一些实施例中，使用例如灰化工艺，接着通过湿清洁工艺去除包括光刻胶材料的图案化掩模401。后续地，使用例如合适的蚀刻工艺去除晶种层301的暴露部分。在一些实施例中，在去除晶种层301的暴露部分之后，可以电测试每个管芯区101以识别已知良好管芯(KGD)，从而用于进一步的处理。在一些实施例中，电测试系统的探针卡可以在电测试工艺期间接触焊料层503。在一些实施例中，在完成电测试工艺之后，从相应的导电柱501去除焊料层503。在一些实施例中，可以使用诸如，例如合适的蚀刻工艺的合适的去除工艺来去除焊料层503。在所示实施例中，在完成电测试工艺之后立即去除焊料层503。在其他实施例中，诸如，例如可以在后续的封装步骤期间的制造工艺的稍后步骤中去除焊料层503。
参考图7，在去除焊料层503之后，在导电柱501上方并围绕导电柱501形成保护层701。在一些实施例中，保护层701可以包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、它们的组合等的一层或多层可光图案化的绝缘材料，并且可以使用旋涂工艺等来形成。
进一步参考图7，在一些实施例中，例如期望背面研磨衬底105，以减小工件100的厚度和后续形成的集成电路管芯的厚度。在这种实施例中，实施削薄工艺，其中，将诸如背面研磨(BG)带的带703施加至保护层701的顶面，并且通过研磨、蚀刻、CMP工艺、它们的组合等削薄衬底105的背侧105b。在一些实施例中，带703保护工件100免受由研磨/蚀刻流体和/或碎屑引起的污染。
参考图8，在完成上述削薄工艺之后，在衬底105的背侧105b上形成晶种层801。在一些实施例中，可以使用与以上参考图3描述的晶种层301类似的材料和方法来形成晶种层801，并且在此不重复描述。在一些实施例中，晶种层801可以具有在约0.06μm和约1.1μm之间的厚度。在一些实施例中，晶种层801可以包括厚度在约0.01μm和约0.1μm之间的钛层，以及厚度在约0.05μm和约1μm之间的铜层。
参考图9，在形成晶种层801之后，去除带703(参见图8)并且分割工件100以形成单独的集成电路管芯901。在一些实施例中，可以使用粘合剂905将工件100附接至框架903以准备用于后续的切割工艺的工件100。在一些实施例中，框架903可以是薄膜框架或任何合适的载体以为后续操作(诸如切割)提供机械支撑。粘合剂905可以是管芯附接膜、切割膜或任何合适的粘合剂、环氧树脂、紫外(UV)胶(当暴露于UV辐射时失去其粘合性)等，并且可以使用沉积工艺、旋涂工艺、印刷工艺、层压工艺等来形成。在一些实施例中，粘合剂905可以具有多层结构并且可以包括释放层(未示出)。在完成切割工艺之后，释放层有助于安全地从框架903去除单独的集成电路管芯901。在一些实施例中，释放层可以是UV型，其中在将释放层暴露于UV辐射之后，释放层的粘合强度大幅降低。在其他实施例中，释放层可以是热型，其中，在将释放层暴露于合适的热源之后，释放层的粘合强度大幅降低。在一些实施例中，可以例如通过锯切、激光烧蚀、它们的组合等将工件100分割为单独的集成电路管芯901。
如图9所示，每个集成电路管芯901包括单个钝化层(诸如钝化层113)、单个缓冲层(诸如缓冲层201)、两个接触焊盘(诸如接触焊盘111)、两个导电柱(诸如导电柱501)以及单个保护层(诸如保护层701)。本领域技术人员将意识到提供的钝化层、缓冲层、接触焊盘、导电柱和保护层的数量仅用于说明目的，并不限制本发明的范围。在其他实施例中，根据集成电路管芯901的设计要求，每个集成电路管芯901可以包括适当数量的钝化层、缓冲层、接触焊盘、导电柱和保护层。
参考图10，在将工件100分割成集成电路管芯901之后，将焊膏1001施加至每个集成电路管芯901的晶种层801。在一些实施例中，可以使用印刷工艺、浸渍工艺、它们的组合等将焊膏1001施加至晶种层801。在一些实施例中，焊膏1001可以包括焊料材料和焊剂。在其他实施例中，焊膏1001可以是无焊剂焊膏。在一些实施例中，焊膏1001的焊料材料可以包括与以上参考图5描述的焊料层503类似的材料，并且在此不重复描述。在一些实施例中，焊膏1001可以具有在约5μm和约100μm之间的厚度。
进一步参考图9和图10，在所示实施例中，在将工件100分割成集成电路管芯901之后，将焊膏1001施加至集成电路管芯901。在其他实施例中，可以在将工件100分割成集成电路管芯901之前将焊膏1001施加至工件100。在这样的实施例中，切割锯在分割工艺期间可能被焊膏1001污染。在一些实施例中，可以对切割锯实施合适的清洁工艺以从切割锯去除污染物。如以下更详细描述的，在后续的封装步骤期间，焊膏1001可以用于将集成电路管芯901附接至下面的再分布层。
图11至图21是根据一些实施例的在使用图1-图10中制造的集成电路管芯制造集成电路封装件期间的各个处理步骤的截面图。首先参考图11，在一些实施例中，在载体1101上方形成释放层1103，并在释放层1103上方形成绝缘层1105以开始形成集成电路封装件。在一些实施例中，载体1101可由石英、玻璃等形成，并且为后续的操作提供机械支撑。在一些实施例中，释放层1103可包括光热转换(LTHC)材料、UV粘合剂、聚合物层等，并且可使用旋涂工艺、印刷工艺、层压工艺等形成。在其中释放层1103由LTHC材料形成的一些实施例中，当释放层1103暴露于光时，释放层1103部分地或完全地丧失其粘合强度，并且可从后续形成的结构的背侧容易地去除载体1101。在一些实施例中，可以使用与以上参考图2描述的缓冲层201类似的材料和方法来形成缓冲层1105，并且在此不重复描述。
进一步参考图11，在绝缘层1105上方形成晶种层1107。在一些实施例中，可以使用与以上参考图3描述的晶种层301类似的材料和方法来形成晶种层1107，并且在此不重复描述。在一些实施例中，晶种层1107可以包括厚度在约0.01μm和约0.1μm之间的钛层，以及厚度在约0.06μm和约1.1μm之间的铜层。在一些实施例中，可以省略钛层，并且晶种层1107可以包括厚度在约0.12μm和约0.7μm之间的铜层。在这样的实施例中，通过省略钛层，可以减小所得到的再分布层的接触电阻。
在一些实施例中，在晶种层1107上方形成具有位于其中的开口1111和1113的图案化掩模1109。在一些实施例中，可以使用与以上参考图4描述的图案化掩模401类似的材料和方法来形成图案化掩模1109，并且在此不重复描述。在所示实施例中，图案化掩模401包括光刻胶材料并且使用合适的光刻方法进行图案化。如以下更详细描述的，在开口1111和1113中形成导电材料以形成再分布层。在一些实施例中，形成在开口1111中的导电材料可形成接触焊盘，其提供至后续形成的导电通孔的电连接。在一些实施例中，形成在开口1113中的导电材料可以形成接合焊盘，集成电路管芯后续附接至该接合焊盘。在一些实施例中，开口1111的宽度W1可以小于开口1113的宽度W2。在一些实施例中，宽度W1可以在约120μm和约500μm之间。在一些实施例中，宽度W2可以在约0.5mm和约2mm之间。在一些实施例中，比率W1/W2可以在约0.06和约1之间。
参考图12，在开口1111和1113中形成导电材料1201。在一些实施例中，导电材料1201可以包括铜、钨、铝、银、金、它们的组合等，并且可以使用电化学镀工艺、化学镀工艺、ALD、PVD、它们的组合等来形成。在一些实施例中，导电材料1201包括形成在开口1111内的第一部分1201a和形成在开口1113内的第二部分1201b。在一些实施例中，导电材料1201的第一部分1201a可以具有与开口1111大致相同的宽度。在一些实施例中，导电材料1201的第二部分1201b可以具有与开口1113大致相同的宽度。
参考图13，在形成导电材料1201之后，去除图案化掩模1109(参见图12)。在一些实施例中，可以使用与以上参考图6描述的图案化掩模401类似的方法来去除图案化掩模1109，并且在此不重复描述。在一些实施例中，在去除图案化掩模1109之后，在晶种层1107和导电材料1201上方形成具有位于其中的开口1303的图案化掩模1301。在一些实施例中，可以使用与以上参考图4描述的图案化掩模401类似的材料和方法来形成图案化掩模1301，并且在此不重复描述。在所示实施例中，图案化掩模1301包括干式可光图案化的膜，其被层压在晶种层1107和导电材料1201上方，并且可以使用合适的光刻方法进行图案化。在一些实施例中，图案化掩模1301保护导电材料1201的第二部分1201b并且通过相应开口1303暴露导电材料1201的第一部分1201a。在一些实施例中，开口1303可具有在约100μm和约300μm之间的宽度W3。
参考图14，在开口1303中形成导电柱1401。在一些实施例中，可以使用与以上参考图5描述的导电柱501类似的材料和方法形成导电柱1401，并且在此不重复描述。在一些实施例中，导电柱1401也可以称为导电通孔1401或模制贯通孔1401。在一些实施例中，导电柱1401可以具有与开口1303大致相同的宽度。
参考图15，在形成导电柱1401之后，去除图案化掩模1301(参见图14)。在其中图案化掩模1301包括干式可光图案化的膜的一些实施例中，可以使用例如灰化工艺以及之后的湿清洁工艺来去除图案化掩模1301。后续地，去除晶种层1107的暴露部分。在一些实施例中，可以使用与以上参考图6描述的晶种层301的暴露部分的类似的方法去除晶种层1107的暴露部分，并且在此不重复描述。在一些实施例中，在去除工艺之后，保留由导电材料1201的第一部分1201a保护的晶种层1107的第一部分1107a和由导电材料1201的第二部分1201b保护的晶种层1107的第二部分1107b。在一些实施例中，导电材料1201和晶种层1107的剩余部分可以统称为再分布层(RDL)1501。在一些实施例中，RDL 1501和绝缘层1105可以统称为再分布结构1503。在一些实施例中，导电材料1201的第一部分1201a和晶种层1107的相应第一部分1107a可以称为RDL 1501的接触焊盘1501a。在一些实施例中，导电材料1201的第二部分1201b和晶种层1107的相应第二部分1107b可以称为RDL 1501的接合焊盘1501b。在一些实施例中，接触焊盘1501a电连接至相应的导电柱1401。如以下更详细描述的，集成电路管芯在后续工艺中接合至接合焊盘1501b。在一些实施例中，接触焊盘1501a可以彼此电连接。在一些实施例中，接合焊盘1501b的每个可以与其他接合焊盘1501b和接触焊盘1501a的每个电隔离。在其他实施例中，接触焊盘1501a和接合焊盘1501b可以彼此电连接。
如图15所示，再分布结构1503包括一个绝缘层(诸如绝缘层1105)和一个RDL(诸如RDL 1501)。本领域技术人员将意识到，绝缘层的数量和RDL的数量仅用于说明的目的，并不限制本发明的范围。在其他实施例中，根据所得到的封装器件的设计要求，再分布结构可以包括适当数量的绝缘层和RDL。
参考图16，集成电路管芯901(参见图10)附接至RDL 1501的相应接合焊盘1501b。在一些实施例中，使用例如拾取和放置装置将集成电路管芯901放置在RDL 1501的相应接合焊盘1501b上。在其他实施例中，可以手动地或使用任何其他合适的方法将集成电路管芯901放置在RDL1501的相应的接合焊盘1501b上。在一些实施例中，在将集成电路管芯901放置在RDL 1501的相应接合焊盘1501b上之后，对焊膏1001实施回流工艺(参见图10)以形成将集成电路管芯901附接至RDL 1501的相应接合焊盘1501b的焊料接头1601。在一些实施例中，焊料接头1601的宽度与集成电路管芯901的宽度大致相同。在一些实施例中，可以在约110℃和约260℃之间的温度处实施回流工艺。在一些实施例中，回流工艺在焊料接头1601与相应晶种层801之间的界面处以及在焊料接头1601与RDL 1501的相应接合焊盘1501b之间的界面处形成金属间化合物(未示出)。通过使用焊料接头1601代替粘合膜(诸如，例如管芯附接膜)来附接集成电路管芯901，热阻可以减小约1.2％。在一些实施例中，在将集成电路管芯901放置在RDL 1501的相应接合焊盘1501b上之后，集成电路管芯901可能相对于RDL1501的相应接合焊盘1501b未对准。在一些实施例中，回流工艺可减少集成电路管芯901与RDL 1501的相应接合焊盘1501b之间的过度偏移，并且可使集成电路管芯901相对于RDL1501的相应接合焊盘1501b自对准。在所示实施例中，集成电路管芯901的背侧附接至RDL1501的相应接合焊盘1501b。因此，RDL 1501也可以称为背侧RDL 1501，并且再分布结构1503还可以称为背侧再分布结构1503。
参考图17，在载体1101上方并且在集成电路管芯901和导电柱1401的上方和周围形成密封剂1701。在一些实施例中，密封剂1701可包括诸如环氧树脂、树脂、可模制聚合物等的模塑料。可以施加大致为液态的模塑料，然后可以通过诸如在环氧树脂或树脂中化学反应进行固化。在其他实施例中，模塑料可为紫外(UV)固化聚合物或热固化聚合物，该模塑料用作能够设置在集成电路管芯901和导电柱1401周围和之间的凝胶或可塑固体。
参考图18，在一些实施例中，使用CMP工艺、研磨工艺、它们的组合等来平坦化密封剂1701。在一些实施例中，实施平坦化工艺直到暴露集成电路管芯901的导电柱501。在一些实施例中，导电柱501的顶面与导电柱1401的顶面和密封剂1701的顶面大致共面。在以上参考图6描述的电测试工艺之后没有立即去除焊料层503(参见图6)的一些实施例中，平坦化工艺还可以从导电柱501上方去除焊料层503。
参考图19，在集成电路管芯901、导电柱1401和密封剂1701上方形成再分布结构1901。在一些实施例中，再分布结构1901可以包括绝缘层19031-19033和设置在绝缘层19031-19033内的再分布层(RDL)19051和19052(包括导线和通孔)。在一些实施例中，可以使用与以上参考图2描述的缓冲层201类似的材料和方法来形成绝缘层19031-19033，并且在此不重复描述。在一些实施例中，可以使用与以上参考图5描述的导电柱501类似的材料形成RDL 19051和19052，并且在此不重复描述。在所示实施例中，在集成电路管芯901的前侧上形成再分布结构1901。因此，再分布结构1901也可以称为前侧再分布结构1901，并且RDL19051和19052也可以称为前侧RDL 19051和19052。
还参考图19，在一些实施例中，用于形成再分布结构1901的工艺步骤可以包括图案化绝缘层19031以形成位于其中的开口。在一些实施例中，可以使用与例如以上参考图2描述的用于图案化缓冲层201类似的方法来图案化绝缘层19031，并且在此不重复描述。在绝缘层19031上方并且在位于绝缘层19031中的开口中形成RDL 19051以连接导电柱1401和导电柱501。RDL 19051可以包括各种线/迹线(跨过绝缘层19031的顶面“水平地”延伸)和/或通孔(“垂直地”延伸到绝缘层19031中)。在一些实施例中，在绝缘层19031上方并且在位于绝缘层19031内的开口中沉积晶种层(未示出)。可以使用与以上参考图3描述的晶种层301类似的材料和方法来形成晶种层，并且在此不重复描述。后续地，在晶种层上方形成图案化掩模(未示出)以限定RDL 19051的期望图案。在一些实施例中，可以使用与以上参考图4描述的图案化掩模401类似的材料和方法来形成其中具有开口的图案化掩模，并且在此不重复描述。在一些实施例中，通过电化学镀工艺、化学镀工艺、ALD、PVD、溅射、它们的组合等在晶种层上形成导电材料。后续地，去除图案化掩模，并且还去除在去除图案化掩模之后暴露的晶种层的部分。在一些实施例中，可以使用与以上参考图6描述的图案化掩模401类似的方法来去除图案化掩模，并且在此不重复描述。在一些实施例中，可以使用与以上参考图6描述的晶种层301的暴露部分类似的方法去除晶种层的暴露部分，并且在此不重复描述。在一些实施例中，在绝缘层19031和RDL 19051上方形成绝缘层19032、RDL 19052和绝缘层19033，完成再分布结构1901的形成。在一些实施例中，可以使用与RDL 19051类似的方法在绝缘层19032上方形成RDL 19052，并且在此不重复描述。在一些实施例中，RDL 19052延伸穿过绝缘层19032并接触RDL 19051的部分。
如图19所示，再分布结构1901包括三个绝缘层(诸如绝缘层19031-19033)和插接在相应绝缘层之间的两个RDL(诸如RDL 19051和19052)。本领域技术人员将意识到，绝缘层的数量和RDL的数量仅用于说明的目的，并不限制本发明的范围。在其他实施例中，根据所得到的封装器件的设计要求，再分布结构可以包括适当数量的绝缘层和RDL。
还参考图19，凸块下金属件(UBM)1907形成在再分布结构1901上方并与之电连接。在一些实施例中，一组开口可以形成为穿过绝缘层19033以暴露RDL 19052的部分。在一些实施例中，UBM 1907可包括诸如钛层、铜层和镍层的多层导电材料。然而，本领域的普通技术人员将意识到，存在诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置的材料和层的许多合适的布置，这些都适用于形成UBM 1907。可用于UBM 1907的任何合适的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，连接件1909形成在UBM 1907上方并且与之电连接。在一些实施例中，连接件1909可为焊料球、可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍-化学镀钯-浸金技术(ENEPIG)形成的凸块等。在连接件1909由焊料材料形成的一些实施例中，可实施回流工艺以将焊料材料成形为期望的凸块形状。在其他实施例中，可以使用与以上参考图5描述的导电柱501类似的材料和方法形成可以是导电柱的连接件1909，并且在此不重复描述。在连接件1909包括导电柱的一些实施例中，连接件1909可以进一步包括可以形成在导电柱的顶部上的帽层。在一些实施例中，帽层可以包括焊料、镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等、它们的组合等，并且可以使用电化学镀工艺、化学镀工艺、它们的组合等形成。
参考图20，在再分布结构1901上方形成连接件1909之后，将所得到的结构附接至由框架2003支撑的带2005，从而使得连接件1909接触带2005。在一些实施例中，带2005可以包括管芯附接膜、切割带等。后续地，载体1101(参见图19)从所得到的结构脱粘以暴露绝缘层1105。在脱粘载体1101之后，可以切割所得到的结构以形成单独的集成电路封装件2001。在一些实施例中，可通过锯切、激光烧蚀方法、它们的组合等切割所得到的结构。后续地，可测试每个集成电路封装件2001以识别已知良好封装件(KGP)，从而用于进一步的处理。
参考图21，在一些实施例中，利用延伸穿过绝缘层1105中的开口的一组连接件2103将工件2101接合至集成电路封装件2001以形成堆叠的半导体器件2100。在所示实施例中，工件2101是封装件。在其他实施例中，工件2101可以是一个或多个管芯、印刷电路板(PCB)、封装衬底、内插器等。在其中工件2101是封装件的一些实施例中，堆叠的半导体器件2100为叠层封装(PoP)器件。在其中工件2101是管芯的其他实施例中，堆叠的半导体器件2100是封装件上芯片(CoP)器件。在一些实施例中，可使用与以上参考图19描述的连接件1909的材料和方法类似的材料和方法形成连接件2103，并且在此不重复描述。在其他实施例中，可以在以上参考图20描述的切割工艺之前，将工件2101接合至再分布结构1503的RDL1501。
进一步参考图21，底部填充材料2105可以注入或以其他方式形成在工件2101和集成电路封装件2001之间的间隔中并且围绕连接件2103。例如，底部填充材料2105可以是在各个结构之间分配的例如液体环氧树脂、可变形凝胶、硅橡胶等，并且然后将底部填充材料固化至变硬。此外，该底部填充材料2105尤其可用于减少对连接件2103的损坏并保护连接件2103。
图22至图23是根据一些实施例的在集成电路封装件的制造期间的各个处理步骤的截面图。图22示出与图20中所示的结构类似的结构，其中，使用相同的参考标号来标注相同的元件。与图20的结构不同，图22的结构包括背侧再分布结构2203，其中，背侧再分布结构2203包括多个RDL(诸如RDL 1501和2207)以及多个绝缘层(诸如绝缘层1105和2205)。
参考图22，在一些实施例中，在载体1101上方形成绝缘层1105之后并且在以上参考图11-图15的描述形成RDL 1501和导电柱1401之前，在绝缘层1105上方形成RDL 2207并且在RDL 2207上方形成绝缘层2205。在一些实施例中，可以使用与以上参考图11描述的绝缘层1105类似的材料和方法来形成绝缘层2205，并且在此不重复描述。在一些实施例中，可以使用与例如以上参考图19描述的RDL 19051类似的材料和方法形成RDL 2207，并且在此不重复描述。在一些实施例中，在形成RDL 2207和绝缘层2205之后，可以实施以上参考图11-图19描述的工艺步骤以形成图22中所示的结构。本领域技术人员将意识到，提供的RDL和绝缘层的数量仅用于说明的目的，并不限制本发明的范围。在其他实施例中，根据所得到的封装器件的设计要求，再分布结构2203可包括适当数量的RDL和绝缘层。后续地，可以切割所得到的结构以形成单独的集成电路封装件2201。在一些实施例中，可通过锯切、激光烧蚀方法、它们的组合等切割所得到的结构。后续地，可测试每个集成电路封装件2201以识别已知良好封装件(KGP)，从而用于进一步的处理。
参考图23，在一些实施例中，利用延伸穿过位于绝缘层1105中的一组开口的连接件2303将工件2301接合至集成电路封装件2201以形成堆叠的半导体器件2300。在所示实施例中，工件2301是封装件。在其他实施例中，工件2301可以是一个或多个管芯、印刷电路板(PCB)、封装衬底、内插器等。在其中工件2301是封装件的一些实施例中，堆叠的半导体器件2300是叠层封装(PoP)器件。在其中工件2301是管芯的其他实施例中，堆叠的半导体器件2300是封装件上芯片(CoP)器件。在一些实施例中，可使用与上述参考图19描述的连接件1909类似的材料和方法形成连接件2303，并且在此不重复描述。在其他实施例中，可以在以上参考图22描述的切割工艺之前，将工件2301接合至再分布结构2203的RDL 2207。
进一步参考图23，底部填充材料2305可以注入或者以其他方式形成在工件2301和集成电路封装件2201之间的间隔中并且围绕连接件2303。例如，底部填充材料2305可以是在各个结构之间分配的例如液体环氧树脂、可变形凝胶、硅橡胶等，并且然后将底部填充材料固化至变硬。此外，该底部填充材料2305尤其可用于减少对连接件2303的损坏并保护连接件2303。
图24示出根据一些实施例的形成集成电路管芯的方法2400的流程图。该方法从步骤2401开始，在步骤2401中，如上参考图1所述，在衬底(诸如图1所示的衬底105)的前侧(有源侧)上方形成接触焊盘(诸如图1所示的接触焊盘111)。在步骤2403中，如上参考图1-图6所述，在接触焊盘上方形成导电柱(诸如图6所示的导电柱)。在步骤2405中，如上参考图7所述，在导电柱上方和周围形成保护层(诸如图7所示的保护层701)。在步骤2407中，如上参考图7所述，削薄衬底的背侧。在步骤2409中，如上参考图8所述，在衬底的背侧上形成晶种层(诸如图8所示的晶种层801)。在步骤2411中，如上参考图9所述，将衬底分割成多个集成电路管芯(诸如图9所示的集成电路管芯901)。在步骤2413中，如上参考图10所述，将焊膏(诸如图10所示的焊膏1001)施加至多个集成电路管芯的每个晶种层。在可选实施例中，可以交换步骤2411和2413。
图25是示出根据一些实施例的形成集成电路封装件的方法2500的流程图。该方法从步骤2501开始，在步骤2501处，如上参考图11-图15所述，在载体(诸如图15所示的载体1101)上方形成第一再分布层(诸如图15所示的再分布层1501)，第一再分布层包括接触焊盘(诸如图15所示的接触焊盘1501a)和接合焊盘(诸如图15所示的接合焊盘1501b)。在步骤2503中，如上参考图13和图14所述，在接触焊盘上方形成导电柱(诸如图14所示的导电柱1401)。在步骤2505中，如上参考图16所述，使用焊料接头(诸如图16所示的焊料接头1601)将集成电路管芯(诸如图16所示的集成电路管芯901)附接至接合焊盘。在步骤2507中，如上参考图17所述，在导电柱和集成电路管芯上方和周围形成密封剂(诸如图17所示的密封剂1701)。在步骤2509中，如上参考图18和图19所述，在密封剂、导电柱和集成电路管芯上方形成第二再分布层(诸如图19所示的再分布层19051)。
根据实施例，一种方法包括：在载体上方形成第一再分布层，第一再分布层包括接触焊盘和接合焊盘；在接触焊盘上方形成导电柱；使用焊料接头将集成电路管芯的背面附接至接合焊盘；沿着导电柱的侧壁和集成电路管芯的侧壁形成密封剂，集成电路管芯的正面与密封剂的最顶面和导电柱的最顶面大致齐平；以及在集成电路管芯的正面、密封剂的最顶面和导电柱的最顶面上方形成第二再分布层。在实施例中，使用焊料接头将集成电路管芯的背面附接至接合焊盘包括：在集成电路管芯的背面上施加焊膏；将集成电路管芯放置在接合焊盘上方，焊膏与接合焊盘物理接触；以及回流焊膏以形成焊料接头。在实施例中，在载体上方形成第一再分布层包括：在载体上方形成晶种层；在晶种层上方形成第一图案化掩模，第一图案化掩模具有第一开口和第二开口；在第一开口和第二开口中沉积第一导电材料以在第一开口中形成第一导电部件并且在第二开口中形成第二导电部件；去除第一图案化掩模；以及去除晶种层的暴露部分，第一导电部件和晶种层的位于第一导电部件下方的第一部分形成接触焊盘，第二导电部件和晶种层的位于第二导电部件下方的第二部分形成接合焊盘。在实施例中，在接触焊盘上方形成导电柱包括：在晶种层、第一导电部件和第二导电部件上方形成第二图案化掩模，第二图案化掩模具有第三开口，第三开口暴露第一导电部件的部分，第二图案化掩模覆盖第二导电部件；在第三开口中沉积第二导电材料以形成导电柱；并去除第二图案化掩模。在实施例中，导电柱将第一再分布层的接触焊盘电连接至第二再分布层。在实施例中，接合焊盘的宽度大于接触焊盘的宽度。在实施例中，接触焊盘和接合焊盘彼此电隔离。
根据另一实施例，一种方法包括：在载体上方形成绝缘层；在绝缘层上方形成晶种层；在晶种层上方形成第一图案化掩模，第一图案化掩模具有第一开口和第二开口，第一开口和第二开口暴露晶种层；在第一开口和第二开口中沉积第一导电材料以在第一开口中形成第一导电部件并且在第二开口中形成第二导电部件；去除第一图案化掩模；在晶种层、第一导电部件和第二导电部件上方形成第二图案化掩模，第二图案化掩模具有第三开口，第三开口暴露第一导电部件；在第三开口中沉积第二导电材料以在第三开口中形成导电柱；去除第二图案化掩模；去除晶种层的暴露部分；以及使用焊料接头将集成电路管芯的背面附接至第二导电部件。在实施例中，该方法还包括沿着导电柱的侧壁和集成电路管芯的侧壁形成密封剂，集成电路管芯的正面与密封剂的最顶面和导电柱的最顶面大致齐平。在实施例中，该方法还包括在集成电路管芯的正面、密封剂的最顶面和导电柱的最顶面上方形成再分布层。在实施例中，导电柱将再分布层电连接至第一导电部件。在实施例中，使用焊料接头将集成电路管芯的背面附接至第二导电部件包括：在集成电路管芯的背面上施加焊膏；将集成电路管芯放置在第二导电部件上方，焊膏与第二导电部件物理接触；以及回流焊膏以形成焊料接头。在实施例中，将焊膏施加在集成电路管芯的背面上包括将焊膏印刷在集成电路管芯的背面上。在实施例中，在去除晶种层的暴露部分之后，第一导电部件和第二导电部件彼此电隔离。
根据又一实施例，一种半导体结构包括：集成电路管芯，集成电路管芯具有前侧和与前侧相对的背侧，集成电路管芯具有位于前侧上的多个接触部件；密封剂，沿着集成电路管芯的侧壁延伸；第一再分布层，位于集成电路管芯的背侧上，第一再分布层包括接触焊盘和接合焊盘；焊料接头，插接在集成电路管芯的背侧和接合焊盘之间；第二再分布层，位于集成电路管芯的前侧上；以及导电通孔，位于密封剂内，导电通孔从第一再分布层延伸至第二再分布层。在实施例中，导电通孔将第一再分布层的接触焊盘电连接至第二再分布层。在实施例中，接触焊盘和接合焊盘彼此电隔离。在实施例中，密封剂的部分沿着接触焊盘的侧壁和接合焊盘的侧壁延伸。在实施例中，多个接触部件电连接至第二再分布层。在实施例中，焊料接头的宽度与集成电路管芯的宽度大致相同。
还可以包括其他部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以对中间结构和最终结构实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以提高产量并降低成本。
根据本发明的一些实施例，提供了一种形成半导体结构的方法，包括：在载体上方形成第一再分布层，所述第一再分布层包括接触焊盘和接合焊盘；在所述接触焊盘上方形成导电柱；使用焊料接头将集成电路管芯的背面附接至所述接合焊盘；沿着所述导电柱的侧壁和所述集成电路管芯的侧壁形成密封剂，所述集成电路管芯的正面与所述密封剂的最顶面和所述导电柱的最顶面齐平；以及在所述集成电路管芯的正面、所述密封剂的最顶面和所述导电柱的最顶面上方形成第二再分布层。
在上述方法中，使用所述焊料接头将所述集成电路管芯的背面附接至所述接合焊盘包括：在所述集成电路管芯的背面上施加焊膏；将所述集成电路管芯放置在所述接合焊盘上方，所述焊膏与所述接合焊盘物理接触；以及回流所述焊膏以形成所述焊料接头。
在上述方法中，在所述载体上方形成所述第一再分布层包括：在所述载体上方形成晶种层；在所述晶种层上方形成第一图案化掩模，所述第一图案化掩模具有第一开口和第二开口；在所述第一开口和所述第二开口中沉积第一导电材料以在所述第一开口中形成第一导电部件并且在所述第二开口中形成第二导电部件；去除所述第一图案化掩模；以及去除所述晶种层的暴露部分，所述第一导电部件和所述晶种层的位于所述第一导电部件下方的第一部分形成所述接触焊盘，所述第二导电部件和所述晶种层的位于所述第二导电部件下方的第二部分形成所述接合焊盘。
在上述方法中，在所述接触焊盘上方形成所述导电柱包括：在所述晶种层、所述第一导电部件和所述第二导电部件上方形成第二图案化掩模，所述第二图案化掩模具有第三开口，所述第三开口暴露所述第一导电部件的部分，所述第二图案化掩模覆盖所述第二导电部件；在所述第三开口中沉积第二导电材料以形成所述导电柱；以及去除所述第二图案化掩模。
在上述方法中，所述导电柱将所述第一再分布层的所述接触焊盘电连接至所述第二再分布层。
在上述方法中，所述接合焊盘的宽度大于所述接触焊盘的宽度。
在上述方法中，所述接触焊盘和所述接合焊盘彼此电隔离。
根据本发明的另一些实施例，还提供了一种形成半导体结构的方法，包括：在载体上方形成绝缘层；在所述绝缘层上方形成晶种层；在所述晶种层上方形成第一图案化掩模，所述第一图案化掩模具有第一开口和第二开口，所述第一开口和所述第二开口暴露所述晶种层；在所述第一开口和所述第二开口中沉积第一导电材料以在所述第一开口中形成第一导电部件并且在所述第二开口中形成第二导电部件；去除所述第一图案化掩模；在所述晶种层、所述第一导电部件和所述第二导电部件上方形成第二图案化掩模，所述第二图案化掩模具有第三开口，所述第三开口暴露所述第一导电部件；在所述第三开口中沉积第二导电材料以在所述第三开口中形成导电柱；去除所述第二图案化掩模；去除所述晶种层的暴露部分；以及使用焊料接头将集成电路管芯的背面附接至所述第二导电部件。
在上述方法中，还包括沿着所述导电柱的侧壁和所述集成电路管芯的侧壁形成密封剂，所述集成电路管芯的正面与所述密封剂的最顶面和所述导电柱的最顶面齐平。
在上述方法中，还包括在所述集成电路管芯的正面、所述密封剂的最顶面和所述导电柱的最顶面上方形成再分布层。
在上述方法中，所述导电柱将所述再分布层电连接至所述第一导电部件。
在上述方法中，使用所述焊料接头将所述集成电路管芯的背面附接至所述第二导电部件包括：在所述集成电路管芯的背面上施加焊膏；将所述集成电路管芯放置在所述第二导电部件上方，所述焊膏与所述第二导电部件物理接触；以及回流所述焊膏形成所述焊料接头。
在上述方法中，将所述焊膏施加在所述集成电路管芯的背面上包括将所述焊膏印刷在所述集成电路管芯的背面上。
在上述方法中，在去除所述晶种层的暴露部分之后，所述第一导电部件和所述第二导电部件彼此电隔离。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：集成电路管芯，所述集成电路管芯具有前侧和与所述前侧相对的背侧，所述集成电路管芯具有位于所述前侧上的多个接触部件；密封剂，沿着所述集成电路管芯的侧壁延伸；第一再分布层，位于所述集成电路管芯的背侧上，所述第一再分布层包括接触焊盘和接合焊盘；焊料接头，插接在所述集成电路管芯的背侧和所述接合焊盘之间；第二再分布层，位于所述集成电路管芯的前侧上；以及导电通孔，位于所述密封剂内，所述导电通孔从所述第一再分布层延伸至所述第二再分布层。
在上述半导体结构中，所述导电通孔将所述第一再分布层的所述接触焊盘电连接至所述第二再分布层。
在上述半导体结构中，所述接触焊盘和所述接合焊盘彼此电隔离。
在上述半导体结构中，所述密封剂的部分沿着所述接触焊盘的侧壁和所述接合焊盘的侧壁延伸。
在上述半导体结构中，所述多个接触部件电连接至所述第二再分布层。
在上述半导体结构中，所述焊料接头的宽度与所述集成电路管芯的宽度相同。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体结构的方法，包括：
在载体上方形成第一再分布层，所述第一再分布层包括接触焊盘和接合焊盘；
在所述接触焊盘上方形成导电柱；
使用焊料接头将集成电路管芯的背面附接至所述接合焊盘；
沿着所述导电柱的侧壁和所述集成电路管芯的侧壁形成密封剂，所述集成电路管芯的正面与所述密封剂的最顶面和所述导电柱的最顶面齐平；以及
在所述集成电路管芯的正面、所述密封剂的最顶面和所述导电柱的最顶面上方形成第二再分布层。
2.根据权利要求1所述的方法，其中，使用所述焊料接头将所述集成电路管芯的背面附接至所述接合焊盘包括：
在所述集成电路管芯的背面上施加焊膏；
将所述集成电路管芯放置在所述接合焊盘上方，所述焊膏与所述接合焊盘物理接触；以及
回流所述焊膏以形成所述焊料接头。
3.根据权利要求1所述的方法，其中，在所述载体上方形成所述第一再分布层包括：
在所述载体上方形成晶种层；
在所述晶种层上方形成第一图案化掩模，所述第一图案化掩模具有第一开口和第二开口；
在所述第一开口和所述第二开口中沉积第一导电材料以在所述第一开口中形成第一导电部件并且在所述第二开口中形成第二导电部件；
去除所述第一图案化掩模；以及
去除所述晶种层的暴露部分，所述第一导电部件和所述晶种层的位于所述第一导电部件下方的第一部分形成所述接触焊盘，所述第二导电部件和所述晶种层的位于所述第二导电部件下方的第二部分形成所述接合焊盘。
4.根据权利要求3所述的方法，其中，在所述接触焊盘上方形成所述导电柱包括：
在所述晶种层、所述第一导电部件和所述第二导电部件上方形成第二图案化掩模，所述第二图案化掩模具有第三开口，所述第三开口暴露所述第一导电部件的部分，所述第二图案化掩模覆盖所述第二导电部件；
在所述第三开口中沉积第二导电材料以形成所述导电柱；以及
去除所述第二图案化掩模。
5.根据权利要求1所述的方法，其中，所述导电柱将所述第一再分布层的所述接触焊盘电连接至所述第二再分布层。
6.根据权利要求1所述的方法，其中，所述接合焊盘的宽度大于所述接触焊盘的宽度。
7.根据权利要求1所述的方法，其中，所述接触焊盘和所述接合焊盘彼此电隔离。
8.一种形成半导体结构的方法，包括：
在载体上方形成绝缘层；
在所述绝缘层上方形成晶种层；
在所述晶种层上方形成第一图案化掩模，所述第一图案化掩模具有第一开口和第二开口，所述第一开口和所述第二开口暴露所述晶种层；
在所述第一开口和所述第二开口中沉积第一导电材料以在所述第一开口中形成第一导电部件并且在所述第二开口中形成第二导电部件；
去除所述第一图案化掩模；
在所述晶种层、所述第一导电部件和所述第二导电部件上方形成第二图案化掩模，所述第二图案化掩模具有第三开口，所述第三开口暴露所述第一导电部件；
在所述第三开口中沉积第二导电材料以在所述第三开口中形成导电柱；
去除所述第二图案化掩模；
去除所述晶种层的暴露部分；以及
使用焊料接头将集成电路管芯的背面附接至所述第二导电部件。
9.根据权利要求8所述的方法，还包括沿着所述导电柱的侧壁和所述集成电路管芯的侧壁形成密封剂，所述集成电路管芯的正面与所述密封剂的最顶面和所述导电柱的最顶面齐平。
10.一种半导体结构，包括：
集成电路管芯，所述集成电路管芯具有前侧和与所述前侧相对的背侧，所述集成电路管芯具有位于所述前侧上的多个接触部件；
密封剂，沿着所述集成电路管芯的侧壁延伸；
第一再分布层，位于所述集成电路管芯的背侧上，所述第一再分布层包括接触焊盘和接合焊盘；
焊料接头，插接在所述集成电路管芯的背侧和所述接合焊盘之间；
第二再分布层，位于所述集成电路管芯的前侧上；以及
导电通孔，位于所述密封剂内，所述导电通孔从所述第一再分布层延伸至所述第二再分布层。
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