CN106549004A - 具有对准标记的集成电路管芯及其形成方法 - Google Patents

具有对准标记的集成电路管芯及其形成方法 Download PDF

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Publication number
CN106549004A
CN106549004A CN201610600014.6A CN201610600014A CN106549004A CN 106549004 A CN106549004 A CN 106549004A CN 201610600014 A CN201610600014 A CN 201610600014A CN 106549004 A CN106549004 A CN 106549004A
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China
Prior art keywords
substrate
alignment mark
tube core
integrated circuit
circuit lead
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CN201610600014.6A
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English (en)
Inventor
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106549004A publication Critical patent/CN106549004A/zh
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Abstract

本发明提供了具有对准标记的集成电路管芯及其形成方法。方法包括在衬底上形成器件。在衬底和器件上方形成多个接触焊盘。与形成多个接触焊盘同时，在衬底和器件上方形成一个或多个对准标记。

Description

具有对准标记的集成电路管芯及其形成方法
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及具有对准标记的集成电路管芯及其形成方法。
背景技术
半导体器件用于许多电子应用，诸如个人计算机、手机、数码相机和其他电子设备。通常，通过在半导体衬底上方相继沉积绝缘层或介电层、导电层和半导体材料层，并使用光刻图案化各个材料层以在材料层上形成电路组件和元件来制造半导体器件。通常，在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路将单个管芯切割。然后，将单个的管芯单独封装在多芯片模块中，或封装在其他类型的封装件中。
由于许多电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体工业经历了快速发展。大体上，该集成度的改进源自最小部件尺寸的不断减小(例如，缩小半导体工艺节点至小于20nm节点)，其允许将更多的组件集成到给定的区域中。由于最近对微型化、更高速度和更大带宽以及更低功耗和延迟的需求不断增长，因此亟需用于半导体管芯的更小和更具创造性的封装技术。
随着半导体技术进一步发展，诸如三维集成电路(3DIC)的堆叠式半导体器件出现，并成为进一步减小半导体器件的物理尺寸的有效替代物。在堆叠式半导体器件中，在不同半导体晶圆上制造诸如逻辑、存储器、处理器电路等的有源电路。可将两个或多个半导体晶圆安装或堆叠在另一个半导体晶圆的顶部以进一步减小半导体器件的形状因子。堆叠式封装(POP)器件是一种类型的3DIC，其中，将管芯封装，然后与另一个封装的管芯或一些管芯封装在一起。
发明内容
本发明的实施例提供了一种方法，包括：在衬底上形成器件；在所述衬底和所述器件上方形成多个接触焊盘；以及与形成所述多个接触焊盘同时，在所述衬底和所述器件上方形成一个或多个对准标记。
本发明的另一实施例提供了一种方法，包括：在衬底上形成器件；在所述衬底和所述器件上方形成一个或多个金属化层；在所述一个或多个金属化层上形成导电层；以及将所述导电层图案化以形成多个接触焊盘和一个或多个对准标记，所述一个或多个对准标记与所述器件电隔离。
本发明的又一实施例提供了一种半导体器件，包括：衬底；器件，位于所述衬底上；介电层，位于所述衬底和所述器件上方；接触焊盘，位于所述介电层上；以及第一对准标记，位于所述介电层上，所述第一对准标记与所述器件电隔离，所述接触焊盘和所述第一对准标记由相同材料形成，所述接触焊盘和所述第一对准标记处于相同的层级。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A至图4B是根据一些实施例的在具有对准标记的集成电路管芯的制造期间的各个工艺步骤的顶视图和截面图。
图5是根据一些实施例的集成电路管芯的顶视图。
图6是根据一些实施例的集成电路管芯的顶视图。
图7是根据一些实施例的集成电路管芯的顶视图。
图8是示出根据一些实施例的形成具有对准标记的集成电路管芯的方法的流程图。
图9至图13是根据一些实施例的在集成电路封装件的制造期间的各个工艺步骤的截面图。
图14是示出根据一些实施例的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现本发明的不同特征。下面将描述元件和布置的特定实例以简化本发明。当然这些仅仅是实例并不旨在限定本发明。例如，在下面的描述中第一部件在第二部件上方或者在第二部件上的形成可以包括第一部件和第二部件以直接接触方式形成的实施例，也可以包括额外的部件可以形成在第一和第二部件之间，使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可以在各实施例中重复参考标号和/或字符。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
在具体地讨论示出的实施例之前，一般地讨论一些实施例的某些有利特征和方面。下面描述具有对准标记的各个集成电路管芯以及形成这种集成电路管芯的方法。此外，下面描述使用集成电路管芯形成集成电路封装件的方法。通过形成具有一个或多个对准标记的集成电路管芯，在形成集成电路封装件时可减少或避免集成电路管芯的不期望的偏移或旋转。而且，可减少或避免由于未对准所致的集成电路管芯的损坏。
图1A至图4B是根据一些实施例的制造具有对准标记的集成电路管芯期间的各个工艺步骤的顶视图和截面图，其中，“A”图代表顶视图且“B”图代表沿着相应的“A”图的B-B’线截取的截面图。
参考图1A以及1B，示出了通过划线103(还称为划切线或划切区)隔开的具有管芯区101的工件100的部分。如下文更详细地描述的，将沿着划线103划切工件100以形成单个的集成电路管芯(诸如图5中示出的集成电路管芯500)。在一些实施例中，工件100包括衬底105，位于衬底105上的一个或多个有源和/或无源器件111以及位于衬底105上方的一个或多个金属化层113。在一些实施例中，衬底105可由硅形成，尽管它还可由诸如硅、锗、镓、砷的其他第III族、第IV族和/或第V族元素及其组合形成。衬底105还可为绝缘体上硅(SOI)的形式。SOI衬底可包括在绝缘体层(例如，隐埋氧化物等)上方形成的半导体材料层(例如，硅、锗等)，所述半导体材料层在硅衬底上形成。此外，可使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、其任意组合等。在其他实施例中，衬底105可包括诸如氧化硅、氧化铝等的介电材料或其组合。
在一些实施例中，一个或多个有源和/或无源器件111(由图1B中的单个晶体管表示)可包括诸如晶体管、电容器、电阻器、二极管、光电二级管、熔断器等的各种n-型金属氧化物半导体(NMOS)和/或p-型金属氧化物半导体(PMOS)器件。在一些实施例中，集成电路管芯可为离散的半导体器件芯片(有时称为表面安装器件(SMD)或集成无源器件(IPD))。在这种实施例中，衬底105可包括诸如RLC电路、电容器、电感器、变压器、平衡-不平衡转换器、微波线、共面波导管等的各种器件，并且可基本上没有有源器件。
一个或多个金属化层113可包括在衬底105上方形成的层间介电层(ILD)/金属间介电层(IMD)。例如，可通过诸如旋转涂布方法、化学气相沉积(CVD)、等离子体增强CVD(PECVD)等或其组合的本领域已知的任何合适的方法，由诸如磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物,碳化硅材料、其混合物、其复合物、其组合等的低-k介电材料形成ILD/IMD。在一些实施例中，例如，可使用镶嵌工艺、双镶嵌工艺等在ILD/IMD中形成互连结构。在一些实施例中，互连结构可包括铜、铜合金、银、金、钨、钽、铝等。在一些实施例中，互连结构可在衬底105上形成的一个或多个有源和/或无源器件111之间提供电连接。
进一步参考图1A以及图1B，在一些实施例中，管芯区101的顶视图，因此在划切工件100之后形成的集成电路管芯的顶视图可在旋转90°、180°和/或270°时几何对称。然而，管芯区101，因此在划切工件100之后形成的集成电路管芯在旋转90°、180°和/或270°时可能不功能对称。这种集成电路管芯的不对称性可由集成电路管芯中的各个有源和/或无源器件的不对称排列所致。因此，可在每个集成电路管芯上形成一个或多个对准标记以识别期望的集成电路管芯的方向。
在一些实施例中，在一个或多个金属化层113上方形成接触焊盘107和对准标记109。可通过一个或多个金属化层113将接触焊盘107电连接至一个或多个有源和/或无源器件111，同时可将对准标记109与一个或多个有源和/或无源器件111电隔离。在一些实施例中，接触焊盘107和对准标记109可包括诸如铝、铜、钨、银、金等的导电材料或其组合。在一些实施例中，例如，可使用物理气相沉积(PVD)、原子层沉积(ALD)、电化学镀、化学镀等或其组合在衬底105和一个或多个有源和/或无源器件111上方形成导电材料。随后，将导电材料图案化以形成接触焊盘107和对准标记109。因此，接触焊盘107和对准标记109可具有相同厚度。在一些实施例中，可使用光刻技术将导电材料图案化。通常，光刻技术包括沉积光刻胶材料(未示出)，随后辐照(曝光)和显影光刻胶材料以去除光刻胶材料的部分。剩余的光刻胶材料保护诸如接触焊盘107和对准标记109的导电材料的下层材料免受诸如蚀刻的随后的工艺步骤的影响。可将诸如反应离子蚀刻(RIE)或其他干蚀刻、各向同性或各向异性湿蚀刻的适当的蚀刻工艺或任何其他适当的蚀刻或图案化工艺应用于导电材料以去除导电材料的暴露的部分并且形成接触焊盘107和对准标记109。在导电材料为铝的一些实施例中，可使用80％磷酸、5％硝酸、5％乙酸和10％去离子水(DI)的混合物蚀刻导电材料。随后，例如，可使用灰化工艺和随后的湿清洗工艺去除光刻胶材料。如下面更详细地描述的，在接触焊盘107上将形成连接件。
在示出的实施例中，接触焊盘107的顶视图形状为矩形，且对准标记109的顶视图形状为L-形多边形。然而，在其他实施例中，接触焊盘107的顶视图形状可为圆形，椭圆形或诸如三角形、正方形的多边形等，且对准标记109的顶视图形状可为圆形，椭圆形或诸如三角形、正方形、矩形的多边形等。在一些实施例中，接触焊盘107和对准标记109的顶视图形状可能相似。在其他实施例中，接触焊盘107和对准标记109的顶视图形状可能不同。
参考图2A以及图2B，在衬底105、接触焊盘107和对准标记109上方形成钝化层201。在一些实施例中，钝化层201可包括诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等的可光图案化介电材料的一个或多个层，并且可使用旋转涂布工艺等形成。可使用与光刻胶材料类似的光刻方法将这种可光图案化介电材料图案化。在其他实施例中，钝化层201可包括诸如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)等的非可光图案化介电材料的一个或多个层，并且可使用化学气相沉积(CVD)、PVD、ALD、旋转涂布工艺等或其组合形成钝化层201。
随后，在钝化层201中形成开口203以暴露接触焊盘107。在一些实施例中，其中，钝化层201由可光图案化介电材料形成，可使用与光刻胶材料类似的光刻方法将钝化层201图案化。在其他实施例中，其中，钝化层201由非可光图案化介电材料形成，在钝化层201上方形成光刻胶材料(未示出)。随后，辐照(曝光)和显影光刻胶材料以去除光刻胶材料的部分。随后，例如，使用适当的蚀刻工艺去除钝化层201的暴露部分以形成开口。在一些实施例中，其中，钝化层201由氧化硅形成，例如，使用缓冲的氢氟酸(HF)将钝化层201蚀刻。在其他实施例中，其中，钝化层201由氮化硅形成，例如，使用热磷酸(H3PO4)将钝化层201蚀刻。随后，例如，可使用灰化工艺和随后的湿清洗工艺将光刻胶材料去除。
参考图3A以及图3B，在一些实施例中，在钝化层201上以及在开口203的底部和侧壁中形成晶种层301。晶种层301可包括铜、钛、镍、金等或其组合，并且可使用电化学镀工艺、ALD、PVD、溅射等或其组合形成晶种层301。在一些实施例中，在晶种层301上方形成牺牲层303。在牺牲层303中形成开口305以暴露设置在开口203中的晶种层301的部分。在一些实施例中，其中，牺牲层303包括光刻胶材料，可使用适当的光刻方法将牺牲层303图案化。如下文更详细描述的，将在开口203和305中形成连接件。
参考图4A以及图4B，在开口203和305中形成连接件401。在一些实施例中，使用电化学镀工艺、化学镀工艺、ALD、PVD等或其组合以诸如铜、铝、镍、金、银、钯等或其组合的导电材料填充开口203和305以形成导电柱401A。在一些实施例中，连接件401还可包括覆盖层401B，覆盖层401B可形成在导电柱401A的顶部。覆盖层401B可包括焊料、镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或其组合并且可通过镀工艺等形成。在完成连接件401的形成之后，将牺牲层303去除。在一些实施例中，其中，牺牲层303包括光刻胶材料，例如，可使用灰化工艺和随后的湿清洗工艺将牺牲层303去除。随后，例如，使用适当的蚀刻工艺将晶种层301的暴露部分去除。晶种层301的剩余的部分还可称为凸块下金属化(UBM)301。在其他实施例中，连接件401可为焊球、可控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍钯-浸金技术(ENEPIG)形成的凸块等。在一些实施例中，其中，连接件401为焊料凸块，可通过诸如蒸发、电镀、印刷、焊料转移、植球等的常用方法首先形成焊料层来形成连接件401。一旦形成焊料层，可实施回流以将材料成型为期望的凸块形状。
在示出的实施例中，连接件401的顶视图形状为圆形。然而，在其他实施例中，连接件401的顶视图形状可为椭圆形或诸如三角形、正方形的多边形等。此外，在示出的实施例中，管芯区101包括二十个接触焊盘(诸如接触焊盘107)、二十个连接件(诸如连接件401)、一个对准标记(诸如对准标记109)和一个钝化层(诸如钝化层201)。本领域技术人员将认识到，钝化层、接触焊盘、对准标记和连接件的数量仅提供用于说明的目的而并非限制本发明的范围。在其他实施例中，取决于随后形成的集成电路管芯的设计要求，管芯区101可包括适当数量的钝化层、接触焊盘、对准标记和连接件。
进一步参考图4A以及图4B，沿着划线103将工件100划切以形成单个的集成电路管芯。在一些实施例中，例如，可使用蚀刻、锯切、激光烧蚀等或其组合将工件100划切。随后，为了进一步加工，可测试各个集成电路管芯以识别已知良好管芯(KGD)。如下面更详细地描述的，集成电路管芯将用于形成集成电路封装件。
图5是根据一些实施例的在划切工件100之后形成的集成电路管芯500的顶视图。在示出的实施例中，对准标记109的顶视图形状为L-形多边形。仅为了例示的目的，提供了图5中示出的对准标记109的特定方向。在其他实施例中，当从顶部观察时，可将对准标记109旋转期望的角度。在一些实施例中，集成电路管芯500的第一侧面可具有约0.5mm和约3.0mm之间的第一宽度W1，且集成电路管芯500的第二侧面可具有约0.5um和约3.0um之间的第二宽度W2。在一些实施例中，连接件401可具有约35um和约55um之间的宽度W3。在一些实施例中，对准标记109的第一最长侧面(平行于集成电路管芯500的第一侧面)可具有约W1/20和约W1/10之间的长度L1，对准标记109的第二最长侧面(平行于集成电路管芯500的第二侧面)可具有约W2/20和约W2/10之间的长度L2，对准标记109的第一最短侧面(平行于集成电路管芯500的第一侧面)可具有约L1/2和约L1/3之间的长度L3，对准标记109的第二最短侧面(平行于集成电路管芯500的第二侧面)可具有约L2/2和约L2/3之间的长度L4。在一些实施例中，对准标记109和最近的连接件401之间的距离L5可大于或等于W3/2。
图6是根据一些实施例的集成电路管芯600的顶视图。在一些实施例中，可使用与上述参考图1A至图4B描述的材料和方法类似的材料和方法形成集成电路管芯600，其中，使用类似的引用数字标记类似的元件，并且此处不重复描述。在一些实施例中，可在集成电路管芯600的拐角处形成对准标记601，并且从顶部观察，对准标记601可具有三角形状。在一些实施例中，可使用与上述参考图1A至图1B描述的对准标记109的材料和方法类似的材料和方法形成对准标记601，并且此处不重复描述。仅为了例示的目的，提供图6中示出的对准标记601的特定方向。在其他实施例中，当从顶部观察时，可将对准标记601旋转期望的角度。在一些实施例中，集成电路管芯600的第一侧面可具有约0.5mm和约3mm之间的第一宽度W1，且集成电路管芯600的第二侧面可具有约0.5mm和约3mm之间的第二宽度W2。在一些实施例中，连接件401可具有约35um和约55um之间的宽度W3。在一些实施例中，对准标记601的第一侧面(平行于集成电路管芯600的第一侧面)可具有约W1/20和约W1/10之间的长度L6，且对准标记601的第二侧面(平行于集成电路管芯600的第二侧面)可具有约W2/20和约W2/10之间的长度L7。在一些实施例中，对准标记601和最近的连接件401之间的距离L8可大于或等于W3/2。
图7是根据一些实施例的集成电路管芯700的顶视图。在一些实施例中，可使用与上述参考图1A至图4B描述的材料和方法类似的材料和方法形成集成电路管芯700，其中，使用类似的引用数字标记类似的元件，并且此处不重复描述。在一些实施例中，可在集成电路管芯700的相对的拐角处形成第一对准标记701和第二对准标记703。在一些实施例中，可使用与上述参考图1A至图1B描述的对准标记109的材料和方法类似的材料和方法形成第一对准标记701和第二对准标记703，并且此处不重复描述。在一些实施例中，第一对准标记701和第二对准标记703的顶视图形状为L-形多边形。仅为了例示的目的，提供图7中示出的第一对准标记701和第二对准标记703的特定方向。在其他实施例中，当从顶部观察时，可将第一对准标记701和第二对准标记703旋转期望的角度。在一些实施例中，集成电路管芯700的第一侧面可具有约0.5mm和约3mm之间的第一宽度W1，且集成电路管芯700的第二侧面可具有约0.5mm和约3mm之间的第二宽度W2。在一些实施例中，连接件401可具有约35um和约55um之间的宽度W3。在一些实施例中，第一对准标记701的第一最长侧面(平行于集成电路管芯700的第一侧面)可具有约W1/20和约W1/10之间的长度L9，第一对准标记701的第二最长侧面(平行于集成电路管芯700的第二侧面)可具有约W2/20和约W2/10之间的长度L10。第一对准标记701的第一最短侧面(平行于集成电路管芯700的第一侧面)可具有约L9/2和约L9/3之间的长度L11，且第一对准标记701的第二最短侧面(平行于集成电路管芯700的第二侧面)可具有约L10/2和约L10/3之间的长度L12。在一些实施例中，第二对准标记703的第一最长侧面(平行于集成电路管芯700的第一侧面)可具有约W1/20和约W1/10之间的长度L14，第二对准标记703的第二最长侧面(平行于集成电路管芯700的第二侧面)可具有约W2/20和约W2/20之间的长度L15，第二对准标记703的第一最短侧面(平行于集成电路管芯700的第一侧面)可具有约L14/2和约L14/3之间的长度L16，且第二对准标记703的第二最短侧面(平行于集成电路管芯700的第二侧面)可具有约L15/2和约L15/3之间的长度L17。在一些实施例中，第一对准标记701和最近的连接件401之间的距离L13可大于或等于W3，且第二对准标记703和最近的连接件401之间的距离L18可大于或等于W3/2。
图8是根据一些实施例的示出形成具有对准标记的集成电路管芯(诸如集成电路管芯500、600和/或700)的方法800的流程图。方法从步骤801开始，其中，如上述参考图1A以及图1B描述的，在工件(诸如工件100)上方形成接触焊盘(诸如接触焊盘107)和对准标记(诸如对准标记109)。在步骤803中，如上述参考图2A至图4B描述的，在接触焊盘上方形成连接件(诸如连接件401)。在步骤805中，如上述参考图4A以及图4B描述的，将工件划切成单个的集成电路管芯。
图9至图13是根据一些实施例的在集成电路封装件的制造期间的各个示例性工艺步骤的截面图。如下面更详细地描述的，集成电路管芯(例如，分别在图5至图7中示出的集成电路管芯500、600和700)将用于形成集成电路封装件(诸如图12中示出的集成电路封装件1215)。本领域技术人员将理解，仅为了例示的目的提供下面描述的工艺步骤，并且可使用任何适当的封装方法封装集成电路管芯。
首先参考图9，在一些实施例中，在载体901上方形成脱模层903，并在脱模层903上方形成一个或多个介电层905以开始形成集成电路封装件。在一些实施例中，载体901可由石英、玻璃等形成，并且提供随后的操作的机械支持。在一些实施例中，脱模层903可包括光热转换(LTHC)材料、UV粘合剂等，并且可使用旋转涂布工艺、印刷工艺、层压工艺等形成。在一些实施例中，其中，脱模层903由LTHC材料形成，当暴露于光时，脱模层903部分地或完全地丧失它的粘合强度，并且可从随后形成的结构的背面容易地去除载体901。在一些实施例中，可使用与上述参考图2A以及图2B描述的钝化层201的材料和方法类似的材料和方法形成一个或多个介电层905，并且此处不重复描述。
进一步参考图9，在一个或多个介电层905上形成导电通孔907。在一些实施例中，可在导电通孔907和一个或多个介电层905之间插入晶种层(未示出)。在一些实施例中，可使用与分别参考图3A至图4B描述的晶种层301和导电柱401A类似的材料和方法形成晶种层和导电通孔907，此处不重复描述。
参考图10，使用粘合层1001将集成电路管芯1003连接至一个或多个介电层905。在一些实施例中，例如，使用拾取和放置装置将集成电路管芯1003放置在一个或多个介电层905上。在其他实施例中，可手动地或使用任何其他适当方法将集成电路管芯1003放置在一个或多个介电层905上。在一些实施例中，粘合层1001可包括LTHC材料、UV粘合剂、管芯附接膜等，并且粘合层1001可使用旋转涂布工艺、印刷工艺、层压工艺等形成。
在一些实施例中，将集成电路管芯1003安装至一个或多个介电层905使得管芯接触件1005和对准标记1007面对远离一个或多个介电层905或者处于一个或多个介电层905的远端。管芯接触件1005提供与在集成电路管芯1003上形成的电路的电连接。管芯接触件1005可在集成电路管芯1003的有源侧面上形成，或者可在背面上形成并且包括通孔。管芯接触件1005还可包括在集成电路管芯1003的第一侧面和第二侧面之间提供电连接的通孔。在一些实施例中，管芯接触件1005可包括铜、钨、铝、银、金、锡、其组合等。在一些实施例中，可使用与上述参考图1A至图4B描述的接触焊盘107和对准标记109类似的材料和方法形成管芯接触件1005和对准标记1007，此处不重复描述。如上所述，一个或多个对准标记的使用具有许多优点。例如，当将集成电路管芯1003安装在一个或多个介电层905上时，可减少或避免集成电路管芯1003的不期望的偏移或旋转。而且，可减少或避免由未对准所致的集成电路管芯1003的损坏。
参考图11，在载体901上方以及在集成电路管芯1003和导电通孔907的上方和周围形成密封剂1101。在一些实施例中，密封剂1101可包括诸如环氧树脂、树脂、可模制聚合物等的模塑料。可在模塑料基本上是液体时将其涂覆，然后通过诸如环氧树脂或树脂中的化学反应将模塑料固化。在其他实施例中，模塑料可为紫外(UV)或热固化聚合物，所述聚合物以能够设置在集成电路管芯1003和导电通孔907周围以及之间的凝胶或可塑固体的形式涂覆。
进一步参考图11，在一些实施例中，使用CMP工艺、磨削工艺等或其组合将产生的结构平坦化。在一些实施例中，实施平坦化工艺直至暴露集成电路管芯1003的管芯接触件1005。在一些实施例中，导电接触件1005的顶面与导电通孔907和密封剂1101的顶面基本共面。
参考图12，在集成电路管芯1003、导电通孔907和密封剂1101上方形成一个或多个再分布层(RDL)1201。在一些实施例中，RDL 1201包括一个或多个介电层1203和设置在一个或多个介电层1203内的一个或多个导电部件1205。在一些实施例中，可使用与上述参考图10描述的介电层905类似的材料和方法形成一个或多个介电层1203，此处不重复描述。在一些实施例中，一个或多个导电部件1205可包括铜、钨、铝、银、金等或其组合，并且可使用电化学镀工艺、化学镀工艺、ALD、PVD等或其组合形成。
进一步参考图12，在RDL1201上方形成电连接至RDL1201的凸块下金属化(UBM)1207。在一些实施例中，可形成穿过一个或多个介电层1203的最顶介电层(未单独示出)的一组开口以暴露RDL1201的一个或多个导电部件1205。在一些实施例中，UBM1207可包括诸如钛层、铜层和镍层的多层导电材料。然而，本领域技术人员将认识到，有适于形成UBM1207的材料和层的许多适当排列，诸如铬/铬-铜合金/铜/金的排列、钛/钛钨/铜的排列或铜/镍/金的排列。可用于UBM1207的任何适当的材料或材料层完全旨在包括在本申请的范围内。在一些实施例中，在一些UBM1207上方形成电连接至该一些UBM1207的连接件1209。在一些实施例中，可使用与上述参考图4A以及图4B描述的连接件401类似的材料和方法形成连接件1209，此处不重复描述。
进一步参考图12，在RDL1201上方安装集成电路管芯1211，并且集成电路管芯1211电连接至RDL1201。在一些实施例中，集成电路管芯1211的连接件1213用于将集成电路管芯1211连接至UBM 1207，同时集成电路管芯1211的对准标记1217用于在RDL 1201上方适当地对准集成电路管芯1211。在一些实施例中，集成电路管芯1211可能与集成电路管芯500、600和/或700(参见图5至图7)类似，并且可使用与上述参考图1A至图4B描述的那些方法类似的方法形成，此处不重复描述。在一些实施例中，可使用分别与参考图1A至图4B描述的连接件401和对准标记109类似的材料和方法形成连接件1213和对准标记1217，此处不重复描述。在一些实施例中，例如，使用拾取和放置装置将集成电路管芯1211放置在RDL1201上。在一些实施例中，拾取和放置装置可使用集成电路管芯1211的对准标记1217以在RDL 1201上方适当地对准集成电路管芯1211。通过使用对准标记1217，可减少或避免集成电路管芯1211的不期望的偏移或旋转。而且，可减少或避免由未对准所致的集成电路管芯1211的损坏。在其他实施例中，可手动地或使用任何其他适当方法将集成电路管芯1211放置在RDL1201上。在示出的实施例中，集成电路管芯1211为离散的半导体器件芯片。然而，在其他实施例中，集成电路管芯1211可为提供期望的功能性的任何适当的集成电路管芯。
在一些实施例中，在RDL1201上方安装集成电路管芯1211之后，将产生的结构从载体901分离并划切以形成单个的集成电路封装件1215。在一些实施例中，可通过锯切、激光烧蚀方法等将产生的结构划切。随后，为了进一步加工，可测试各个集成电路封装件1215以识别已知良好封装件(KGP)。
图13示出通过延伸穿过一个或多个介电层905中的开口的工件1303与集成电路封装件1215的接合工艺以形成堆叠式半导体器件1300。在一些实施例中，工件1303可为封装件、一个或多个管芯、印刷电路板(PCB)、封装件衬底、插件等。在一些实施例中，其中，工件1303为封装件，堆叠式半导体器件1300为堆叠封装(PoP)器件。在其他实施例中，其中，工件1303为管芯，堆叠式半导体器件1300为封装件上芯片(CoP)器件。在一些实施例中，可使用与上述参考图3A至图4B描述的连接件401的材料和方法类似的材料和方法形成连接件1305，此处不重复描述。在一些实施例中，在参考图12描述的划切工艺之前，可将工件1303接合至集成电路封装件1215。
进一步参考图13，可注入底部填充材料(未示出)或者可以其他方式在工件1303和集成电路封装件1215之间的空间以及连接件1305周围形成底部填充材料。例如，底部填充材料可为在各个结构之间分配的液体环氧树脂、可变形凝胶、硅橡胶等，然后将底部填充材料固化至变硬。此外，该底部填充材料可用于减少对连接件1305的损坏以及保护连接件1305。
进一步参考图13，在一些实施例中，可使用连接件1209将堆叠式半导体器件1300接合至工件1301。在一些实施例中，工件1301可能与工件1303类似并且此处不重复描述。在示出的实施例中，工件1301是印刷电路板(PCB)。
图14是示出根据一些实施例的形成集成电路封装件的方法1400的流程图。方法1400从步骤1401开始，其中，如上述参考图9描述的，在载体(诸如载体901)上方形成一个或多个介电层(诸如一个或多个介电层905)。随后，如上述参考图9描述的，在一个或多个介电层上方形成导电通孔(诸如导电通孔907)。在步骤1403中，如上述参考图10描述的，将第一管芯(诸如集成电路管芯1003)连接至一个或多个介电层。在步骤1405中，如上述参考图11描述的，形成密封剂(诸如密封剂1101)以封装导电通孔和第一管芯。在步骤1407中，如上述参考图12描述的，在封装的第一管芯和导电通孔上方形成一个或多个再分布层(诸如RDL1201)。在步骤1409中，如上述参考图12描述的，在一个或多个RDL上方形成连接件(诸如连接件1209)。在步骤1411中，如上述参考图12描述的，将第二管芯(诸如集成电路管芯1211)安装在一个或多个RDL上。在步骤1413中，如上述参考图12描述的，将产生的结构从载体分离并划切以形成单个的集成电路封装件(诸如集成电路封装件1215)。
根据一个实施例，方法包括在衬底上形成器件。在衬底和器件上方形成多个接触焊盘。与形成多个接触焊盘同时，在衬底和器件上方形成一个或多个对准标记。
在上述方法中，还包括：将所述衬底划切以形成管芯，所述管芯具有至少一个对准标记；使用所述至少一个对准标记将所述管芯与工件对准；以及将所述管芯连接至所述工件。
在上述方法中，还包括：将所述衬底划切以形成管芯，所述管芯具有至少一个对准标记；使用所述至少一个对准标记将所述管芯与工件对准；以及将所述管芯连接至所述工件，其中，所述管芯是离散的半导体器件芯片。
在上述方法中，还包括：将所述衬底划切以形成管芯，所述管芯具有至少一个对准标记；使用所述至少一个对准标记将所述管芯与工件对准；以及将所述管芯连接至所述工件，其中，所述工件包括多个封装的管芯和位于所述多个封装的管芯上的一个或多个再分布线(RDL)，所述管芯连接至所述一个或多个RDL，所述一个或多个RDL插入在所述多个封装的管芯和所述管芯之间。
在上述方法中，其中，形成所述多个接触焊盘和所述一个或多个对准标记包括：在所述衬底和所述器件上方沉积导电层；以及将所述导电层图案化以形成所述多个接触焊盘和所述一个或多个对准标记。
在上述方法中，还包括在所述多个接触焊盘上形成连接件。
在上述方法中，其中，所述一个或多个对准标记与所述器件电隔离。
根据另一个实施例，方法包括在衬底上形成器件。在衬底和器件上方形成一个或多个金属化层。在一个或多个金属化层上形成导电层。将导电层图案化以形成多个接触焊盘和一个或多个对准标记，一个或多个对准标记与器件电隔离。
在上述方法中，还包括在所述多个接触焊盘和所述一个或多个对准标记上方形成钝化层，所述钝化层覆盖所述一个或多个对准标记的整个顶面。
在上述方法中，还包括：将所述衬底切割以形成切割的管芯，所述切割的管芯具有至少一个对准标记；使用所述至少一个对准标记将所述切割的管芯与工件对准；以及将所述切割的管芯连接至所述工件。
在上述方法中，还包括：将所述衬底切割以形成切割的管芯，所述切割的管芯具有至少一个对准标记；使用所述至少一个对准标记将所述切割的管芯与工件对准；以及将所述切割的管芯连接至所述工件，其中，所述工件包括多个封装的管芯和位于所述多个封装的管芯上的一个或多个再分布线(RDL)，所述切割的管芯连接至所述一个或多个RDL，所述一个或多个RDL插入在所述切割的管芯和所述多个封装的管芯之间。
在上述方法中，还包括：将所述衬底切割以形成切割的管芯，所述切割的管芯具有至少一个对准标记；使用所述至少一个对准标记将所述切割的管芯与工件对准；以及将所述切割的管芯连接至所述工件，其中，所述切割的管芯为离散的半导体器件芯片。
在上述方法中，还包括在所述多个接触焊盘上形成连接件。
在上述方法中，其中，当从顶部观察时，所述一个或多个对准标记的每个都具有多边形形状。
仍根据另一个实施例，半导体器件包括衬底、位于衬底上的器件和位于衬底和器件上方的介电层。半导体器件还包括位于介电层上的接触焊盘和位于介电层上的第一对准标记，第一对准标记与器件电隔离，接触焊盘和第一对准标记由相同材料形成，接触焊盘和第一对准标记处于相同的层级。
在上述半导体器件中，还包括：钝化层，位于所述介电层上，所述接触焊盘和所述第一对准标记插入在所述介电层和所述钝化层之间。
在上述半导体器件中，其中，所述接触焊盘和所述第一对准标记具有相同厚度。
在上述半导体器件中，其中，所述第一对准标记位于所述衬底的第一拐角处。
在上述半导体器件中，其中，所述第一对准标记位于所述衬底的第一拐角处，所述半导体器件还包括：第二对准标记，位于所述介电层上，所述第二对准标记位于所述衬底的第二拐角处，所述第二拐角与所述第一拐角相对。
在上述半导体器件中，其中，当从顶部观察时，所述第一对准标记具有多边形形状。
上面论述了若干实施例的部件，使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域技术人员也应该意识到，这些等效结构并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种方法，包括：
在衬底上形成器件；
在所述衬底和所述器件上方形成多个接触焊盘；以及
与形成所述多个接触焊盘同时，在所述衬底和所述器件上方形成一个或多个对准标记。
2.根据权利要求1所述的方法，还包括：
将所述衬底划切以形成管芯，所述管芯具有至少一个对准标记；
使用所述至少一个对准标记将所述管芯与工件对准；以及
将所述管芯连接至所述工件。
3.根据权利要求2所述的方法，其中，所述管芯是离散的半导体器件芯片。
4.根据权利要求2所述的方法，其中，所述工件包括多个封装的管芯和位于所述多个封装的管芯上的一个或多个再分布线(RDL)，所述管芯连接至所述一个或多个RDL，所述一个或多个RDL插入在所述多个封装的管芯和所述管芯之间。
5.根据权利要求1所述的方法，其中，形成所述多个接触焊盘和所述一个或多个对准标记包括：
在所述衬底和所述器件上方沉积导电层；以及
将所述导电层图案化以形成所述多个接触焊盘和所述一个或多个对准标记。
6.根据权利要求1所述的方法，还包括在所述多个接触焊盘上形成连接件。
7.根据权利要求1所述的方法，其中，所述一个或多个对准标记与所述器件电隔离。
8.一种方法，包括：
在衬底上形成器件；
在所述衬底和所述器件上方形成一个或多个金属化层；
在所述一个或多个金属化层上形成导电层；以及
将所述导电层图案化以形成多个接触焊盘和一个或多个对准标记，所述一个或多个对准标记与所述器件电隔离。
9.根据权利要求8所述的方法，还包括在所述多个接触焊盘和所述一个或多个对准标记上方形成钝化层，所述钝化层覆盖所述一个或多个对准标记的整个顶面。
10.一种半导体器件，包括：
衬底；
器件，位于所述衬底上；
介电层，位于所述衬底和所述器件上方；
接触焊盘，位于所述介电层上；以及
第一对准标记，位于所述介电层上，所述第一对准标记与所述器件电隔离，所述接触焊盘和所述第一对准标记由相同材料形成，所述接触焊盘和所述第一对准标记处于相同的层级。
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