TWI606570B - 積體電路結構及形成方法 - Google Patents

積體電路結構及形成方法 Download PDF

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Publication number
TWI606570B
TWI606570B TW104139604A TW104139604A TWI606570B TW I606570 B TWI606570 B TW I606570B TW 104139604 A TW104139604 A TW 104139604A TW 104139604 A TW104139604 A TW 104139604A TW I606570 B TWI606570 B TW I606570B
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Taiwan
Prior art keywords
die
redistribution layer
layer
film
integrated circuit
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TW104139604A
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English (en)
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TW201705438A (zh
Inventor
Chen Hua Yu
Jui Pin Hung
Kuo Chung Yee
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201705438A publication Critical patent/TW201705438A/zh
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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Description

積體電路結構及形成方法
本申請案主張美國臨時申請案62/140,356的優先權，其申請日為2015年3月30日，在此將其全文納入參照。
本揭露一般係關於積體電路結構及形成方法。
半導體裝置可運用於多種電子應用中，譬如個人電腦、行動電話、數位相機以及其他電子設備。半導體裝置的製造通常是利用在一半導體基板上依序沈積絕緣或介電層、導電層以及半導體層之材料，並利用微影製程將各種材料層圖案化，以在其上形成電路元件及部件。通常在單一個半導體晶圓上會形成數十甚至數百個積體電路。藉由沿著切割道鋸切積體電路，而將個別晶粒單粒化。之後將個別晶粒單獨封裝於多晶片模組或其他類型的封裝中。
由於對多種電子元件(如，電晶體、二極體、電阻器、電容器等)之集積密度持續的改進，半導體產業經歷了快速的成長。通常來說，上述對集積密度的改進來自於對最小構件尺寸的不斷縮減(如，將半導體製程節點(process node)縮減至次-20奈米節點)，這使得能在一指定面積中整合更多的元件。由於近來對於微型化、高速及高頻寬還有對於低耗電與低延時(latency)的需求持續成長，本領域需要一種更小且更有創意的半導體晶粒包裝技術。
隨著半導體技術持續的進展，堆疊式半導體裝置，如三維積體電路(three dimensional integrated circuits，3DICs)已漸漸成為一種進一步縮減半導體裝置實體尺寸的有效替代方案。在堆疊式半導體裝置中，在不同的半導體晶圓上製造主動電路，譬如邏輯、記憶體、處理器電路及其他類似者。可將二或更多個半導體晶圓裝置或堆疊在彼此上方，以進一步縮減半導體裝置的形狀因素(form factor)。層疊封裝(Package-on-package，POP)裝置是3DIC的一種，其中晶粒經過封裝之後再和另一或多個晶粒一起封裝。
本發明的實施例提供一種形成半導體裝置的方法。上述方法包括將晶粒放置於載板上方以及在鄰近該晶粒處形成膜塑料。形成重佈層，其係電性耦接至該晶粒並位於該膜塑料上方。移除該載板。連接第一基板至該重佈層之與該晶粒相反的一側上，且該重佈層連接至印刷電路板。
本發明的實施例提供一種形成半導體裝置的方法。上述方法包括將複數個晶粒放置於載板上方。沿著該些晶粒之側壁形成膜塑料，其中該膜塑料不具有延伸通過該膜塑料的貫穿通路。形成重佈層，其係電性耦接至該晶粒且位於該膜塑料上方。移除該載板。將一或多個裝置、被動元件及/或封裝放置於該重佈層上方。
本發明的實施例提供一種半導體裝置。上述半導體裝置包括晶粒、及沿著該晶粒之側壁延伸的膜塑料。重佈層設於該膜塑料及該晶粒上方。基板安裝於該重佈層之與該膜塑料相反的一側上。印刷電路板連接至該重佈層。
100‧‧‧載板
102‧‧‧緩衝層
200‧‧‧積體電路晶粒
202‧‧‧接點
204‧‧‧晶粒附接膜/黏著層
300‧‧‧膜塑材料
400‧‧‧重佈層/RDL
402‧‧‧導電線
404‧‧‧通路
406‧‧‧鈍化層
408‧‧‧凸塊下金屬/UBM
410‧‧‧連接件
600‧‧‧元件
602‧‧‧封裝
700‧‧‧InFO結構
800‧‧‧印刷電路板/PCB
802‧‧‧電源連接器
804‧‧‧積體電路結構
806‧‧‧外殼
808‧‧‧天線
810、812‧‧‧導線
814‧‧‧接觸墊
A、B‧‧‧距離
為讓本發明的上述與其他目的、特徵、優點與實施例能更明顯易懂，下文將參照附隨圖式進行說明，其中所附圖式之說明 如下：圖1-7是根據例示性實施方式形成一積體電路結構之中間階段的剖面圖；以及圖8A、8B、9A與9B是根據例示性實施方式之一積體電路結構的剖面與平面圖。
以下揭示內容提供了多種實施方式或例示，其能用以實現所提供之標的的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，這些敘述僅為例示，其本意並非用於限制本揭示內容。舉例來說，在下文的描述中，將第一構件形成於第二構件上或之上，可能包括某些實施例其中所述的第一與第二構件彼此直接接觸；且也可能包括某些實施例其中還有額外的元件形成於上述第一與第二構件之間，而使得第一與第二構件可能不具有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號和/或標號。此種重複使用乃是基於簡潔與清楚之目的，且其本身不代表所討論的不同實施例和/或組態之間的關係。
再者，在此處使用空間上相對的詞彙，譬如「之下」、「下方」、「低於」、「之上」、「上方」及與其相似者，可能是為了方便說明圖中所繪示的一元件或構件相對於另一或多個元件或構件之間的關係。這些空間上相對的詞彙其本意除了圖中所繪示的方位之外，還涵蓋了裝置在使用或操作中所處的多種不同方位。可能將所述設備放置於其他方位(如，旋轉90度或處於其他方位)，而這些空間上相對的描述詞彙就應該做相應的解釋。
下文參照特定脈絡中的實施例來描述多個實施例，即，安裝於外殼中的獨立三維(three dimensional，3D)整合扇出型(Integrated Fan Out，InFO)封裝及印刷電路板(printed circuit board，PCB)結構，且其可用於譬如家用電器。其他實施例可能適用於其他應用。舉例來說，某些實施例可能適用於醫療裝置、家庭自動化、地理位置服務、行動通訊及行銷應用。亦可有多種不同的實施例與應用。
根據多種例示性的實施例，提供積體電路結構及其製造方法。圖中繪示了形成所述積體電路結構的中間階段，並討論了實施例的變化。
圖1-7繪示根據某些實施方式，形成積體電路結構之中間步驟的剖面圖。首先參照圖1，圖中繪示了載板100及緩衝層102。一般來說，在後續製程步驟中，載板100提供了暫時性的機械與結構支撐。載板100可包括任何適當的材料，譬如，舉例來說，含矽材料(譬如矽晶圓、玻璃或氧化矽)、其他材料(譬如氧化鋁、陶瓷材料)、或任何上述材料的組合或與其相似者。在某些實施例中，載板100是平面的，以便用於後續製程。
可在載板100上形成可任選的釋放層(圖中未繪示)，其有助於更輕易地移除載板100。如下文所詳述的，將會在載板100上放置各種層與裝置，其後可將載板100移除。可任選的釋放層有助於移除載板100、減少對形成於載板100上之結構的損傷。釋放層可以由聚合物材料所形成。在某些實施例中，所述釋放層是含環氧樹脂的熱釋放材料，此種材料在加熱後會失去黏性，譬如光熱轉換(Light-to-Heat-Conversion，LTHC)釋放塗層。在其他實施例中，釋放層可為紫外(ultra-violet，UV)膠，此種材料當接觸到UV光時會失去黏性。可用液態的形式施佈釋放層並將其固化。在其他實施例中，釋放層可為層壓於載板100上的層壓膜。亦可運用其他釋放層。
緩衝層102形成於載板100上方。緩衝層102是介電層，其可為一聚合物(譬如苯并口咢唑(polybenzoxazole，PBO)、 聚醯亞胺、苯環丁烯(benzocyclobutene，BCB)或與其相似者)、一氮化物(如氮化矽或與其相似者)、一氧化物(如氧化矽、磷矽酸鹽玻璃(PhosphoSilicate Glass，PSG)、硼矽酸鹽玻璃(BoroSilicate Glass，BSG)、硼磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass，BPSG)或上述之組合或與其相似者)或與其相似者，且可利用譬如旋塗、層壓、化學氣相層積(Chemical Vapor Deposition，CVD)或與其相似的方式所形成。在某些實施例中，緩衝層102為平面層，在製程變化下，其具有均勻的厚度，其中所述厚度可介於約5微米至約20微米之間。緩衝層102的上方與下方表面於製程變化下亦為平面的。
圖2繪示根據某些實施例，將複數個積體電路晶粒200附接到緩衝層102的背側。在某些實施例中，可利用黏著層204，譬如晶粒附接膜(die-attach film，DAF)，將積體電路晶粒200黏著至緩衝層102。於一實施例中，晶粒附接膜204可能僅位於積體電路晶粒200的正下方，如圖2所示。在其他實施例中，晶粒附接膜204可能延伸在緩衝層102上介於相鄰的積體電路晶粒200之間。黏著層的厚度可介於約5微米至約50微米之間，譬如約20微米。可使用任何數目的積體電路晶粒200，且積體電路晶粒200可包括適用於特定用途之任何晶粒。舉例來說，積體電路晶粒200可包括靜態隨機存取記憶體(static random access memory，SRAM)晶片或動態隨機存取記憶體(dynamic random access memory，DRAM)晶片、處理器、記憶體晶片、邏輯晶片、類比晶片、數位晶片、中央處理單元(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)、基頻處理器、微控制器單元(microcontroller unit，MCU)、射頻(radio frequency，RF)晶片、感應器晶片、微機電系統(micro-electromechanical-system，MEMS)晶片、積體被動元件 (integrated passive device，IPD)或上述之組合或與其相似者。在被附接至緩衝層102之前，可根據適當的製程來處理積體電路晶粒200，以在積體電路晶粒200上形成積體電路。每一晶粒200可包括基板(譬如矽基板)，其係接合至黏著層，其中半導體基板的背面接合至所述黏著層。
在某些例示性實施例中，晶粒200包括接點202(譬如銅柱)，其與晶粒200中之裝置譬如電晶體電性耦接。在某些實施例中，在個別晶粒200的頂面形成有介電層(圖中未繪示)，且接點202的至少下部位於所述介電層中。在某些實施例中，接點202的頂表面亦可與介電層的頂面齊平。或者是，接點202可突起高於及/或下陷低於個別晶粒200的頂層。在其他實施例中，可運用其他結構作為接點202，譬如導線、金屬柱、銅栓、金栓或與其相似者。
參照圖3，將膜塑材料300成型及/或層壓於晶粒200上。膜塑材料300填充了晶粒200之間的間隙且可和緩衝層102相接。此外，當接點202的部分突起時，膜塑材料300可填充於接點202之間的間隙。膜塑材料300可包括膜塑料、成型底膠、環氧樹脂、樹脂、乾膜或與其相似者。在某些實施例中，膜塑材料300的頂面高於接點202的頂端。
可進行研磨步驟，以使膜塑材料300變薄進而使接點202露出。所得到的結構如圖3所示。因為研磨步驟，接點202的頂端可實質上和膜塑材料300的頂面齊平(共平面)。由於研磨的關係，可能會產生金屬殘餘物譬如金屬粒子，並會留存在膜塑材料300及接點202的頂面。因此，在研磨之後，必須進行清潔，舉例來說，可利用濕式蝕刻來移除金屬殘餘物。
接著，參照圖4，形成一或多個重佈層(RDL)400。一般來說，RDL提供了一種導電圖案，其使得完成之封裝的腳位接點 圖案和金屬柱的圖案不同，這使得晶粒200的放置有較高的彈性。RDL可用於提供對晶粒200的外部電性耦接。RDL包括導電線402及通路404，其中通路404將上方線連接到下方導電構件(如，接點202及/或導電線402)。導電線402可沿著任何方向延伸，譬如，可向頁面的左方或右方延伸或進入或離開頁面。
可利用任何適當的製程來形成RDL。舉例來說，在某些實施例中，在膜塑材料300及積體電路晶粒200上形成介電層。在某些實施例中，上述介電層是由聚合物所形成，所述聚合物可為光敏材料，譬如苯并口咢唑(PBO)、聚醯亞胺、苯環丁烯(BCB)或與其相似者，可透過微影製程將這些材料圖案化。在其他實施例中，所述介電層是由氮化物(譬如氮化矽)、氧化物(如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、硼磷矽酸鹽玻璃(BPSG)或與其相似者所形成。上述介電層可利用旋塗、層壓、CVD、其他相似技術上述之組合所形成。之後將介電層圖案化，以形成開口而使接點202露出。在利用光敏材料形成介電層的實施例中，可藉由以所欲圖案來曝光介電層並將其顯影而移除不要的材料，以進行上述圖案化，進而使接點202露出。亦可使用其他方法，譬如利用圖案化遮罩與蝕刻，將介電層圖案化。
在介電層上以及在形成於介電層中之開口內形成晶種層(圖中未繪示)。在某些實施例中，晶種層為一金屬層，其可為單一層或複合層，其包括由不同材料所形成的複數個子層。在某些實施例中，晶種層包括鈦層與該鈦層上的銅層。可利用譬如PVD或相似技術來形成晶種層。之後在晶種層上形成遮罩，並根據所欲的重佈圖案將其圖案化，譬如圖4所示的圖案。在某些實施例中，遮罩是利用旋塗或類似技術所形成的光阻，並將其暴露於光線下以進行圖案化。上述圖案化過程透過遮罩形成開口，以使晶種層露出。在遮罩之開口中 以及在晶種層的露出部分上，形成導電材料。可利用鍍覆法來形成所述導電材料，譬如電鍍或無電式電鍍或其他類似技術。導電材料可包括金屬，如銅、鈦、鎢、鋁或與其相似者。之後，移除光阻以及其上並未形成導電材料之晶種層的部分。可利用可接受的灰化或剝除製程來移除光阻，譬如使用含氧電漿或與其相似者。一旦移除了光阻後，將晶種層露出的部分移除，譬如可利用可接受的蝕刻製程，利用運用濕式或乾式蝕刻。晶種層與導電材料的留存部分形成了導電線402及通路404。
雖然上文敘述了形成一層RDL，可重複上述製程以得到超過一層的RDL，此一層數取決於特定應用的設計需求。舉例來說，圖4中繪示了一層RDL。亦可有更多的RDL層。
接著，根據某些實施例，可在最上層的金屬化圖案上形成鈍化層406。鈍化層可由聚合物所形成，其可為光敏材料譬如PBO、聚醯亞胺、BCB或與其相似者，可利用微影製程遮罩將這些材料圖案化。在其他實施例中，鈍化層可由氮化物或氧化物所形成，譬如氮化矽、氧化矽、PSG、BSG、BPSG或與其相似者。可利用旋塗、層壓、CVD或相似技術或其組合來形成鈍化層。之後將鈍化層圖案化，以使得下方金屬化層的部分露出。可利用可接受的製程進行圖案化，譬如當介電層是光敏材料時，可將鈍化層暴露於光線；或利用蝕刻譬如非等向性蝕刻。接著，在鈍化層上並穿透鈍化層而形成並圖案化一凸塊下金屬(under bump metallization，UBM)408，因而形成和最上方金屬化層的電性耦接。凸塊下金屬提供了電性耦接，可於其上放置電性耦接件，如，銲球/凸塊、導電柱或與其相似者。在某些實施例中，凸塊下金屬包括擴散阻障層、晶種層或其組合。擴散阻障層可包括Ti、TiN、Ta、TaN或其組合。晶種層可包括銅或銅合金。然而，亦可包括其他金屬，譬如鎳、鈀、銀、金、鋁、上述之組合及 尤其所組成的多層結構。在某些實施例中，凸塊下金屬是利用濺鍍所形成。在其他實施例中，亦可利用電鍍。
根據某些實施例，可在凸塊下金屬上形成連接件410。連接件410可為銲球、金屬柱、控制塌陷晶片連接(C4(Controlled Collapse Chip Connection，C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)所形成之凸塊、上述之組合(如，金屬柱尚接有銲球)或與其相似者。連接件410可包括導電材料，譬如銲料、銅、鋁、金、鎳、銀、鈀、錫、與其相似者或其組合。在某些實施例中，連接件410包括共晶材料且可包括譬如銲接凸塊或銲球。銲接材料可為，舉例來說，含鉛及不含鉛的銲料，譬如Pb-Sn組合物可用作含鉛銲料；不含鉛銲料則包括InSb；錫、銀及銅(tin,silver,and copper，SAC)組合物；以及具有共同熔點且在電子應用中可形成導電銲料連接的其他共晶材料。在不含鉛銲料中，可使用具有不同組成的SAC銲料，譬如SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305以及SAC 405。亦可由SnCu化合物來形成不含鉛連接件譬如銲球，而不使用銀(Ag)。或者是，不含鉛銲料連接件可包括錫及銀(Sn-Ag)而不使用銅。連接件410可形成格柵，譬如球柵陣列(ball grid array，BGA)。在某些實施例中，可進行回銲製程，以使得連接件410在某些實施例中具有部分球型的外型。或者是，連接件410可包括其他形狀。舉例來說，連接件410亦可包括非球型導電連接件。
在某些實施例中，連接件410包括利用濺鍍、印刷、電鍍、無電式電鍍、CVD或相似技術所形成的金屬柱(譬如銅柱)，且其上可以具有或不具有銲接材料。金屬柱可不含銲料，且具有實質上垂直之側壁或傾斜之側壁。
接著，將載板100自緩衝層102分離，如圖5所示。若 有使用釋放層，則亦將其自緩衝層102清除。舉例來說，當使用含環氧樹脂的熱釋放材料時，上述材料在加熱後會喪失黏著性質，因此可加熱所述結構而將載板100分離。在另一種例子中，當使用紫外(UV)膠釋放層時，將釋放層暴露於UV光而使載板分離。在又另一種例子中，釋放層是以液態形式施佈並固化。可任選地，亦可將緩衝層102由所述結構移除。
圖6繪示將元件600及封裝602接合到RDL 400上位於和晶粒200相反側之結構。在某些實施例中，隨著膜塑材料300與RDL 400總厚度的不同，結構的翹曲可能造成問題。若翹曲會造成問題，則在將元件600及封裝602接合到該結構過程中，可能會需要載板100來支撐該結構。在此一情形中，會在將元件600及封裝602接合到上述結構之後(而非在這之前)，才移除載板100。
在某些實施例中，將元件600表面安裝至上述結構。可取決於特定實施例的設計與需求，利用任何類型的表面安裝元件，且可包括分離的裝置、被動表面安裝元件(例如電阻器及電容器)還有主動元件，譬如電晶體、二極體及放大器。亦可將包括安裝於封裝基板上並封裝於膜塑材料中的一或多個晶粒的封裝602連接到所述結構。舉例來說，封裝602可包括積體電路晶粒，譬如靜態隨機存取記憶體(SRAM)晶片或動態隨機存取記憶體(DRAM)晶片、處理器、記憶體晶片、邏輯晶片、類比晶片、數位晶片、中央處理單元(CPU)、圖形處理單元(GPU)、基頻處理器、微控制器單元(MCU)、射頻(RF)晶片、感應器晶片、微機電系統(MEMS)晶片或上述之組合或與其相似者。在某些實施例中，在將一或多個封裝602接合至所述結構之前或之後，會對其進行測試。舉例來說，在某些實施例中，可在將微機電系統(MEMS)封裝接合到RDL之前或之後對其進行測試。將此種封裝接合至所述結構，而使得在接合之後能 夠取用該封裝以供測試。在某些實施例中，可將封裝於晶圓級晶片尺寸封裝(wafer level chip scale package，WLCSP)中的積體電路晶粒直接結合到位於晶粒200相反側的RDL 400。
在某些實施例中，所述結構經設計使得在所述結構中之元件或封裝之間的電性耦接更為可靠。舉例來說，取決於某些實施例的設計，可將晶粒200放置在RDL的一側，所述側和位於RDL另一側之表面安裝元件表面安裝元件600或封裝602相反，而使得在這兩個裝置在RDL中的連接路徑較短。相較於較長的連接路徑，較短的連接路徑可增加這兩個裝置之間電性耦接的可靠度。此外，某些實施例可經設計而排除對貫穿通路的需求，在許多3D晶圓及/或面板級扇出結構(panel level fan-out structures)中都會用到這種貫穿通路。舉例來說，圖6所繪示的實施例不具有任何延伸通過膜塑材料300的貫穿通路。
接著，將所述結構單粒化為複數個InFO結構700。圖7繪示一InFO結構700的剖面圖。在一特定設計中，每一單粒化的InFO結構700可包括任何數目的晶粒200、元件600及/或封裝602。舉例來說，圖7所繪示的實施例包括兩個晶粒200、一個元件600以及一個封裝602。其他實施例可有更多或更少的每一種所述部件。
參照圖8A及8B，在某些實施例中，InFO結構700連接至印刷電路板(PCB)800，並裝置於外殼806中。基於說明的目的，圖8A及8B所示的InFO結構700和圖7所示者屬於不同的實施例。不論是哪一種上述實施例或其他實施例都是可行的。當InFO結構700及PCB 800連接之後，在本揭露書中統稱為積體電路結構804。圖8A繪示積體電路結構804的剖面圖，而圖8B繪示積體電路結構804的平面圖。
PCB 800對積體電路結構804提供了較高的機械強 度。PCB 800的機械強度高於InFO結構700，且因此可對積體電路結構804提供較強的結構支撐。PCB 800較高的機械強度可用於安裝或連接較大的裝置，這有助於增加積體電路結構804的可靠度。此外，PCB 800較高的機械結構支撐力亦使得將積體電路結構804安裝於產品中的時候，相較於其他情況，能達到更穩固的機械安裝。舉例來說，可利用通孔裝置(譬如螺釘)將PCB 800安裝在一產品中。
在某些實施例中，積體電路結構804可經設計，而使得具有有限I/O需求的較大元件(譬如電池與天線)可安裝於或連接至PCB 800。InFO結構700的機械強度較低，且相較於PCB 800，能在較小的面積中提供更多的I/O連接。因此，積體電路結構804的某些實施例可經設計而使得具有最低I/O需求的較大元件可安裝於或機械連接至PCB 800而非InFO結構700。之後可利用PCB 800中的連接線(如導線810、812)，將上述較大的元件電性連接至InFO結構700。此種設計可將InFO結構700上的空間保留給具有較高I/O需求的較小元件，其係由RDL 400所支撐，且可實現積體電路結構804的進一步微型化，這可能是某些應用中所需要的。舉例來說，圖8A及8B所繪示的實施例中，在PCB 800上具有天線808與電源連接器802裝置。
在某些實施例中，InFO結構700以InFO結構700的一端連接至PCB 800，如圖8A及8B所示。PCB 800與InFO結構700之間的連接可以位在RDL 400上和表面安裝元件600及封裝602相同的表面上。電源連接器802對積體電路結構804提供了和電池(圖中未繪示)的電性耦接。由PCB 800中的導線將電源連接器802及天線808連接至InFO結構700。在某些實施例中，如圖9B所示，導線810將電池的一端連接至InFO結構700，而導線812將電池的另一端連接至InFO結構700。
在某些實施例中，PCB 800利用銲接而連接至InFO結 構700。InFO結構700可延伸超過PCB 800內部空腔邊緣而超出約20微米至2000微米的A距離。如上文所述，銲接材料可為，譬如含鉛與不含鉛銲料，譬如Pb-Sn組合物可用作含鉛銲料；不含鉛銲料則包括InSb；錫、銀及銅(tin,silver,and copper，SAC)組合物；以及具有共同熔點且在電子應用中可形成導電銲料連接的其他共晶材料。在不含鉛銲料中，可使用具有不同組成的SAC銲料，譬如SAC 105(Sn 98.5%、Ag 1.0%、Cu 0.5%)、SAC 305以及SAC 405。亦可由SnCu化合物來形成不含鉛連接件譬如銲球，而不使用銀(Ag)。或者是，不含鉛銲料連接件可包括錫及銀(Sn-Ag)而不使用銅。在某些實施例中，可進行回銲製程，以使得連接件在某些實施例中具有部分球型的外型。或者是，連接件可包括其他形狀。舉例來說，連接件亦可包括非球型導電連接件。在某些實施例中，可利用黏著劑(圖中未繪示)將InFO結構700附接至PCB 800，以提供額外的支撐力。
積體電路結構804裝置於外殼806中。在某些實施例中，積體電路結構804和外殼806形成一獨立的產品，其可用於連接至網際網路。如圖8A所示，InFO結構700的兩端皆受到支撐，一端是由PCB 800支撐，而另一端是由外殼806所支撐。可利用上文所述的方法，將一層RDL 400銲接至接觸墊814，藉以將積體電路結構804固定於外殼806中。在某些實施例中，可利用黏著劑將InFO結構700連接至外殼806。InFO結構700可延伸超過外殼806的邊緣而超出約500微米至2000微米的B距離。
參照圖9A及9B，圖中繪示了積體電路結構804的剖面圖與平面圖，其包括一InFO結構，譬如InFO結構700，連接至PCB 800。不同於圖8A及8B中所示的將InFO結構700以InFO結構700的一側安裝於PCB 800上，圖9A及9B所示的實施例是將InFO結構700放置於PCB 800之開口中，進而將InFO結構700的四個側邊都安裝在PCB 800 上。本實施例可對InFO結構700提供更為堅固的機械支撐。基於說明的目的，圖9A及9B所示的InFO結構700和圖7、8A與8B所示的InFO結構700的不同之處包括，例如晶元與封裝的數目與放置。任何上述實施例或其他實施例都是可行的。
在某些實施例中，如圖9A及9B所示，InFO結構700係配置於PCB 800中的一開口內。電源連接器802係連接至PCB 800。電源連接器802可用以將積體電路結構804連接至電池(圖中未繪示)。天線808亦安裝於PCB 800上。PCB 800中的導電線將電源連接器802及天線808連接至InFO結構700。在某些實施例中，如圖9B所示，導線810將電池的一終端連接至InFO結構700的一側，而導線812將電池的另一終端連接至InFO結構700的第二側。
可利用機械安裝裝置900來將積體電路結構804安裝於外殼806中。舉例來說，機械安裝裝置可為一種貫穿孔裝置，譬如螺釘。亦可基於裝設積體電路裝置之產品的用途與需求，而使用其他適當的機械安裝裝置。
在某些實施例中，積體電路結構804及外殼806包括安裝於一產品中的一個獨立結構。InFO結構700的InFO技術使得可將積體電路結構804微型化，而PCB 800可對較大的連接器與裝置提供機械結構支撐以及穩固的連接，且同時將InFO結構700上的空間保留給有較高I/O需求的元件及封裝。在某些實施例中，積體電路結構804用以連接至網際網路。積體電路結構804的某些實施例可適用於物聯網(Internet of Things，IoT)裝置，而積體電路結構的某些實施例可為微型化的獨立裝置，其可用以連接至網際網路。作為一例，積體電路結構804的某些實施例可用以符合ZigBee聯盟(ZigBee Alliance)提供的一或多種標準。
雖然此處所述的實施例是關於包括安裝於外殼中之獨 立三維InFO與PCB結構且可用於例如家用電器之實施例，其他實施例亦可適用於其他應用。舉例來說，某些實施例可能適用於醫療裝置、家庭自動化、地理位置服務、行動通訊及行銷應用。亦可有多種不同的實施例與應用。
本發明的實施例提供一種製造半導體裝置之方法。上述方法包括將晶粒放置於載板上方、以及在鄰近該晶粒處形成膜塑料。形成重佈層，其係電性耦接至該晶粒並位於該膜塑料上方。移除該載板。連接第一基板至該重佈層之與該晶粒相反的一側上，且該重佈層連接至印刷電路板
本發明的實施例提供一種製造半導體裝置之方法。上述方法包括將複數個晶粒放置於載板上方。沿著該些晶粒之側壁形成膜塑料，其中該膜塑料不具有延伸通過該膜塑料的貫穿通路。形成重佈層，其係電性耦接至該晶粒且位於該膜塑料上方。移除該載板。將一或多個裝置、被動元件及/或封裝放置於該重佈層上方。
本發明的實施例提供一種半導體裝置。上述半導體裝置包括晶粒、及沿著該晶粒之側壁延伸的膜塑料。該半導體裝置亦包括重佈層、基板、及印刷電路板，重佈層位於該膜塑料及該晶粒上方，基板安裝於該重佈層之與該膜塑料相反的一側上，印刷電路板連接至該重佈層。
雖然上文實施方式中揭露了本發明的例示性實施方式，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，當可對其進行各種更動與修飾。因此附隨之申請專利範圍當涵蓋此種更動或實施方式。
200‧‧‧積體電路晶粒
204‧‧‧晶粒附接膜/黏著層
300‧‧‧膜塑材料
400‧‧‧重佈層/RDL
402‧‧‧導電線
404‧‧‧通路
600‧‧‧元件
602‧‧‧封裝
700‧‧‧InFO結構

Claims (10)

  1. 一種製造一半導體裝置的方法，包括：放置一晶粒於一載板上方；形成一膜塑料，其係鄰近該晶粒；形成一重佈層，其係電性耦接至該晶粒並位於該膜塑料上方；移除該載板；連接一第一基板至該重佈層之與該晶粒相反的一側上；以及連接該重佈層至一印刷電路板。
  2. 如請求項1所述之該方法，進一步包括放置一或多個額外晶粒於該載板上，以及形成該膜塑料於該些額外晶粒上方。
  3. 如請求項1所述之該方法，進一步包括連接一電源連接器及天線至該印刷電路板。
  4. 如請求項1所述之該方法，其中該半導體裝置為一獨立裝置，其可用於連接至網際網路。
  5. 如請求項1所述之該方法，進一步包括利用一機械安裝裝置將該印刷電路板安裝於一外殼中。
  6. 如請求項5所述之該方法，進一步包括配置該第一基板於該印刷電路板中之一開口內，以及在該重佈層的一第一點以及該重佈層的一第二點將該重佈層連接至該印刷電路板。
  7. 如請求項1所述之該方法，進一步包括將複數個元件表面安裝於該重佈層之與該膜塑料相反的該側上。
  8. 如請求項1所述之該方法，其中該第一基板包括一封裝，且進一步包括在將該封裝連接至該重佈層之後，測試該封裝。
  9. 一種製造一半導體裝置的方法，包括：放置複數個晶粒於一載板上方； 形成一膜塑料，其係沿著該些晶粒之側壁，其中該膜塑料不具有延伸穿過該膜塑料的一貫穿通路；形成一重佈層，其係電性耦接至該些晶粒並位於該膜塑料上方；移除該載板；以及放置一或多個裝置於該重佈層上。
  10. 一半導體裝置，包括：一晶粒；膜塑料，沿著該晶粒之側壁延伸；一重佈層，位於該膜塑料及該晶粒上方；一基板，安裝於該重佈層之與該膜塑料相反的一側上；以及一印刷電路板，連接至該重佈層。
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CN106024740A (zh) 2016-10-12
KR101923260B1 (ko) 2018-11-28
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US20160295700A1 (en) 2016-10-06
US20190350082A1 (en) 2019-11-14
US11291116B2 (en) 2022-03-29
US10368442B2 (en) 2019-07-30
TW201705438A (zh) 2017-02-01

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