CN106024740A - 集成电路结构及其形成方法 - Google Patents

集成电路结构及其形成方法 Download PDF

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Publication number
CN106024740A
CN106024740A CN201610124108.0A CN201610124108A CN106024740A CN 106024740 A CN106024740 A CN 106024740A CN 201610124108 A CN201610124108 A CN 201610124108A CN 106024740 A CN106024740 A CN 106024740A
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China
Prior art keywords
redistribution layer
tube core
moulding compound
layer
pcb
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CN201610124108.0A
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English (en)
Inventor
余振华
洪瑞斌
余国宠
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106024740A publication Critical patent/CN106024740A/zh
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    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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Abstract

本发明实施例提供了一种集成电路结构及其形成方法。管芯放置在衬底上并且包裹在模塑料中。重分布层形成在管芯上方并且去除衬底。在重分布层的与管芯相对的侧部上，一个或多个表面安装器件和/或封装件连接至重分布层。重分布层连接至印刷电路板。

Description

集成电路结构及其形成方法
相关申请的交叉参考
本申请要求于2015年3月30日提交的美国临时专利申请第62/140,356号的优先权，该申请结合于此作为参考。
技术领域
本发明实施例涉及集成电路结构及其形成方法。
背景技术
半导体器件用于多种电子应用，诸如个人计算机、手机、数码相机和其他的电子设备。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化该多个材料层，以在该多个材料层上形成电路组件和元件。通常在单个半导体晶圆上制造数十或数百集成电路。通过沿着划割线锯切集成电路来切割单独的管芯。然后，通常以多芯片模块或以其他的封装类型将单独的管芯分别封装。
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断提高，半导体行业已经历了快速的发展。在很大程度上，集成密度的这种提高源自于最小部件尺寸的不断减小(例如，将半导体工艺节点减小至亚20nm节点)，这允许在给定区域内集成更多的组件。由于对小型化的需求，近来已经发展了更高速度和更大带宽以及更低功耗和延迟，所以已经产生了对用于半导体管芯的一种更小且更富创造性的封装技术的需要。
随着半导体技术的进一步发展，已经出现了堆叠的半导体器件(例如，三维集成电路(3DIC))作为有效替代以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中，在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个或更多的半导体晶圆可以安装或堆叠在彼此的顶部上以进一步降低半导体器件的形状因数。叠层封装(POP)器件是一种类型的3DIC，其中，封装管芯并且然后将管芯与另一封装的一个管芯或多个管芯封装在一起。
发明内容
根据本发明的一些实施例，提供了一种制造半导体器件的方法，包括：将管芯放置在载体衬底上方；邻近所述管芯形成模塑料；形成电连接至所述管芯并且位于所述模塑料上方的重分布层；去除所述载体衬底；在所述重分布层的与所述管芯相对的侧部上将第一衬底连接至所述重分布层；以及将所述重分布层连接至印刷电路板。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：将多个管芯放置在载体衬底上方；沿着所述管芯的侧壁形成模塑料，其中，所述模塑料中不存在延伸穿过所述模塑料的通孔；形成电连接至所述管芯并且位于所述模塑料上方的重分布层；去除所述载体衬底；以及将一个或多个器件放置在所述重分布层上。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：管芯；模塑料，沿着所述管芯的侧壁延伸；重分布层，位于所述模塑料和所述管芯上方；衬底，在所述重分布层的与所述模塑料相对的侧部上安装至所述重分布层；以及印刷电路板，连接至所述重分布层。
附图说明
为了更全面地理解本发明及其优点，现在结合附图所进行的一些描述作为参考，其中：
图1至图7是根据示例性实施例的在集成电路结构的制作的中间阶段的截面图；以及
图8A、图8B、图9A和图9B是根据示例性实施例的集成电路结构的截面图和平面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
将关于具体背景下的实施例来描述实施例，即，例如，安装在壳体中并且适用于家用器具的独立的三维(3D)集成扇出(InFO)封装件和印刷电路板(PCB)结构。其他的实施例可以适用于其他的应用。例如，一些实施例可以适用于医疗设备、家庭自动化、地理位置服务、移动通信和行销应用。许多不同的实施例和应用都是可能的。
根据各个示例性实施例提供了集成电路结构及其形成方法。示出了形成集成电路结构的中间阶段并且讨论了实施例的变形。
图1至图7示出了根据一些实施例的形成集成电路结构的中间步骤的截面图。首先参考图1，示出了载体衬底100和缓冲层102。通常地，载体衬底100在后续的加工步骤中提供临时的机械和结构支撑。例如，载体衬底100可以包括任何合适的材料，诸如硅基材料(诸如硅晶圆、玻璃或氧化硅)或其他材料(诸如氧化铝、陶瓷材料)、这些材料的任意组合等。在一些实施例中，为了适应进一步的加工，载体衬底100是平坦的。
可选的释放层(未示出)可以形成在载体衬底100上方，可以允许更加容易地去除载体衬底100。如下面更详细的解释，各个层和器件将放置在载体衬底100的上方，之后可以去除载体衬底100。可选的释放层有助于载体衬底100的去除，减少了对形成在载体衬底100上方的结构的损坏。释放层可以由基于聚合物的材料形成。在一些实施例中，释放层是诸如光热转换(LTHC)释放涂层的环氧化物基热释放材料，该材料在被加热时失去其粘性。在其他实施例中，释放层可以是紫外(UV)胶，当紫外(UV)胶暴露于UV光时，失去其粘性。释放层可以作为液体被分配并且被固化。在其他实施例中，释放层可以是层压到载体衬底100上的层压膜。可以使用其他释放层。
缓冲层102形成在载体衬底100上方。缓冲层102是介电层，该介电层可以是聚合物(诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等)、氮化物(诸如氮化硅等)、氧化物(诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)或它们的组合等)等，并且例如，可以通过旋涂、层压、化学汽相沉积(CVD)等来形成。在一些实施例中，缓冲层102是在工艺变化范围内具有均匀厚度的平面层，其中该厚度可以介于约5μm与约20μm之间。缓冲层102的顶面和底面也在工艺变化范围内是平坦的。
根据一些实施例，图2示出了将多个集成电路管芯200附接至缓冲层102的背侧。在一些实施例中，集成电路管芯200可以通过粘合层204(诸如管芯附接膜(DAF))粘附于缓冲层102。在实施例中，如图2所示，管芯附接膜204可以仅位于集成电路管芯200的正下方。在其他的实施例中，管芯附接膜204可以延伸至邻近的集成电路管芯200之间的缓冲层102上方。粘合层的厚度可以在从约5μm至约50μm的范围内，诸如约20μm。可以使用任何数量的集成电路管芯200，并且集成电路管芯200可以包括适用于特殊途径的任何管芯。例如，集成电路管芯200可以包括静态随机存取存储器(SRAM)芯片或动态随机存取存储器(DRAM)芯片、处理器、存储芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)、图形处理单元(GPU)、基带处理器、微控制器单元(MCU)、射频(RF)芯片、传感器芯片、微机电系统(MEMS)芯片、集成无源器件(IPD)或它们的组合等。在附接至缓冲层102之前，可以根据可应用的制造工艺处理集成电路管芯200以在集成电路管芯200之上形成集成电路。每个管芯200都可以包括连接至粘合层的衬底(例如，硅衬底)，其中，半导体衬底的背面与粘合层连接。
在一些示例性实施例中，管芯200包括接触件202(诸如铜柱)，该接触件电连接至诸如管芯200中的晶体管的器件。在一些实施例中，介电层(未示出)形成在相应的管芯200的顶面处，接触件202的至少下部位于介电层中。在一些实施例中，接触件202的顶面还可以与介电层的顶面平齐。可选地，接触件202可以突出于相应的管芯200的顶层之上和/或没入该相应的管芯的顶层之下。在其他的实施例中，其他的结构可以用于接触件202，诸如迹线、金属柱、铜接线柱、金接线柱等。
参考图3，模制材料300被模制和/或层压在管芯200上。模制材料300填充管芯200之间的间隙，并且可以与缓冲层102接触。此外，当接触件202的一部分突出时，模制材料300被填充到接触件202之间的间隙中。模制材料300可以包括模塑料、模制底部填充物、环氧树脂、树脂、干膜等。在一些实施例中，模制材料300的顶面高于接触件202的顶端。
可以执行研磨步骤以减薄模制材料300，从而暴露接触件202。图3示出了所得到的结构。由于研磨，接触件200的顶端与模制材料300的顶面基本齐平(共面)。作为研磨的结果，可以生成诸如金属颗粒的金属残留物，并且留在模制材料300和接触件202的顶面上。因此，在研磨之后，可以例如通过湿蚀刻执行清洁，使得去除金属残留物。
接下来，参考图4，形成一个或多个重分布层(RDL)400。通常，RDL提供与金属柱图案不同的允许用于完整的封装件的引脚输出接触图案的导电图案，以允许更加灵活地放置管芯200。RDL可以用于提供至管芯200的外部电连接。RDL包括导线402和通孔404，其中通孔404将上面的线连接至下面的导电部件(例如，接触件202和/或导线402)。例如，导线402可以沿着任何方向延伸至纸面的左边或右边或者延伸进纸面或从纸面向外延伸。
可以使用任何合适的工艺来形成RDL。例如，在一些实施例中，介电层形成在模制材料300和集成电路管芯200上。在一些实施例中，介电层由聚合物形成，聚合物可以是使用光刻可以图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。在其他实施例中，介电层由诸如氮化硅的氮化物、诸如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等形成。介电层可以通过旋涂、层压、CVD等或它们的组合来形成。然后，介电层被图案化以形成开口来暴露接触件202。在实施例中，介电层由光敏材料形成，可以按照所需的图案通过暴露介电层来执行图案化并且显影以去除不期望的材料，从而暴露接触件202。其他方法，诸如使用图案化的掩模和蚀刻，也可以用于图案化介电层。
晶种层(未示出)形成在介电层上方，以及形成在形成于介电层中的开口中。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同的材料形成的多个子层的复合层。在一些实施例中，该晶种层包括钛层和钛层上方的铜层。可以使用例如PVD等形成晶种层。然后根据期望的重分布图案(诸如图4所示的图案)在晶种层上形成并图案化掩模。在一些实施例中，掩模是通过旋涂等形成并且暴露于光以用于图案化的光刻胶。图案化形成穿过掩模的开口以暴露晶种层。在掩模的开口中和晶种层的暴露部分上形成导电材料。可以通过诸如电镀或化学镀等的镀来形成导电材料。导电材料可以包括如铜、钛、钨、铝等的金属。然后，去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过诸如使用氧等离子体等的可接受的灰化或剥离工艺去除光刻胶。一旦去除光刻胶，诸如通过使用可接受的蚀刻工艺(诸如通过湿蚀刻或干蚀刻)去除晶种层的暴露部分。晶种层和导电材料的剩余部分形成导线402和通孔404。
尽管以上描述了一层RDL的形成，但是可以重复工艺以创建一层以上的RDL，这取决于特定的途径的设计。例如，图4示出了一层RDL。多层RDL也是可能的。
接下来，根据一些实施例，钝化层406可以形成在最上面的金属化图案的上方。钝化层可以由聚合物形成，聚合物可以是使用光刻掩模图案化的诸如PBO、聚酰亚胺、BCB等的光敏材料。在其他实施例中，钝化层由诸如氮化硅、氧化硅、PSG、BSG、BPSG等的氮化物或氧化物形成。可以通过旋涂、层压、CVD等或它们的组合形成钝化层。然后图案化钝化层以暴露下面的金属化层的一部分。可以通过可接受的工艺进行图案化，诸如当介电层是光敏材料时通过将钝化层暴露于光或者例如通过使用各向异性蚀刻的蚀刻。接下来，在钝化层上方并且穿过钝化层形成凸块下金属(UBM)408并且图案化该凸块下金属，从而形成与最上面的金属化层的电连接。凸块下金属提供了电连接，可以在该凸块下金属上面放置电连接件(例如，焊球/凸块、导电柱等)。在一些实施例中，凸块下金属包括扩散阻挡层、晶种层或它们的组合。扩散阻挡层可以包括Ti、TiN、Ta、TaN或它们的组合。晶种层可以包括铜或铜合金。然而，其他金属，诸如镍、钯、银、金、铝、它们的组合以及它们的多层也可以包括在内。在一些实施例中，使用溅射形成凸块下金属。在其他实施例中，可以使用电镀。
根据一些实施例，在凸块下金属上方形成连接件410。连接件410可以是焊球、金属柱、可控坍塌芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块、它们的组合(例如，具有与其附接的焊球的金属柱)等。连接件410可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，如实例，连接件410包括共晶材料并且可以包括焊料凸块或焊球。例如，焊料材料可以是例如，铅基和无铅焊料，诸如用于铅基焊料的Pb-Sn组分；包括InSb的无铅焊料；锡、银和铜(SAC)组分；以及具有共同熔点并且在电气应用中形成导电焊料连接件的其它共晶材料。例如，对于无铅焊料来说，可以使用具有不同组分的SAC焊料，诸如SAC 105(Sn98.5％、Ag1.0％、Cu0.5％)、SAC 305和SAC 405。诸如焊球的无铅连接件也可以由SnCu化合物形成，而不使用银(Ag)。可选地，无铅焊料连接件可以包括锡和银、Sn-Ag，而不使用铜。连接件410可以形成栅格，诸如球栅格阵列(BGA)。在一些实施例中，可以执行回流工艺，在一些实施例中给出局部球形形状的连接件410a。可选地，连接件410可以包括其他形状。例如，连接件410也可以包括非球形导电连接件。
在一些实施例中，连接件410包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)，在连接件528上具有或不具有焊料材料。金属柱可以无焊料并且具有基本垂直的侧壁或锥形的侧壁。
接下来，如图5所示，将载体衬底100与缓冲层102脱离。如果存在，还从缓冲层102上清洗释放层。例如，在环氧树脂基热释放材料的情况中，当加热时该材料失去其粘合特性，加热结构并且载体衬底100脱离。作为另一实例，在紫外(UV)胶释放层的情况中，将释放层暴露于UV光并且载体脱离。作为另一实例，释放层可以作为液体被分配并且被固化。可选地，还可以从结构去除缓冲层102。
图6示出了将组件600和封装件602接合至RDL 400的与管芯200相对的一侧上的结构。在一些实施例中，取决于模制材料300和RDL 400的总厚度，结构的翘曲会成为一个问题。如果考虑翘曲，那么需要载体衬底100来在将组件600和封装件602接合至结构期间支撑结构。在这种情况中，在将组件600和封装件602接合至结构之后(而不是之前)使载体衬底100脱离。
在一些实施例中，组件600表面安装至结构。可以使用任何类型的表面安装的组件，这取决于特殊实施例的设计和要求，并且可以包括离散的器件、无源表面安装的组件(例如，电阻器和电容器)以及有源器件(例如，晶体管、二极管和放大器)。包括安装在封装衬底上并且包裹在模制材料中的一个或多个管芯的封装件602也可以连接至结构。例如，封装件602可以包括集成电路管芯，诸如静态随机存取存储器(SRAM)芯片或动态随机存取存储器(DRAM)芯片、处理器、存储芯片、逻辑芯片、模拟芯片、数字芯片、中央处理单元(CPU)、图形处理单元(GPU)、基带处理器、微控制器单元(MCU)、射频(RF)芯片、传感器芯片、微机电系统(MEMS)芯片或它们的组合等。在一些实施例中，将在接合至结构之前和之后测试一个或多个封装件602。例如，在一些实施例中，可以在接合至RDL之前或之后测试微机电系统(MEMS)封装件。将以在接合之后允许访问用于测试目的的封装件的方式使这种封装件接合至封装件。在一些实施例中，封装在晶圆级芯片规模封装件(WLCSP)中的集成电路管芯可以直接接合至与管芯200相对的RDL 400。
在一些实施例中，以允许结构中的组件或封装件之间的电连接具有增强的可靠性的方式设计结构。例如，取决于一些实施例的设计，以在两个器件之间的RDL中存在较短的连接路径的方式，可以将管芯200放置在RDL的与位于RDL的另一侧上的表面安装的组件600或封装件602相对的一侧上。与更长的连接路径相比，较短的连接路径增加了两个器件之间的电连接的可靠性。附加地，可以以不需要通孔(通常用于许多3D晶圆和/或平板级扇出结构中)的方式来设计一些实施例。例如，图6示出的实施例不具有延伸穿过模制材料300的任何通孔。
接下来，将结构分割为多个InFO结构700。图7示出了一个InFO结构700的截面图。每一个分割的InFO结构700都可以包括用于特殊设计的任何数量的管芯200、组件600和/或封装件602。例如，图7示出了包括两个管芯200、一个组件600和一个封装件602的实施例。其他的实施例可以具有每个元件的更多或更少的数量。
现在参考图8A和图8B，在一些实施例中，InFO结构700连接至印刷电路板(PCB)800并且安装在壳体806中。为了说明的目的，图8A和图8B中的InFO结构700示出了与图7不同的InFO结构700的实施例。任一实施例或其他的实施例都是可能的。在本文中，连接的InFO结构700和PCB 800一起被称为集成电路结构804。图8A示出了集成电路结构804的截面图，而图8B示出了集成电路结构804的平面图。
PCB 800为集成电路结构804提供了增强的机械强度。PCB 800可以比InFO结构700更具机械强度，并且因此可以为集成电路结构804提供增强的机械支撑。PCB 800的增强的机械强度可以用于安装或连接至更大的器件，这可以帮助增强集成电路结构804的可靠性。而且，PCB 800的增强的机械结构可以使得产品中的集成电路结构804的比以其他方式更加安全的机械安装成为可能。例如，PCB 800可以允许使用通孔器件(例如，螺钉)将集成电路结构804安装在产品中。
在一些实施例中，可以以具有有限的I/O需求的更大的组件(诸如电池和天线)安装在PCB 800上或连接至PCB 800的方式来设计集成电路结构804。与PCB 800相比，InFO结构700具有更低的机械强度，并且可以在更小的面积内支撑增加的I/O连接件。这样，可以设计集成电路结构804的一些实施例，从而使得具有最小I/O需求的更大的组件安装在PCB 800(而不是InFO结构700)上并机械连接至PCB 800。然后，使用PCB 800中的连接迹线(例如，迹线810、812)将更大的组件电连接至InFO结构700。这种设计可以保持InFO结构700上的用于具有较高I/O需求的更小的组件的空间，其被RDL 400支撑，并且使得集成电路结构804的增强的小型化成为可能，这可以满足一些应用。例如，图8A和图8B示出了具有安装在PCB 800上的天线808和电源连接件802的实施例。
在一些实施例中，如图8A和图8B所示，InFO结构700在InFO结构700的一端处连接至PCB 800。PCB 800与InFO结构700之间的连接可以位于RDL 400的与表面安装的组件600和封装件602相同的表面上。电源连接件802提供电池(未示出)至集成电路结构804的电连接。电源连接件802和天线808通过PCB 800中的导电迹线连接至InFO结构700。在一些实施例中，如图9B所示，迹线810将电池的端部连接至InFO结构700，并且迹线812将电池的另一端连接至InFO结构700。
在一些实施例中，使用焊接将PCB 800连接至InFO结构700。InFO结构700可以以20μm至2000μm的距离A延伸越过PCB 800的内腔边缘。如上所述，例如，焊料材料可以是例如，铅基和无铅焊料，诸如用于铅基焊料的Pb-Sn组分；包括InSb的无铅焊料；锡、银和铜(SAC)组分；以及具有共同熔点并且在电气应用中形成导电焊料连接件的其它共晶材料。例如，对于无铅焊料来说，可以使用具有不同组分的SAC焊料，诸如SAC105(Sn98.5％、Ag1.0％、Cu0.5％)、SAC 305和SAC 405。诸如焊球的无铅连接件也可以由SnCu化合物形成，而不使用银(Ag)。可选地，无铅焊料连接件可以包括锡和银、Sn-Ag，而不使用铜。在一些实施例中，可以执行回流工艺，在一些实施例中给出局部球形形状的连接件。可选地，连接件可以包括其他形状。例如，连接件也可以包括非球形导电连接件。在一些实施例中，可以使用粘合剂(未示出)将InFO结构700附接至PCB800以提供附加的支撑。
集成电路结构804安装在壳体806中。在一些实施例中，集成电路结构804和壳体806形成配置为连接至互联网的独立的产品。如图8A所示，InFO结构700在两端上被支撑，一端被PCB 800支撑，第二端被壳体806支撑。可以使用先前描述的方法通过将RDL 400的层焊接至接触焊盘814来将集成电路结构804固定在壳体806中。在一些实施例中，可以使用粘合剂将InFO结构700连接至壳体806。InFO结构700可以以500μm至2000μm的距离B延伸越过壳体806的边缘。
参考图9A和图9B，提供了集成电路结构804的截面图和平面图，集成电路结构804包括连接至PCB 800的InFO结构，诸如InFO结构700。代替如图8A和图8B所示的在InFO结构700的一侧上将InFO结构700安装至PCB 800，图9A和图9B示出了通过将InFO结构700放置在PCB 800中的开口中来在InFO结构700的四个侧部上将InFO结构700安装至PCB800的实施例。该实施例可以为InFO结构700提供更加强健的机械支撑。为了说明的目的，图9A和图9B中的InFO结构700示出了与图7、图8A和图8B的InFO结构700不同的实施例，例如，在管芯和封装件的数量和放置上。任何的这些实施例或其他的实施例都是可能的。
在一些实施例中，如图9A和图9B所示，InFO结构700布置在PCB 800中的开口中。电源连接件802连接至PCB 800。电源连接件802可以用于将集成电路结构804连接至电池(未示出)。天线808也安装在PCB 800上。PCB 800中的导线将电源连接件802和天线808连接至InFO结构700。在一些实施例中，如图9B所示，迹线810将电池的一端连接至InFO结构700的一侧，并且迹线812将电池的另一端连接至InFO结构700的第二侧。
机械安装器件900可以用于将集成电路结构804安装在壳体806中。例如，机械安装器件可以是通孔器件，诸如螺钉。可以使用其他合适的机械安装器件，这取决于其中安装集成电路器件的产品的途径和需要。
在一些实施例中，集成电路结构804和壳体806包括安装在产品中的独立的结构。InFO结构700的InFO技术允许集成电路结构804的小型化，而PCB 800提供用于更大的连接件和器件的机械结构支撑和安全的连接，同时节省了InFO结构700上的用于具有更高I/O需求的组件和封装件的空间。在一些实施例中，集成电路结构804配置为连接至互联网。由于集成电路器件的一些实施例可以是配置为连接至互连网的小型化的独立的器件，所以集成电路结构804的一些实施例可以适合于物联网(IoT)器件。作为实例，集成电路结构804的一些实施例可以配置为遵守ZigBee Alliance发布的一个或多个标准。
例如，尽管本文关于包括安装在壳体中并且适用于家用器具的独立的三维InFO和PCB结构的实施例描述了实施例，但是其他的实施例可以适用于其他的应用。例如，一些实施例可以适用于医疗设备、家庭自动化、地理位置服务、移动通信和行销应用。许多不同的实施例和应用都是可能的。
本发明的实施例提供了制作半导体器件的方法。方法包括：将管芯放置在载体衬底上方并且邻近管芯形成模塑料。形成电连接至管芯并且位于模塑料上面的重分布层。去除载体衬底。在重分布层的与管芯相对的侧部上将第一衬底连接至重分布层，并且将重分布层连接至印刷电路板。
本发明的实施例提供了制作半导体器件的方法。方法包括：将多个管芯放置在载体衬底上方。沿着管芯的侧壁形成模塑料，其中模塑料中不存在延伸穿过模塑料的通孔。形成电连接至管芯并且位于模塑料上面的重分布层。去除载体衬底。将一个或多个器件、无源组件和/或封装件放置在重分布层上。
本发明的实施例提供了一种半导体器件。半导体器件包括管芯和沿着管芯的侧壁延伸的模塑料。重分布层位于模塑料和管芯上方。在重分布层的与模塑料相对的侧部上将衬底安装至重分布层。将印刷电路板连接至重分布层。
根据本发明的一些实施例，提供了一种制造半导体器件的方法，包括：将管芯放置在载体衬底上方；邻近所述管芯形成模塑料；形成电连接至所述管芯并且位于所述模塑料上方的重分布层；去除所述载体衬底；在所述重分布层的与所述管芯相对的侧部上将第一衬底连接至所述重分布层；以及将所述重分布层连接至印刷电路板。
在上述方法中，还包括：将一个或多个附加的管芯放置在所述载体衬底上方并且在所述附加的管芯上方形成所述模塑料。
在上述方法中，还包括：将电源连接件连接至所述印刷电路板。
在上述方法中，所述半导体器件是配置为连接至互联网的独立的器件。
在上述方法中，还包括：使用机械安装器件将所述印刷电路板安装在壳体中。
在上述方法中，还包括：将所述第一衬底布置在所述印刷电路板中的开口中，并且在所述重分布层的第一点和所述重分布层的第二点处将所述重分布层连接至所述印刷电路板。
在上述方法中，还包括：在所述重分布层的与所述模塑料相对的侧部上将多个组件表面安装在所述重分布层上。
在上述方法中，所述第一衬底包括封装件，并且还包括在将所述封装件连接至所述重分布层之后测试所述封装件。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，包括：将多个管芯放置在载体衬底上方；沿着所述管芯的侧壁形成模塑料，其中，所述模塑料中不存在延伸穿过所述模塑料的通孔；形成电连接至所述管芯并且位于所述模塑料上方的重分布层；去除所述载体衬底；以及将一个或多个器件放置在所述重分布层上。
在上述方法中，所述一个或多个器件包括至少一个表面安装器件和至少一个半导体封装件。
在上述方法中，还包括：将所述半导体封装件和所述表面安装器件布置在印刷电路板中的开口。
在上述方法中，所述表面安装器件是无源器件。
在上述方法中，还包括：使用焊料将所述重分布层连接至印刷电路板。
在上述方法中，还包括：将天线连接至所述重分布层。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：管芯；模塑料，沿着所述管芯的侧壁延伸；重分布层，位于所述模塑料和所述管芯上方；衬底，在所述重分布层的与所述模塑料相对的侧部上安装至所述重分布层；以及印刷电路板，连接至所述重分布层。
在上述器件中，所述重分布层具有多个边缘，一个或多个边缘电连接至所述印刷电路板，剩余的边缘连接至壳体。
在上述器件中，还包括：多个表面安装器件，安装在所述重分布层的与所述模塑料相对的侧部上。
在上述器件中，使用焊料将所述印刷电路板连接至所述重分布层，并且所述印刷电路板连接至所述重分布层的与所述衬底相同的侧部上。
在上述器件中，所述衬底布置在所述印刷电路板中的开口中。
在上述器件中，天线连接至所述重分布层。
尽管关于说明性的实施例描述了本发明，但是该描述不意欲被解释为限制意义。对于本领域的普通技术人员来说，参考该描述，说明性的实施例的各种改变和组合以及本发明的其他的实施例都是显而易见的。因此，所附权利要求包含任何这种改版或实施例。

Claims (10)

1.一种制造半导体器件的方法，包括：
将管芯放置在载体衬底上方；
邻近所述管芯形成模塑料；
形成电连接至所述管芯并且位于所述模塑料上方的重分布层；
去除所述载体衬底；
在所述重分布层的与所述管芯相对的侧部上将第一衬底连接至所述重分布层；以及
将所述重分布层连接至印刷电路板。
2.根据权利要求1所述的方法，还包括：将一个或多个附加的管芯放置在所述载体衬底上方并且在所述附加的管芯上方形成所述模塑料。
3.根据权利要求1所述的方法，还包括：将电源连接件连接至所述印刷电路板。
4.根据权利要求1所述的方法，其中，所述半导体器件是配置为连接至互联网的独立的器件。
5.根据权利要求1所述的方法，还包括：使用机械安装器件将所述印刷电路板安装在壳体中。
6.根据权利要求5所述的方法，还包括：将所述第一衬底布置在所述印刷电路板中的开口中，并且在所述重分布层的第一点和所述重分布层的第二点处将所述重分布层连接至所述印刷电路板。
7.根据权利要求1所述的方法，还包括：在所述重分布层的与所述模塑料相对的侧部上将多个组件表面安装在所述重分布层上。
8.根据权利要求1所述的方法，其中，所述第一衬底包括封装件，并且还包括在将所述封装件连接至所述重分布层之后测试所述封装件。
9.一种制造半导体器件的方法，包括：
将多个管芯放置在载体衬底上方；
沿着所述管芯的侧壁形成模塑料，其中，所述模塑料中不存在延伸穿过所述模塑料的通孔；
形成电连接至所述管芯并且位于所述模塑料上方的重分布层；
去除所述载体衬底；以及
将一个或多个器件放置在所述重分布层上。
10.一种半导体器件，包括：
管芯；
模塑料，沿着所述管芯的侧壁延伸；
重分布层，位于所述模塑料和所述管芯上方；
衬底，在所述重分布层的与所述模塑料相对的侧部上安装至所述重分布层；以及
印刷电路板，连接至所述重分布层。
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