CN115910814A - 形成封装结构的方法 - Google Patents

形成封装结构的方法 Download PDF

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Publication number
CN115910814A
CN115910814A CN202211615779.9A CN202211615779A CN115910814A CN 115910814 A CN115910814 A CN 115910814A CN 202211615779 A CN202211615779 A CN 202211615779A CN 115910814 A CN115910814 A CN 115910814A
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Prior art keywords
conductive
package
forming
semiconductor device
buffer layer
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CN202211615779.9A
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郑心圃
陈硕懋
许峯诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN115910814A publication Critical patent/CN115910814A/zh
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Abstract

封装结构包括第一介电层、第一半导体装置、第一重分布线、第二介电层、第二半导体装置、第二重分布线、第一导电件及第一模制材料。第一半导体装置在第一介电层上方。第一重分布线在第一介电层中且电连接至第一半导体装置。第二介电层在第一半导体装置上方。第二半导体装置在第二介电层上方。第二重分布线在第二介电层中且电连接至第二半导体装置。第一导电件电连接第一重分布线与第二重分布线。第一模制材料模制第一半导体装置及第一导电件。

Description

形成封装结构的方法
本申请是申请日为2017年12月7日、申请号为201711288268.X、发明名称为“封装结构”的专利申请的分案申请。
技术领域
本揭露是有关于一种封装结构及一种形成封装结构的方法。
背景技术
半导体工业通过不断减小最小特征尺寸来持续提高各电子组件(例如，晶体管、二极管、电阻器、电容器等等)的整合密度，减小最小特征尺寸的方式允许更多组件整合至指定区域中。这些较小的电子组件在一些应用中亦要求更小封装，利用比过去封装更少的面积。用于半导体的一些更小类型的封装包括四方扁平封装(quad flat pack；QFP)、针栅阵列(pin grid array；PGA)、球栅阵列(ball grid array；BGA)、覆晶(flip chips；FC)、三维集成电路(three dimensional integrated circuits；3DIC)、晶圆级封装(wafer levelpackages；WLPs)、轨迹上粘合(bond-on-trace；BOT)封装、及层叠封装(package onpackage；PoP)结构。
发明内容
根据本揭露多个实施方式，一种形成封装结构的方法包括以下步骤。形成一第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及该第一导电通孔。形成一第一重分布线，该第一重分布线电连接该第一导电通孔的一第一端及该第一半导体装置，使得该第一缓冲层、该第一导电通孔、该第一半导体装置、该第一模制材料、及该第一重分布线形成一第一封装。形成一第一导电球体于该第一重分布线上方并电连接该第一重分布线。形成一第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及该第二导电通孔。形成一第二重分布线，该第二重分布线电连接该第二导电通孔的一第一端及该第二半导体装置，使得该第二缓冲层、该第二导电通孔、该第二半导体装置、该第二模制材料、及该第二重分布线形成一第二封装。形成一第二导电球体于该第二重分布线上方并电连接该第二重分布线。翻转该第一封装。在翻转该第一封装后，在该第一缓冲层中形成一开口以暴露该第一导电通孔的一第二端。翻转该第二封装。在翻转该第二封装后，将该第二封装堆叠于该第一封装上，使得该第二导电球体位于该第一导电通孔的该第二端并电连接该第一导电通孔的该第二端。
根据本揭露多个实施方式，一种形成封装结构的方法包括以下步骤。形成一第一封装及形成一第二封装。形成第一封装包括以下步骤。形成多个第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔。形成多个第一重分布线于该第一模制材料上。形成多个第一导电球体于所述多个第一重分布线上方。形成第二封装包括以下步骤。形成多个第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔。形成多个第二重分布线于该第二模制材料上。形成多个第二导电球体于所述多个第二重分布线上方。形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔。通过放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，以接合该第二封装至该第一封装。
根据本揭露多个实施方式，一种形成封装结构的方法包括以下步骤。形成一第一封装及形成一第二封装。形成第一封装包括以下步骤。形成多个第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔。形成多个第一重分布线于该第一模制材料上。形成多个第一导电球体于所述多个第一重分布线上方。形成第二封装包括以下步骤。形成多个第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔。形成多个第二重分布线于该第二模制材料上。形成多个第二导电球体于所述多个第二重分布线上方。形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔。接合所述多个第二导电球体至所述多个第一导电通孔，使得所述多个第二导电球体在垂直方向上位于所述多个第一导电通孔与所述多个第二导电通孔之间。
附图说明
当结合附图阅读时，自以下详细描述最佳地理解本揭露的态样。应当注意，根据工业中的标准实务，各特征并未按比例绘制。事实上，为论述清楚，各特征的大小可任意地增加或缩小。
图1至图19为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图；
图20为根据本揭露的一些实施方式的半导体组件的剖面图；
图21至图22为在图17的步骤后的制造封装结构的中间阶段的剖面图；
图23为根据本揭露的一些实施方式的封装结构的剖面图；
图24至图32为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图；
图33为根据本揭露的一些实施方式的模制封装的剖面图；
图34为根据本揭露的一些实施方式的模制封装的剖面图；
图35为根据本揭露的一些实施方式的封装结构的剖面图；
图36至图51为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图；
图52为根据本揭露的一些实施方式的集成扇出型封装的剖面图；
图53为根据本揭露的一些实施方式的集成扇出型封装的剖面图；
图54为根据本揭露的一些实施方式的封装结构的剖面图。
具体实施方式
以下揭露提供许多不同实施方式或例子，以实现所提供的标的的不同特征。下文描述的组件及排列的特定实例以简化本揭露。当然，这些仅仅为实例且不意欲作为限制。例如，在随后描述中在第二特征上方或在第二特征上的第一特征的形成可包括第一及第二特征形成为直接接触的实施方式；以及亦可包括可在第一及第二特征之间形成额外特征，以使得第一及第二特征可不直接接触的实施方式。另外，本揭露可能在各实例中重复组件符号及/或字母。重复为出于简易及清楚的目的，且本身不指示所论述的各种实施方式及/或配置之间关系。
另外，空间相对术语，诸如“在...之下”、“低于”、“下部”、“高于”、“上部”等，可在本文用以便于描述，以描述如在附图中图示的一个组件或特征相对另一组件或特征的关系。除图形中描绘的方向外，空间相对术语意图是包含在使用或操作中的装置的不同的方向。装置可为不同朝向(旋转90度或以其他的方向)及可因此相应地解释在本文中使用的空间相对的描述词。
本揭露亦可包含其他技术特征及制程。例如，可包含测试结构以帮助三维封装及三维集成电路装置的验证测试。测试结构可以包含，例如，在重分布层中或基板上形成的测试垫，此测试垫允许三维封装及三维集成电路的测试、使用探针及/或探针板、及类似物。上述验证测试可以对中间结构以及最终结构执行。另外，本文揭露的结构及方法可以结合测试方法使用，此测试方法结合已知良好晶粒的中间验证以增加良率与降低成本。
图1至图19为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图。参阅图1。粘胶层A1在载体C1上形成。载体C1可为空白玻璃载体、空白陶瓷载体、金属框或类似物。粘胶层A1可由粘胶组成，诸如紫外光(ultra-violet；UV)胶、光热转换(light-to-heat conversion；LTHC)胶或类似物，虽然可以使用其他类型的粘胶。缓冲层110可例如用旋转涂布制程、薄膜层压制程或沉积制程形成在粘胶层A1上方。缓冲层110为介电层，其可为聚合物层。聚合物层可以包括，例如聚酰亚胺、聚苯恶唑(PBO)、苯并环丁烯(BCB)、ajinomoto增设膜(ajinomoto buildup film；ABF)、阻焊(solder resist；SR)膜或类似物。在一些实施方式中，缓冲层110可为组合层，其结合缓冲层110与粘胶层A1于一个层中。缓冲层110可为大体上平坦的层，具有大体上均于的厚度，其中厚度可大于约2μm或可在0.5μm至约40μm的范围中。在一些实施方式中，缓冲层110的顶面及底面亦为大体上平坦的。
参阅图2。例如，使用旋转涂布制程或层压制程在缓冲层110上方形成介电层120。之后，介电层120经图案化以形成开口O1。开口O1可以布置在对应于随后形成的球栅阵列(BGA)的行及列的栅格图案中。介电层120可以使用微影制程图案化。在一些实施方式中，介电层120可以为聚合物层。聚合物层可以包括，例如聚酰亚胺、聚苯恶唑(PBO)、苯并环丁烯(BCB)、ajinomoto增设膜(ABF)、阻焊(SR)膜或类似物。
参阅图3。晶种层132在载体C1上方形成。晶种层132在载体C1上的缓冲层110及介电层120上方形成。晶种层132包括例如钛(Ti)、铜(Cu)或其组合，并且例如在一些实施方式中使用物理气相沉积(physical vapor deposition；PVD)或通过箔材料的层压而沉积。或者，晶种层132可以包括其他材料及尺寸，且可使用其他方法形成。之后，光阻P1涂布在晶种层132上方且随后被图案化。如此一来，开口O2在光阻P1中形成，且晶种层132的一些部分经由开口O2暴露。
参阅图4。导体134经由镀覆(其可为电镀或无电电镀)分别在光阻P1的开口O2中形成。导体134被电镀在晶种层132的暴露部分上。导体134可以包括金属或金属合金，此金属合金包括铝、铜、钨及/或其合金。在电镀导体134之后，去除光阻P1以暴露晶种层132的一些部分。
参阅图5。执行蚀刻操作以去除晶种层132的暴露部分，且蚀刻操作可以包括非等向性蚀刻。被导体134覆盖的晶种层132的部分仍然未蚀刻。在本文中，导体134及其下方晶种层132的剩余部分组合成为重分布线(redistribution lines；RDL)130。虽然晶种层132绘示为与导体134分开的层，但是当晶种层132由类似于或大体上相同于其上导体134的材料组成时，晶种层132可以与导体134融合而在两者间无可区分的界面。在替代实施方式中，在晶种层132与其上导体134之间存在可区分的界面。
参阅图6。介电层140在重分布线130上方形成。介电层140可以包括聚合物，诸如聚酰亚胺、苯并环丁烯(BCB)、聚苯恶唑(PBO)或类似物，其例如使用旋转涂布制程或层压制程沉积。或者，介电层140可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。介电层140使用微影制程图案化。例如，光阻(未绘示)可以在介电层140上方形成，以及光阻通过暴露至能量或光而图案化，此能量或光从其上具有预定图案的微影遮罩反射或通过。显影光阻，且使用灰化及/或蚀刻制程去除光阻的曝光(或未曝光，取决于光阻为正型还是负型)区域。光阻随后在蚀刻制程期间作为蚀刻遮罩。介电层140的暴露部分在蚀刻制程期间去除以形成开口O3，经由开口O3暴露重分布线130的一些部分。随后去除光阻。
参阅图7。晶种层152在载体C1上方形成。晶种层152在介电层140上方及在介电层140的开口O3(如图6所示)中形成。在一些实施方式中，晶种层152在介电层140及开口O3(如图6所示)上共形地形成。晶种层152包括例如钛(Ti)、铜(Cu)或其组合，且例如在一些实施方式中使用物理气相沉积(PVD)或通过箔材料的层压而沉积。或者，晶种层152可以包括其他材料且可使用其他方法形成。
在形成晶种层152之后，光阻P2涂布在晶种层152上方且随后被图案化。结果，开口O4在光阻P2中形成，晶种层152的一些部分经由开口O4暴露晶种层152。使用微影技术图案化光阻P2以定义出在后续步骤中形成的导体154的图案。导体154例如经由镀覆(其可为电镀或无电电镀)分别在光阻P2的开口O4中形成。导体154被电镀在晶种层152的暴露部分上。导体154可包括金属或金属合金，包括铝、铜、钨及/或其合金。
在电镀导体154之后，去除光阻P2，及暴露晶种层152的一些部分。可执行蚀刻步骤以去除晶种层152的暴露部分，并且蚀刻步骤可以包括非等向性蚀刻。另一方面，被导体154覆盖的晶种层152的部分仍然未蚀刻，结构如图8所示。导体154及晶种层152的剩余部分可共同地成为重分布线(RDL)150。虽然晶种层152绘示为与导体154分隔的层，但是当晶种层152由类似于或大体上相同于其上导体154的材料组成时，晶种层152可以与导体154融合而在两者间无可区分的界面。在替代实施方式中，在晶种层152与其上导体154之间存在可区分的界面。
参阅图9。介电层160在重分布线150上方形成，使得重分布线150嵌入介电层160中。介电层160可以包括聚合物，诸如聚酰亚胺、苯并环丁烯(BCB)、聚苯恶唑(PBO)或类似物，及例如使用旋转涂布制程或层压制程沉积。或者，介电层160可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。介电层160使用微影制程图案化。例如，光阻(未绘示)可以在介电层160上方形成，以及光阻通过暴露至能量或光而图案化，此能量或光从其上具有预定图案的微影遮罩反射或通过。显影光阻，且使用灰化及/或蚀刻制程去除光阻的曝光(或未曝光，取决于光阻为正型还是负型)区域。光阻随后在蚀刻制程期间作为蚀刻遮罩。介电层160的暴露部分在蚀刻制程期间经去除以形成开口O5，重分布线150的一些部分经由开口O5暴露。
重分布线的层数及介电层的数目并不限制本揭露的各种实施方式。例如，在形成图9的结构之后，图10中所示的另一层重分布线170及另一介电层180可经由图6至图9所示的步骤在重分布线150及介电层160上方形成。为了简化描述，形成重分布线170及介电层180的步骤不再重复赘述。
参阅图10。介电层180经图案化而形成开口O6以暴露重分布线170的一些部分。之后，毯覆晶种层192在介电层180及暴露的重分布线170上方形成，如图11所示。
参阅图12。光阻P3涂布在晶种层192上方且随后被图案化。如此一来，开口O7在光阻P3中形成，晶种层192的一些部分由开口O7暴露。后来，导体194经由镀覆方法分别在光阻P3的开口O7中形成，镀覆方法可为电镀或无电电镀。导体194被电镀在晶种层192的暴露部分上。在电镀导体194之后，去除光阻P3以暴露晶种层192的一些部分。
参阅图13。执行蚀刻操作以去除晶种层192的暴露部分，并且蚀刻操作可以包括非等向性蚀刻。另一方面，被导体194覆盖的晶种层192的部分仍然未被蚀刻。
缓冲层110、介电层120、重分布线130、介电层140、重分布线150、介电层160、重分布线170、介电层180、晶种层192及导体194可共同地作为重分布结构102。在一些实施方式中，缓冲层110、介电层120、140、160、180可作为重分布结构102的介电结构104。重分布线130、150、170、晶种层192及导体194可作为重分布结构102的布线结构106。
参阅图14。晶种层212例如经由PVD或金属箔层压在重分布结构102上形成。晶种层212可以包括铜、铜合金、铝、钛、钛合金或其组合。在一些实施方式中，晶种层212包括钛层及在钛层上方的铜层。在替代实施方式中，晶种层212为铜层。之后，光阻P4涂布在晶种层212上方且随后经图案化而暴露晶种层212的一些部分。如此一来，开口O8在光阻P4中形成，晶种层212的一些部分经由开口O8暴露。
参阅图15。导体214经由例如镀覆方法分别在光阻P4的开口O8中形成，镀覆方法可为电镀、无电电镀或金属膏印刷。导体214分别被电镀在开口O8下的晶种层212的暴露部分上。导体214可以包括铜、铝、钨、镍、焊料、银或其合金。导体214的俯视形状可为矩形、正方形、圆形或类似形状。在电镀导体214之后，去除光阻P4，且暴露晶种层212的一些部分。
参阅图16。执行蚀刻步骤以去除未被导体214覆盖的晶种层212的暴露部分，其中蚀刻步骤可包括非等向性蚀刻。另一方面，由导体214覆盖的晶种层212的部分仍然未被蚀刻。在本文中，导体214及其下晶种层212的剩余部分组合地作为集成扇出(throughintegrated fan-out；InFO)通孔(TIV)210，其亦称为通孔。虽然晶种层212绘示为与导体214分隔的层，但是当晶种层212由类似于或大体上相同于其上导体214的材料组成时，晶种层212可以与导体214融合而在两者之间没有可区分的界面。在替代实施方式中，在晶种层212与其上导体214之间存在可区分的界面。
在形成集成扇出通孔210之后，暴露未被导体214覆盖的一些导体194，以便后续放置的半导体装置220(见图17)可经由预先暴露的导体194电连接至重分布结构102。在放置半导体装置220之前形成重分布结构102的方法在本文可称作“RDL为先”(RDL-first)制程。
参阅图17。使用拾取及放置的机器、人工等等将半导体装置220设置在或放置在重分布结构102上。半导体装置220的数目并不限制本揭露的各种实施方式。半导体装置220的厚度可为相同的或不同的，且本揭露的各种实施方式并不限于此。半导体装置220可电连接至未被集成扇出通孔210覆盖的重分布结构102的一些导体194。例如，半导体装置220的底部上的接合垫224(诸如铜垫)电连接至导体194。换言之，使用“覆晶”(flip chip)方法将半导体装置220设置在重分布结构102上；即，在半导体装置220的面上的接合垫224经“翻转”，所以它们“面朝下”，且接合垫224使用导电材料连接至导体194。例如，接合垫224可经由连接件226电连接及机械连接至重分布结构102的暴露的导体194。在一些实施方式中，导体194形成为垫，连接件226可以为焊料凸块或焊球，这些焊料凸块或焊球实体接触导体194而形成垫上焊料(solder-on-pad；SOP)连接物。在一些其他实施方式中，导体194可以形成为走线(trace)，及连接件226可以包括非焊料金属凸块。非焊料金属凸块可以包括铜柱且可以包括一或多个包括镍、金、钯或其他适宜材料的层。这些非焊料金属凸块(例如，连接件226的代替类型)及导体194可以通过焊料接合以形成走线上凸块(bump-on-trace；BOT)连接物。通过连接件226形成的SOP连接物或BOT连接物，半导体装置220可以与重分布结构102电连接。
如图17所示，根据一些实施方式，在“RDL为先”制程形成的结构中，底部填充层230可选择性地形成在半导体装置220与重分布结构102之间，及连接件226之间。底部填充层230可以使用毛细底部填充(capillary underfill；CUF)方法作为液体施配(dispense)。树脂或环氧树脂液体在半导体装置220下方流动，且填充在半导体装置220与重分布结构102之间的空间。室温、UV或热固化可以用以固化底部填充层230。底部填充层230可至少对其上的半导体装置220及其下的重分布结构102提供机械强度及应力消除。在一些实施方式中，底部填充层230与后续用来模制半导体装置220形成的模制化合物250(见图22)相同。即，在半导体装置220与重分布结构102之间的空间可以由后续形成的模制化合物250填充。
在一些实施方式中，半导体装置220为未封装半导体装置，诸如逻辑装置晶粒(例如，加速处理单元(accelerated processing unit；APU)、图形处理单元(graphicsprocessing unit；GPU)、压电多层促动器(piezoelectric multilayer actuator；PMA)、压电促动器(piezoelectric actuator；PA)等等)，记忆体装置晶粒(例如，低功率双倍数据速率(low power double-data-rate；LPDDR)、快闪(flash)、高频宽记忆体(high bandwidthmemory；HBM)等等)，或感测装置晶粒(例如，接触影像感测器(contact image sensor；CIS)、微电机系统(micro-electro-mechanical system；MEMS)等等)。在一些实施方式中，半导体装置220设计来用于移动应用且可为中央计算单元(central computing unit；CPU)晶粒、功率管理集成电路(power management integrated circuit；PMIC)晶粒、收发器(transceiver；TRX)晶粒或类似物。半导体装置220包括半导体基板222(例如硅基板)，以及自半导体装置220的底部介电层(未绘示)凸出或齐平的接合垫224。
参阅图18。重分布结构102从载体C1脱离。粘胶层A1亦自重分布结构102的缓冲层110清除。去除粘胶层A1的结果会暴露重分布结构102的缓冲层110。在一些实施方式中，图18所示的结构粘附至切割胶带(未绘示)。在一些实施方式中，层压薄膜(未绘示)可放置在暴露的缓冲层110上，其中层压薄膜可以包括SR、ABF、背面涂层胶带或类似物。在替代实施方式中，没有层压膜放置在缓冲层110上方。
参阅图19。图案化缓冲层110以形成开口O9，借此暴露重分布线130。在一些实施方式中，执行激光钻孔制程以形成开口O9以去除缓冲层110的部分及晶种层132的部分。即，开口O9可为激光钻孔开口。激光钻孔制程可以产生开口O9的侧壁的锯齿轮廓或粗糙轮廓。在一些其他实施方式中，光微影制程亦可用以形成开口O9以去除缓冲层110的部分，随后执行蚀刻步骤以去除晶种层132的暴露部分，其中蚀刻步骤可包括非等向性蚀刻。如此一来，导体134的部分经由开口O9而暴露。在一些实施方式中，开口O9布置在行及列的栅格图案中，以便后续在开口O9中形成的导电凸块(例如，导电球体240)能形成BGA。
导电球体240在重分布线130的暴露部分上形成。换言之，导电球体240电连接至重分布线130。如此一来，导电球体240可经由重分布线130电偶接至重分布线150。导电球体240的形成可以包括在缓冲层110的开口O9中放置焊球，且随后将焊球回焊。因此，导电球体240部分嵌入式地保留在缓冲层110的开口O9中。在形成导电球体240之后，执行切割制程沿线L-L切割介电结构104，使得至少一个半导体组件100能形成。在一些实施方式中，此组件粘附至切割胶带，此切割胶带可在切割制程之后去除。
在形成导电球体240之后，可对重分布结构102、半导体装置220及集成扇出通孔210执行电性测试，其可有助于在模制半导体装置220及集成扇出通孔210之前解决一些问题(例如，缺陷/可靠度)。换言之，根据本揭露的一些实施方式的RDL为先的制程允许经由如导电球体240对中间封装执行电性测试。以这种方法，中间封装，即半导体组件100，当其通过电性测试时可确定为已知良好的封装。另外，半导体组件100对热敏感的半导体装置220是有益的，因为重分布结构102是在设置半导体装置220之前形成，而重分布结构102是被施以高温制程的，因此能避免半导体装置220损坏。
图20为根据本揭露的一些实施方式的半导体组件100a的剖面图。半导体组件100a可以通过如上所述的半导体组件100的制造步骤而形成。半导体组件100a具有重分布线130a及比半导体组件100的导电球体240数量少的导电球体240a。重分布线130a位于介电层120a中且电连接至半导体装置220a及集成扇出通孔210a，且导电球体240a电连接至重分布线130a。在一些实施方式中，半导体组件100a包括半导体装置220a，其与图19的半导体装置220相同。在替代实施方式中，图20的半导体装置220a不同于图19的半导体装置220，本揭露的各种实施方式并不限于此。
在形成图19的半导体组件100及图20的至少一个半导体组件100a之后，半导体组件100a经由半导体组件100a的导电球体240a及半导体组件100的集成扇出通孔210接合至半导体组件100。导电球体240a分别与集成扇出通孔210大体上对齐。如此一来，半导体组件100a可堆叠在半导体组件100上。
在一些实施方式中，半导体组件100a的集成扇出通孔210a分别与导电球体240a大体上对齐。这样的配置，至少两个半导体组件100a可经由上半导体组件100a的导电球体240a及下半导体组件100a的集成扇出通孔210a堆叠。
图21至图22为在图19的步骤后的制造封装结构的中间阶段的剖面图。参阅图21。在形成半导体组件100及多个半导体组件100a之后，半导体组件100a其中之一经由半导体组件100a底侧的导电球体240a及半导体组件100顶侧的集成扇出通孔210堆叠在半导体组件100上。如此一来，半导体组件100a的重分布线130a接合至半导体组件100的重分布线170。换言之，包括集成扇出通孔210及其上导电球体240a的导电件215电连接半导体组件100a的重分布线130a与半导体组件100的重分布线170。此外，包括集成扇出通孔210a及其上导电球体240a的导电件215a经由重分布线150a电连接重分布线130a。之后，其他半导体组件100a经由导电球体240a及集成扇出通孔210a依序堆叠在第一个堆叠的半导体组件100a上。在一些实施方式中，半导体组件100a为相同的。在其他实施方式中，半导体组件100a为不同的。例如，半导体组件100a可以具有不同种类的半导体装置220a、不同层数的重分布线150a、及/或不同布局的重分布线150a。
在半导体组件100a接合至半导体组件100后，半导体封装300接合至上半导体组件100a。半导体封装300在半导体组件100a及半导体组件100的堆叠组件上方。在一些实施方式中，半导体封装300包括基板320，及导电凸块或导电球体330。导电凸块330自基板320凸出。此外，半导体封装300的导电凸块330分别与上半导体组件100a的集成扇出通孔210a大体上对齐。在这种配置中，半导体封装300可经由半导体封装300底侧的导电凸块330及上半导体组件100a顶侧的集成扇出通孔210a接合至上半导体组件100a，使得半导体封装300经由导电凸块330电连接至其下的集成扇出通孔210a。然而，前述步骤的顺序并不用以限制本揭露的各种实施方式。例如，接合半导体组件100a以形成堆叠结构，随后半导体封装300接合至堆叠结构的顶侧。之后，堆叠结构的下侧接合至半导体组件100，使得图21的结构仍可获得。在一些实施方式中，半导体封装300可以为记忆体装置，诸如静态随机存取记忆体(static random access memory；SRAM)或动态随机存取记忆体(dynamic random accessmemory；DRAM)装置。半导体封装300可以包括在其内的多个堆叠记忆体晶粒。此外，半导体封装300的其他类型也可位于半导体组件100a上，本揭露的各种实施方式并不限于此。
参阅图22。在形成如图21图示的堆叠结构后，模制材料(或模制化合物)250模制半导体装置220、半导体装置220a、集成扇出通孔210、集成扇出通孔210a及导电球体240a、导电球体330。半导体封装300在模制材料250上方。换言之，模制材料250在半导体组件100与其上半导体组件100a之间、两个相邻半导体组件100a之间、及半导体封装300与其下半导体组件100a之间形成。此外，模制材料250围绕半导体装置220、半导体装置220a、集成扇出通孔210、集成扇出通孔210a及导电球体240a、导电球体330。模制材料250填充半导体装置220与集成扇出通孔210之间的缝隙及填充半导体装置220a与集成扇出通孔210a之间的缝隙。另外，模制材料250具有在半导体装置220与介电层120a(或缓冲层110a)之间的部分。集成扇出通孔210、导电球体240a、及集成扇出通孔210a与模制材料250接触。模制材料250可与介电层180、介电层160a、缓冲层110a及基板320接触。在形成模制材料250之后，半导体组件100及其上模制材料250形成集成扇出型封装410，且半导体组件100a及其上模制材料250形成集成扇出型封装410a。因此，集成扇出型封装410、集成扇出型封装410a及半导体封装300的组合形成封装结构400，所得的结构如图22所示。
在一些实施方式中，模制材料250包括聚合物基材料。「聚合物」可表示热固性聚合物、热塑性聚合物、或其任何混合物。聚合物基材料可包括例如塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有填充剂(包括纤维、粘土、陶瓷、无机颗粒)的聚合物化合物、或其任意组合。
因为单一模制步骤可让模制材料250能填充在半导体组件100与其上半导体组件100a之间、两个相邻半导体组件100a之间、及在半导体封装300与其下半导体组件100a之间的缝隙，所以可以减少制造封装结构400的周期时间(cycle time)及翘曲。
此外，当封装结构400设置在印刷电路板(printed circuit board；PCB)上时，封装结构400占据与半导体组件100、半导体组件100a或半导体封装300的面积相同的印刷电路板面积，因此印刷电路板被半导体组件100、半导体组件100a及半导体封装300占据的面积得以缩小。
由于封装结构400为三维层叠封装(PoP)结构，因此集成扇出型封装410、集成扇出型封装410a及半导体封装300之间的短长度及高频宽通讯可提升设有封装结构400的系统的效能。此外，封装结构400可以包括各种半导体装置(例如，220及220a)及半导体封装310，以便由设计者弹性使用。
在一些实施方式中，集成扇出型封装410其内具有更多的半导体装置220，集成扇出型封装410a的至少一个其内具有更多的半导体装置220a。这样的配置结果，集成扇出型封装410a的层数可以减少，但封装结构400仍可具有相同的功能。此外，可降低封装结构400的总高度。
图23为根据本揭露的一些实施方式的封装结构400a的剖面图。封装结构400a包括集成扇出型封装410、集成扇出型封装410a及在其上的集成扇出型封装410b。集成扇出型封装410b及集成扇出型封装410a之间的差异为在集成扇出型封装410b中没有集成扇出通孔210a及其下导体194a。集成扇出型封装410b的导电球体240b与其下集成扇出型封装410a的集成扇出通孔210a大体上对齐，因此集成扇出型封装410b的导电球体240b可分别接合至其下集成扇出型封装410a的集成扇出通孔210a。
图24至图32为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图。参阅图24。包括介电结构104及布线结构106a的重分布结构102a在载体C1上形成。重分布结构102a的形成类似上述的图1至图13所描述的重分布结构102的形成，不再重复赘述。图24的布线结构106a的图案不同于图13的布线结构106的图案，但本揭露的各种实施方式并不限于此。
参阅图25。导电件265包括被动嵌入件260及导电凸块266。在一些实施方式中，被动嵌入件260为硅通孔(through silicon via；TSV)装置。半导体装置220及硅通孔装置260使用拾取及放置机器、人工或其他适宜方法设置在或放置在重分布结构102a上。硅通孔装置260在介电层180上方，且硅通孔268在硅通孔装置260中且电连接至接触垫264。导电凸块266在硅通孔装置260与重分布线170之间且电连接硅通孔装置260与重分布线170。半导体装置220的数目及硅通孔装置260的数目不限制本揭露的各种实施方式。半导体装置220及硅通孔装置260可电连接至重分布结构102a的导体194。半导体装置220的接合垫224及硅通孔装置260的接触垫264使用导电材料连接至导体194。例如，接合垫224可经由连接件226电连接及机械连接至一些导体194，连接件226例如导电凸块，且接触垫264可经由导电凸块266电连接及机械连接至其余导体194。
如在图25的组件所示，根据一些实施方式，在由「RDL为先」制程形成的结构中，底部填充层230可选择性地在半导体装置220与重分布结构102a之间及连接件226之间形成，且可选择性地在硅通孔装置260与重分布结构102a之间及导电球体266之间形成。
在一些实施方式中，硅通孔装置260可包括例如，硅通孔(TSV)268及整合式被动元件(IPD，未绘示)。硅通孔装置260允许高密度的结构于在其内形成，诸如硅通孔268及/或整合式被动元件。在一些实施方式中，硅通孔装置260包含基板261，基板261包含半导体材料，诸如硅或类似物。基板261中的孔可充满导体以形成硅通孔268及整合式被动元件，诸如沟槽电容器。硅通孔装置260包含互连层262，其包括一或多层其内形成导电件的介电材料。在一些实施方式中，互连层262中的介电材料层由感光材料形成，诸如聚苯恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)或类似物。在替代实施方式中，互连层262中的介电材料层可由诸如氮化硅的氮化物、诸如氮化硅的氧化物形成、磷硅酸盐玻璃(PSG)、硅酸硼玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)或类似物形成。在一些替代实施方式中，互连层262可以包含嵌入件或封装基板，诸如硅嵌入件、有机基板、层压基板(例如，1-2-1层压基板)或类似物。互连层262在相对侧之间提供电连接且可作为布线结构。外部接触垫264组例如使用导电凸块266提供外部电连接。
如图所示，相邻硅通孔268的间距(pitch)比邻近集成扇出通孔(例如，如前所述的集成扇出通孔210或集成扇出通孔210a)的间距短，因此若硅通孔268与凸块接合，则具有较短间距的硅通孔268允许高密度凸块。
参阅图26。模制材料(或模制化合物)250a模制在重分布结构102a、半导体装置220及硅通孔装置260上。模制材料250a填充在半导体装置220与硅通孔装置260之间的缝隙中，且可与重分布结构102a接触，例如接触重分布结构102a的介电层180。模制材料250a的顶面高于半导体装置220及硅通孔装置260的顶面。
在一些实施方式中，模制材料250a包括聚合物基材料。「聚合物」可表示热固性聚合物、热塑性聚合物、或其任何混合物。聚合物基材料可包括例如塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有填充剂(包括纤维、粘土、陶瓷、无机颗粒)的聚合物化合物、或其任意组合。
参阅图27。接下来，执行诸如研磨的平坦化制程以使模制材料250a变薄，直到暴露半导体装置220及硅通孔装置260的顶面。模制材料250a围绕半导体装置220及硅通孔装置260。在一些实施方式中，在研磨模制材料250a后亦暴露在硅通孔装置260顶面的硅通孔268。所得的结构如图27所示，其中模制材料250a与半导体装置220及硅通孔装置260的侧壁接触。由于研磨，半导体装置220的顶面与硅通孔装置260的顶面大体上齐平(共面)，且与模制材料250a的顶面大体上齐平(共面)。研磨的结果，可能会产生诸如金属颗粒的导电残留物，并留在图27的结构的顶面上。因此，在研磨之后，清洗制程(例如经由湿式蚀刻)可以执行以去除导电残留物。
参阅图28。接下来，模制封装510从载体C1脱离。粘胶层A1亦自模制封装510清除。去除粘胶层A1的结果，可暴露缓冲层110。参阅图28，具有半导体装置220、模制材料250a及在其上的硅通孔装置260的模制封装510进一步粘附至切割胶带DT，其中模制材料250a朝向切割胶带DT且可接触切割胶带DT。在一些实施方式中，层压薄膜(未绘示)置于暴露的缓冲层110上，其中层压薄膜可包括ajinomoto增设膜(ABF)、阻焊(SR)膜、背面涂层胶带或类似物。在替代实施方式中，没有层压薄膜置于缓冲层110上方。
开口O10在缓冲层110中形成。在形成缓冲层110的开口O10之后，经由开口O10暴露重分布线130的晶种层132的部分。在一些实施方式中，执行激光钻孔制程以形成开口O10。在一些其他实施方式中，光微影制程亦可用以形成开口O10。之后，执行蚀刻步骤以去除晶种层132的暴露部分，其中蚀刻步骤可以包括非等向性蚀刻。如此一来，在晶种层132下的导体134的部分由开口O10暴露，以便接受后续形成的导电球体240(见图29)。在一些实施方式中，开口O10布置在行及列的栅格图案中，使后续在开口O10中形成的导电球体240可形成球栅阵列(BGA)。
参阅图29。诸如导电球体240的导电凸块在导体134的暴露部分上形成。换言之，导电球体240分别与导体134接触，使得导电球体240可电连接至导体134。如此一来，导电球体240可经由导体134电偶接至布线结构106a。导电球体240的形成可以包括在开口O10中放置焊球，且随后将焊球回焊。
在形成导电球体240之后，执行切割制程以沿线L1切割介电结构104及模制材料250a，且也可去除切割胶带DT，以形成多个晶片尺寸模制封装510。
在替代实施方式中，在脱离载体C1及清除粘胶层A1之后，执行一或多个蚀刻操作以去除缓冲层110及晶种层132的水平部分直到暴露导体134。所得的结构如图30所示，其中重分布线130的顶面被暴露且与剩余介电层120的顶面大体上齐平。在蚀刻制程之后，导电球体240在暴露的重分布线130上形成，所得的结构如图31所示。
在形成导电球体240之后，执行切割制程以沿线L1切割介电结构104及模制材料250a，且也可去除切割胶带DT，以形成多个晶片尺寸模制封装510，所得的结构如图32所示。在以下叙述中，图31的重分布线130、导电球体240及介电层120形成于图32至图35的封装中。在一些替换性实施方式中，图29的重分布线130、导电球体240、缓冲层110及介电层120可形成在图32至图35的封装中，本揭露的各种实施方式不限于此。
图33为根据本揭露的一些实施方式的模制封装510a的剖面图。模制封装510a可以通过模制封装510的前述制造步骤而形成。与模制封装510相较，模制封装510a具有在其内的重分布线130a，且具有分别与模制封装510其上硅通孔装置260大体上对齐的导电球体240a。在一些实施方式中，模制封装510a包括分别与图32的半导体装置220及硅通孔装置260相同的半导体装置220a及硅通孔装置260a。在替代实施方式中，半导体装置220a及硅通孔装置260a分别不同于图32的半导体装置220及硅通孔装置260，本揭露的各种实施方式不限于此。
图34为根据本揭露的一些实施方式的模制封装510b的剖面图。在一些实施方式中，图29的硅通孔装置260a为可选择的。模制封装510b在模制材料250a中没有硅通孔装置，但在介电层160a上具有更多的模制材料250a以补充空缺。
图35为根据本揭露的一些实施方式的封装结构500的剖面图。在形成图32的模制封装510，图33的至少一个模制封装510a及图34的模制封装510b后，模制封装510b经由其导电球体240a及下方模制封装510a的硅通孔装置260a接合至模制封装510a，且模制封装510a经由其导电球体240a及模制封装510的硅通孔装置260接合至模制封装510。导电球体240a在模制封装510的硅通孔装置260与模制封装510a的重分布线130a之间，且电连接模制封装510的硅通孔装置260与模制封装510a的重分布线130a。因此，模制封装510b的导电球体240a电连接至模制封装510a的硅通孔装置260a的硅通孔268，且模制封装510a的导电球体240a电连接至模制封装510的硅通孔装置260的硅通孔268。换言之，包括硅通孔装置260、导电球体266及导电球体240a的导电件265电连接模制封装510a的重分布线130a与模制封装510的重分布线170。此外，包括硅通孔装置260a、导电球体266a及导电球体240a的导电件265a经由重分布线150a电连接至重分布线130a。这样的配置，模制封装510b在模制封装510a上堆叠，且模制封装510a在模制封装510上堆叠，进而形成封装结构500。
在一些实施方式中，模制封装510a的硅通孔装置260a与模制封装510a的导电球体240a大体上对齐，因此至少两个模制封装510a可经由上模制封装510a的导电球体240a及下模制封装510a的硅通孔装置260a而堆叠。例如，封装结构500包括三个模制封装510a，但本揭露的各种实施方式不限于此。
在一些实施方式中，底部填充UF选择性地设置在模制封装510b与其下模制封装510a之间，在两个相邻模制封装510a之间、及在模制封装510a与其下模制封装510之间，使得模制封装510b稳固地置于模制封装510a上，且模制封装510a稳固地置于另一模制封装510a或模制封装510上。
图36至图51为根据本揭露的一些实施方式的制造封装结构的中间阶段的剖面图。参阅图36。粘胶层A3在载体C3上形成。载体C3可为空白玻璃载体、空白陶瓷载体或类似物。粘胶层A3可由粘胶组成，诸如紫外线(UV)胶、光热转换(LTHC)胶或类似物，虽也可使用其他类型的粘胶。缓冲层610在粘胶层A3上方形成。缓冲层610为介电层，其可为聚合物层。聚合物层可以包括，例如聚酰亚胺、聚苯恶唑(PBO)、苯并环丁烯(BCB)、ajinomoto增设膜(ABF)、阻焊(SR)膜或类似物。
参阅图37。晶种层623例如经由物理气相沉积(PVD)或金属箔层压而在缓冲层610上形成。晶种层623可以包括铜、铜合金、铝、钛、钛合金或其组合。在一些实施方式中，晶种层623包括钛层及在钛层上方的铜层。在替代实施方式中，晶种层623为铜层。
参阅图38。光阻P11涂布在晶种层623上方且随后被图案化。如此一来，开口O11在光阻P11中形成，经由开口O11暴露晶种层623的一些部分。
参阅图39。导体625经由镀覆(其可为电镀或无电电镀)在光阻P11中形成。导体625被电镀在晶种层623的暴露部分上。导体625可以包括铜、铝、钨、镍、焊料或其合金。导体625的高度由后续放置的半导体装置630(见图42)决定，其中在本揭露的一些实施方式中导体625的高度大于半导体装置630的厚度。在镀覆导体625后，去除光阻P11，且所得的结构如图40所示。在去除光阻P11后，暴露晶种层623的一些部分。
参阅图41。可执行蚀刻步骤以去除晶种层623的暴露部分，其中蚀刻步骤可以包括非等向性蚀刻。另一方面，由导体625覆盖的晶种层623的一些部分仍未被蚀刻。在本文中，导体625及其下晶种层623的剩余部分组合地作为导电件620，为集成扇出(InFO)通孔(TIV)，其亦称为通孔。虽然晶种层623绘示为与导体625分隔的层，但是当晶种层623由类似于或大体上相同于其上导体625的材料组成时，晶种层623可以与导体625融合而在两者之间没有可区分的界面。在替代实施方式中，在晶种层623与其上导体625之间存在可区分的界面。
图42绘示在缓冲层610上方放置半导体装置630。半导体装置630可经由粘胶层631粘附至缓冲层610。在一些实施方式中，半导体装置630为非封装的半导体装置，即装置晶粒。例如，半导体装置630可为其内包括逻辑晶体管的逻辑装置晶粒。在一些实施方式中，半导体装置630经设计以用于移动应用，且可以为中央计算单元(CPU)晶粒、功率管理集成电路(PMIC)晶粒、收发器(TRX)晶粒或类似物。每个半导体装置630包括接触粘胶层631的半导体基板632(例如，硅基板)，其中半导体基板632的背表面接触粘胶层631。
在一些实施方式中，导电柱636(诸如铜柱)形成为半导体装置630的顶部，且电偶接至诸如半导体装置630中的晶体管(未绘示)的装置。在一些实施方式中，介电层634在对应的半导体装置630的顶面上形成，其中导电柱636具有至少在介电层634中的下部分。在一些实施方式中导电柱636的顶面与介电层634的顶面大体上齐平。或者，未形成介电层，且导电柱636自对应的半导体装置630的顶部介电层凸出(未绘示)。
参阅图43。模制材料635在半导体装置630及集成扇出通孔620上形成。模制材料635填充在半导体装置630与集成扇出通孔620之间的缝隙，且可以接触缓冲层610。此外，当导电柱636凸出金属柱(未绘示此配置)时，模制材料635填充进导电柱636之间的缝隙中。模制材料635的顶面高于导电柱636及集成扇出通孔620的顶端。
在一些实施方式中，模制材料635包括聚合物基材料。“聚合物”可表示热固性聚合物、热塑性聚合物、或其任意混合物。聚合物基材料可包括例如塑性材料、环氧树脂、聚酰亚胺、聚对苯二甲酸乙二酯(PET)、聚氯乙烯(PVC)、聚甲基丙烯酸甲酯(PMMA)、掺杂有填充剂(包括纤维、粘土、陶瓷、无机颗粒)的聚合物化合物、或其任意组合。
接下来，执行研磨步骤以使模制材料635变薄，直到暴露导电柱636及集成扇出通孔620。所得的结构如图44所示，其中模制材料635接触半导体装置630及集成扇出通孔620的侧壁。模制材料635围绕半导体装置630及集成扇出通孔620。由于研磨，集成扇出通孔620的顶端与导电柱636的顶端大体上齐平(共面)，且与模制材料635的顶面大体上齐平(共面)。经由研磨的结果，可能生成诸如金属颗粒的导电残留物，且留在图44的结构的顶面上。因此，在研磨之后，清洗制程(例如经由湿式蚀刻)可以执行以去除导电残留物。
参阅图45。介电层640在集成扇出通孔620、模制材料635及半导体装置630上方形成。介电层640可以包括聚合物，诸如聚酰亚胺、苯并环丁烯(BCB)、聚苯恶唑(PBO)或类似物，其例如使用旋转涂布制程或层压制程沉积。或者，介电层640可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。介电层640使用微影制程图案化。例如，光阻(未绘示)可以在介电层640上方形成，以及光阻通过暴露至能量或光而图案化，此能量或光从其上具有预定图案的微影遮罩反射或通过。显影光阻，且使用灰化及/或蚀刻制程去除光阻的曝光(或未曝光，取决于光阻为正型还是负型)区域。光阻随后在蚀刻制程期间作为蚀刻遮罩。介电层640的暴露部分在蚀刻制程期间去除以形成开口O12，经由开口O12暴露集成扇出通孔620及导电柱636。接着，去除光阻。
参阅图46。晶种层652在介电层640上方及介电层640的开口O12中形成。在一些实施方式中，晶种层652在介电层640上及开口O12中共形地形成。晶种层652包括诸如钛(Ti)、铜(Cu)或其组合的约0.3μm的材料，其例如在一些实施方式中使用物理气相沉积(PVD)或通过箔材料的层压而沉积。或者，晶种层652可以包括其他材料及尺寸且可使用其他方法形成。
在形成晶种层652之后，光阻P12涂布在晶种层652上方且随后被图案化。因此，开口O13在光阻P12中形成，经由开口O13暴露晶种层652的一些部分。使用微影图案化光阻P12以进一步定义后续步骤中形成的导体654的图案。导体654例如经由镀覆(其可为电镀或无电电镀)分别在光阻P12的开口O13中形成。导体654被镀覆在晶种层652的暴露部分上。导体654可包括金属或金属合金，此金属合金包括铝、铜、钨及/或其合金。
在镀覆导体654之后，去除光阻P12，且暴露晶种层652的一些部分。可执行蚀刻步骤以去除晶种层652的暴露部分，且蚀刻步骤可以包括非等向性蚀刻。另一方面，由导体654覆盖的晶种层652的一些部分仍未被蚀刻，所得的结构如图47所示。导体654及晶种层652的剩余部分可共同地作为重分布线(RDL)650。虽然晶种层652绘示为与导体654分隔的层，但是当晶种层652由类似于或大体上相同于其上导体654的材料组成时，晶种层652可以与导体654融合而在两者之间大体上没有可区分的界面。在替代实施方式中，在晶种层652与其上导体654之间存在可区分的界面。
参阅图48。介电层640a在重分布线650及介电层640上方形成，使得重分布线650嵌入介电层640a中。介电层640a可以包括聚合物，诸如聚酰亚胺、苯并环丁烯(BCB)、聚苯恶唑(PBO)或类似物，其例如使用旋转涂布制程或层压制程沉积。或者，介电层640a可以包括非有机介电材料，诸如氧化硅、氮化硅、碳化硅、氮氧化硅或类似物。介电层640a使用微影制程图案化。例如，光阻(未绘示)可以在介电层640a上方形成，且光阻通过暴露至能量或光而图案化，此能量或光从其上具有预定图案的微影遮罩反射或通过。显影光阻，且使用灰化及/或蚀刻制程去除光阻的曝光(或未曝光，取决于光阻为正型还是负型)区域。光阻随后在蚀刻制程期间作为蚀刻遮罩。介电层640a的暴露部分在蚀刻制程期间去除以形成开口O14，经由开口O14暴露重分布线650的一些部分。
重分布线650的层数及介电层的数目并不限制本揭露的各种实施方式。例如，在形成图48的结构后，如图49绘示的重分布线650a、重分布线650b的层及介电层640b、介电层640c可经由图45至图48的前述步骤在重分布线650及介电层640a上方形成。为了简化描述，将不重复赘述形成重分布线650a、重分布线650b及介电层640b、介电层640c的步骤。此外，图49的接触垫660的形成类似于图3至图5的步骤。
参阅图49。在介电层640c经图案化以形成开口之后，晶种层662在介电层640c及开口中的重分布线650b的暴露部分上方形成，随后光阻涂布在晶种层662上方且经图案化以形成开口。接下来，导体664经由镀覆分别在光阻的开口中形成，使得导体664被镀覆在晶种层662的暴露部分上。在电镀导体664后，去除光阻以暴露晶种层662的一些部分，随后执行蚀刻操作以去除晶种层662的暴露部分。如此一来，导体664及其下晶种层662的剩余部分组合地作为图49的接触垫660。
虽然晶种层662绘示为与导体664分隔的层，但当晶种层662由类似于或大体上相同于其上导体664的材料组成时，晶种层662可以与导体664融合而在两者之间大体上没有可区分的界面。在替代实施方式中，在晶种层662与其上导体664之间存在可区分的界面。
参阅图50。诸如导电球体670的导电凸块在接触垫660上形成。换言之，导电球体670分别与接触垫660接触，使导电球体670可电连接至接触垫660。如此一来，导电球体670经由接触垫660可电偶接至重分布线650、重分布线650a、重分布线650b。在形成导电球体670之后，载体C3及粘胶层A3自缓冲层610去除。
参阅图51。载体C3脱离及粘胶层A3去除之果，在半导体装置630及模制材料635上方的缓冲层610被暴露。随后缓冲层610经图案化以形成开口O15，借此暴露集成扇出通孔620。在一些实施方式中，执行激光钻孔制程以形成开口O15。在一些其他实施方式中，光微影制程亦可用以形成开口O15及去除缓冲层610的部分。在一些实施方式中，图50的结构可在与载体C3脱离后粘附至切割胶带(未绘示)。接下来，执行切割制程以沿线L2切割缓冲层610、模制材料635及介电层640与介电层640a～640c，使得多个晶片尺寸集成扇出型封装600可被形成，所得的结构如图52所示。
图53为根据本揭露的一些实施方式的集成扇出型封装600a的剖面图。集成扇出型封装600a可以通过图52的集成扇出型封装600的前述制造步骤而形成。相较于集成扇出型封装600，集成扇出型封装600a具有更少的导电球体670a。在一些实施方式中，集成扇出型封装600a包括与图52的半导体装置630相同的半导体装置630a。在替代实施方式中，图53的半导体装置630a不同于图52的半导体装置630，本揭露的各种实施方式并不限于此。
图54为根据本揭露的一些实施方式的封装结构700的剖面图。在形成图52的集成扇出型封装600及图53的至少一个集成扇出型封装600a之后，集成扇出型封装600a经由集成扇出型封装600a的导电球体670a接合至集成扇出型封装600。导电球体670a在集成扇出型封装600a的重分布线650b与集成扇出型封装600的集成扇出通孔620之间，且无模制材料635覆盖。集成扇出型封装600a的导电球体670a分别与集成扇出型封装600的集成扇出通孔620大体上对齐，而这些集成扇出型封装600的集成扇出通孔620分别经由开口O15暴露(查看图51)。如此一来，集成扇出型封装600a可在集成扇出型封装600上堆叠。在一些实施方式中，在集成扇出型封装600a中，集成扇出通孔620a分别与导电球体670a大体上对齐。这样的配置，至少两个集成扇出型封装600a可经由上方集成扇出型封装600a的导电球体670a及下方集成扇出型封装600a的暴露的集成扇出通孔620a而堆叠。在一些实施方式中，底部填充物可设置在相邻集成扇出型封装之间且围绕导电球体670a。
在集成扇出型封装600a粘合至集成扇出型封装600后，半导体封装300粘合至上集成扇出型封装600a。在一些实施方式中，半导体封装300包括缓冲层320及导电球体330。导电球体330自缓冲层320凸出。另外，半导体封装300的导电球体330分别与上方集成扇出型封装600a的集成扇出通孔620a大体上对齐。在这种配置中，半导体封装300可经由半导体封装300底侧的导电球体330及上集成扇出型封装600a顶侧的集成扇出通孔620a接合至上集成扇出型封装600a。然而，本揭露的各种实施方式并不限于前述步骤的顺序。例如，接合集成扇出型封装600a以形成堆叠结构，随后半导体封装300接合至堆叠结构的顶侧。之后，堆叠结构的下侧接合至集成扇出型封装600，也可得到图54的封装结构700。在一些实施方式中，半导体封装300可以为记忆体装置，诸如静态随机存取记忆体(SRAM)或动态随机存取记忆体(DRAM)装置。半导体封装300可以包括在其内的多个堆叠记忆体晶粒。此外，半导体封装300的其他类型也可在集成扇出型封装600a上，且本揭露的各种实施方式并不限于此。
在前述封装结构中，由于封装结构为三维层叠封装(PoP)结构，集成扇出型封装及半导体封装之间的短长度及高频宽通讯可提升设有封装结构的系统的效能。此外，封装结构可以包括各种半导体装置及半导体封装，以便由设计者弹性使用。
根据一些实施方式，封装结构包括第一介电层、第一半导体装置、第一重分布线、第二介电层、第二半导体装置、第二重分布线、导电凸块、第一导电件及第一模制材料。第一半导体装置在第一介电层上方。第一重分布线在第一介电层中且电连接至第一半导体装置。第二介电层在第一半导体装置上方。第二半导体装置在第二介电层上方。第二重分布线在第二介电层中且电连接至第二半导体装置。第一导电件电连接第一重分布线与第二重分布线。第一模制材料模制第一半导体装置及第一导电件。
在一些实施方式中，第一导电件包括电连接至第二重分布线的导电凸块。
在一些实施方式中，第一导电件包括电连接至第一重分布线的导电通孔。
在一些实施方式中，第一导电件包括电连接至第一重分布线的被动嵌入件。
在一些实施方式中，第一导电件进一步包括导电凸块。导电凸块在被动嵌入件与第一重分布线之间且电连接被动嵌入件与第一重分布线。
在一些实施方式中，第一导电件进一步包括导电凸块。导电凸块在被动嵌入件与第二重分布线之间且电连接被动嵌入件与第二重分布线。
在一些实施方式中，封装结构进一步包括第二模制材料。第二模制材料模制第二半导体装置。
在一些实施方式中，封装结构进一步包括第二导电件。第二导电件在第二模制材料中且电连接至第二重分布线。
在一些实施方式中，封装结构进一步包括半导体封装。半导体封装在第二模制材料上方且电连接至第二导电件。
在一些实施方式中，封装结构进一步包括在第一半导体装置及第一模制材料上方的缓冲层。
在一些实施方式中，封装结构进一步包括导电凸块。导电凸块在第二重分布线与第一导电件之间且无第一模制材料覆盖。
在一些实施方式中，第一模制材料具有在第一半导体装置与第二介电层之间的部分。
根据一些实施方式，封装结构包括第一介电层、第一半导体装置、导电件、第二介电层、第二半导体装置、重分布线、导电凸块、第一模制材料及第二模制材料。第一半导体装置在第一介电层上方。导电件在第一介电层上方。第二介电层在第一介电层、第一半导体装置及导电件上方。第二半导体装置在第二介电层上方。重分布线在第二介电层中且电连接至第二半导体装置。导电凸块电连接重分布线及导电件。第一模制材料模制第一半导体装置及导电件。第二模制材料模制第二半导体装置。
在一些实施方式中，导电件包括电连接至重分布线的导电通孔。
在一些实施方式中，导电件包括电连接至重分布线的被动嵌入件。
根据一些实施方式，一种形成封装结构的方法包括形成第一组件，其中第一组件包括第一半导体装置、电连接至第一半导体装置的第一重分布线、及电连接至第一重分布线的导电件；形成第二组件，其中第二组件包括第二半导体装置及电连接至第二半导体装置的第二重分布线；以及使用导电凸块将第二组件接合至第一组件上，以便第二重分布线经由导电凸块电连接至导电件。
在一些实施方式中，形成第一组件的步骤包括形成第一重分布线，形成在第一重分布线上方且电连接至第一重分布线的导电件，及将第一半导体装置设置在第一重分布线上方且电连接至第一重分布线。
在一些实施方式中，方法进一步包括以模制材料模制第一半导体装置、导电件、导电凸块及第二半导体装置于其内。
在一些实施方式中，形成第一组件的步骤包括在缓冲层上方形成导电件，在缓冲层上方设置第一半导体装置，以模制材料中模制第一半导体装置及导电件于其内，及形成在第一半导体装置及导电件上方且电连接至第一半导体装置及导电件的第一重分布线。
在一些实施方式中，方法进一步包括在缓冲层中形成开口以暴露导电件。
根据一些实施方式，一种形成封装结构的方法包括以下步骤。形成一第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及该第一导电通孔。形成一第一重分布线，该第一重分布线电连接该第一导电通孔的一第一端及该第一半导体装置，使得该第一缓冲层、该第一导电通孔、该第一半导体装置、该第一模制材料、及该第一重分布线形成一第一封装。形成一第一导电球体于该第一重分布线上方并电连接该第一重分布线。形成一第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及该第二导电通孔。形成一第二重分布线，该第二重分布线电连接该第二导电通孔的一第一端及该第二半导体装置，使得该第二缓冲层、该第二导电通孔、该第二半导体装置、该第二模制材料、及该第二重分布线形成一第二封装。形成一第二导电球体于该第二重分布线上方并电连接该第二重分布线。翻转该第一封装。在翻转该第一封装后，在该第一缓冲层中形成一开口以暴露该第一导电通孔的一第二端。翻转该第二封装。在翻转该第二封装后，将该第二封装堆叠于该第一封装上，使得该第二导电球体位于该第一导电通孔的该第二端并电连接该第一导电通孔的该第二端。
在一些实施方式中，将该第二封装堆叠于该第一封装上，会使得该第二导电球体的一部分会被该第一缓冲层所围绕。
在一些实施方式中，将该第二封装堆叠于该第一封装上，会使得该第二导电球体的一部分从该第一缓冲层的一顶部突起。
在一些实施方式中，方法还包含将一半导体封装接合至该第二导电通孔的一第二端。
在一些实施方式中，方法还包含在形成该第一重分布线之前，薄化该第一模制材料以暴露该第一导电通孔的该第一端。
在一些实施方式中，形成该第一导电通孔的步骤是在形成该第一重分布线的步骤之前进行的。
在一些实施方式中，形成该第二导电通孔的步骤是在形成该第二重分布线的步骤之前进行的。
根据一些实施方式，一种形成封装结构的方法包括以下步骤。形成一第一封装及形成一第二封装。形成第一封装包括以下步骤。形成多个第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔。形成多个第一重分布线于该第一模制材料上。形成多个第一导电球体于所述多个第一重分布线上方。形成第二封装包括以下步骤。形成多个第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔。形成多个第二重分布线于该第二模制材料上。形成多个第二导电球体于所述多个第二重分布线上方。形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔。通过放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，以接合该第二封装至该第一封装。
在一些实施方式中，放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，会使得所述多个第二导电球体填满该第一缓冲层的所述多个开口。
在一些实施方式中，形成所述多个第一导电通孔的步骤是在设置该第一半导体装置的步骤之前进行的。
在一些实施方式中，形成所述多个第二导电通孔的步骤是在设置该第二半导体装置的步骤之前进行的。
在一些实施方式中，当放置所述多个第二导电球体于该第一缓冲层的所述多个开口中之后，所述多个第二导电球体的位于所述多个开口外的剖面轮廓与所述多个导电球体的位于所述多个开口中的剖面轮廓不同。
在一些实施方式中，当放置所述多个第二导电球体于该第一缓冲层的所述多个开口中之后，所述多个第二导电球体的位于所述多个开口外的侧壁比所述多个第二导电球体的位于所述多个开口中的侧壁更弯曲。
在一些实施方式中，当放置所述多个第二导电球体于该第一缓冲层的所述多个开口中之后，所述多个第二导电球体的位于所述多个开口外的侧壁是弯曲的，而所述多个第二导电球体的位于所述多个开口中的侧壁是倾斜的。
在一些实施方式中，当放置所述多个第二导电球体于该第一缓冲层的所述多个开口中之后，所述多个第二导电球体的部分是裸露的。
根据本揭露多个实施方式，一种形成封装结构的方法包括以下步骤。形成一第一封装及形成一第二封装。形成第一封装包括以下步骤。形成多个第一导电通孔于一第一缓冲层上。设置一第一半导体装置于该第一缓冲层上。形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔。形成多个第一重分布线于该第一模制材料上。形成多个第一导电球体于所述多个第一重分布线上方。形成第二封装包括以下步骤。形成多个第二导电通孔于一第二缓冲层上。设置一第二半导体装置于该第二缓冲层上。形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔。形成多个第二重分布线于该第二模制材料上。形成多个第二导电球体于所述多个第二重分布线上方。形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔。接合所述多个第二导电球体至所述多个第一导电通孔，使得所述多个第二导电球体在垂直方向上位于所述多个第一导电通孔与所述多个第二导电通孔之间。
在一些实施方式中，所述多个第二导电通孔的一者、所述多个第二导电球体的一者、与所述多个第一导电通孔的一者在垂直方向上对齐。
在一些实施方式中，所述多个第二导电球体之间的距离大于所述多个第一导电球体之间的距离。
在一些实施方式中，所述多个第二导电球体的宽度小于所述多个第一导电球体的宽度。
在一些实施方式中，所述多个第二导电球体的高度小于所述多个第一导电球体的高度。
以上概述了若干实施方式的特征，使得本领域普通技术人员可清楚理解本揭露的态样。本领域技术人员应理解，他们可易于使用本揭露作为设计及更改其他制程及结构以实现相同目标及/或达成本文介绍实施方式的相同优势的基础。但是本领域技术人员亦应理解，此种等同结构并不脱离本揭露的精神及范畴，以及他们可以在不脱离本揭露的精神及范畴的情况下对本文进行各种改变、置换及变更。

Claims (10)

1.一种形成封装结构的方法，其特征在于，包含：
形成一第一导电通孔于一第一缓冲层上；
设置一第一半导体装置于该第一缓冲层上；
形成一第一模制材料围绕该第一半导体装置及该第一导电通孔；
形成一第一重分布线，该第一重分布线电连接该第一导电通孔的一第一端及该第一半导体装置，使得该第一缓冲层、该第一导电通孔、该第一半导体装置、该第一模制材料、及该第一重分布线形成一第一封装；
形成一第一导电球体于该第一重分布线上方并电连接该第一重分布线；
形成一第二导电通孔于一第二缓冲层上；
设置一第二半导体装置于该第二缓冲层上；
形成一第二模制材料围绕该第二半导体装置及该第二导电通孔；
形成一第二重分布线，该第二重分布线电连接该第二导电通孔的一第一端及该第二半导体装置，使得该第二缓冲层、该第二导电通孔、该第二半导体装置、该第二模制材料、及该第二重分布线形成一第二封装；
形成一第二导电球体于该第二重分布线上方并电连接该第二重分布线；
翻转该第一封装；
在翻转该第一封装后，在该第一缓冲层中形成一开口以暴露该第一导电通孔的一第二端；
翻转该第二封装；及
在翻转该第二封装后，将该第二封装堆叠于该第一封装上，使得该第二导电球体位于该第一导电通孔的该第二端并电连接该第一导电通孔的该第二端。
2.根据权利要求1所述的方法，其特征在于，将该第二封装堆叠于该第一封装上，会使得该第二导电球体的一部分会被该第一缓冲层所围绕。
3.根据权利要求1所述的方法，其特征在于，将该第二封装堆叠于该第一封装上，会使得该第二导电球体的一部分从该第一缓冲层的一顶部突起。
4.根据权利要求1所述的方法，其特征在于，还包含：
将一半导体封装接合至该第二导电通孔的一第二端。
5.根据权利要求1所述的方法，其特征在于，还包含：
在形成该第一重分布线之前，薄化该第一模制材料以暴露该第一导电通孔的该第一端。
6.一种形成封装结构的方法，其特征在于，包含：
形成一第一封装，包含：
形成多个第一导电通孔于一第一缓冲层上；
设置一第一半导体装置于该第一缓冲层上；
形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔；
形成多个第一重分布线于该第一模制材料上；及
形成多个第一导电球体于所述多个第一重分布线上方；
形成一第二封装，包含：
形成多个第二导电通孔于一第二缓冲层上；
设置一第二半导体装置于该第二缓冲层上；
形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔；
形成多个第二重分布线于该第二模制材料上；及
形成多个第二导电球体于所述多个第二重分布线上方；
形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔；及
通过放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，以接合该第二封装至该第一封装。
7.根据权利要求6所述的方法，其特征在于，放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，会使得所述多个第二导电球体接触所述多个第一导电通孔。
8.根据权利要求6所述的方法，其特征在于，放置所述多个第二导电球体于该第一缓冲层的所述多个开口中，会使得所述多个第二导电球体填满该第一缓冲层的所述多个开口。
9.一种形成封装结构的方法，其特征在于，包含：
形成一第一封装，包含：
形成多个第一导电通孔于一第一缓冲层上；
设置一第一半导体装置于该第一缓冲层上；
形成一第一模制材料围绕该第一半导体装置及所述多个第一导电通孔；
形成多个第一重分布线于该第一模制材料上；及
形成多个第一导电球体于所述多个第一重分布线上方；
形成一第二封装，包含：
形成多个第二导电通孔于一第二缓冲层上；
设置一第二半导体装置于该第二缓冲层上；
形成一第二模制材料围绕该第二半导体装置及所述多个第二导电通孔；
形成多个第二重分布线于该第二模制材料上；及
形成多个第二导电球体于所述多个第二重分布线上方；
形成多个开口于该第一缓冲层中以暴露所述多个第一导电通孔；及
接合所述多个第二导电球体至所述多个第一导电通孔，使得所述多个第二导电球体在垂直方向上位于所述多个第一导电通孔与所述多个第二导电通孔之间。
10.根据权利要求9所述的方法，其特征在于，所述多个第二导电通孔的一者、所述多个第二导电球体的一者、与所述多个第一导电通孔的一者在垂直方向上对齐。
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784220B2 (en) 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10529637B1 (en) 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US11164814B2 (en) * 2019-03-14 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11239173B2 (en) * 2019-03-28 2022-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
CN110265425B (zh) * 2019-06-26 2021-10-08 京东方科技集团股份有限公司 一种转移结构及其制备方法、转移装置
US11201205B2 (en) 2019-07-31 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect layout for semiconductor device
US11094635B2 (en) 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US11587905B2 (en) * 2019-10-09 2023-02-21 Industrial Technology Research Institute Multi-chip package and manufacturing method thereof
TWI701777B (zh) * 2019-10-22 2020-08-11 財團法人工業技術研究院 影像感測器封裝件及其製造方法
US11682654B2 (en) * 2019-12-17 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a sensor device and method of manufacturing the same
TW202201673A (zh) * 2020-03-17 2022-01-01 新加坡商安靠科技新加坡控股私人有限公司 半導體裝置和製造半導體裝置的方法
US11715699B2 (en) 2020-03-17 2023-08-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11296065B2 (en) * 2020-06-15 2022-04-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages and methods of forming same
TW202231146A (zh) * 2021-01-25 2022-08-01 優顯科技股份有限公司 電子裝置及其製造方法
US11756873B2 (en) * 2021-02-26 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11756870B2 (en) * 2021-04-29 2023-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked via structure disposed on a conductive pillar of a semiconductor die
CN113314475B (zh) * 2021-05-27 2022-05-17 广东工业大学 一种使用玻璃基板的系统级扇出型封装结构及其加工方法
US11854928B2 (en) * 2021-08-27 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034386B2 (en) * 2001-03-26 2006-04-25 Nec Corporation Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
DE10348620A1 (de) 2003-10-15 2005-06-02 Infineon Technologies Ag Halbleitermodul mit Gehäusedurchkontakten
DE102006037538B4 (de) * 2006-08-10 2016-03-10 Infineon Technologies Ag Elektronisches Bauteil, elektronischer Bauteilstapel und Verfahren zu deren Herstellung sowie Verwendung einer Kügelchenplatziermaschine zur Durchführung eines Verfahrens zum Herstellen eines elektronischen Bauteils bzw. Bauteilstapels
US8133762B2 (en) * 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8193624B1 (en) * 2008-02-25 2012-06-05 Amkor Technology, Inc. Semiconductor device having improved contact interface reliability and method therefor
TWI362732B (en) * 2008-04-07 2012-04-21 Nanya Technology Corp Multi-chip stack package
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5535494B2 (ja) * 2009-02-23 2014-07-02 新光電気工業株式会社 半導体装置
JP5340789B2 (ja) * 2009-04-06 2013-11-13 新光電気工業株式会社 電子装置及びその製造方法
JP5330065B2 (ja) * 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) * 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9082780B2 (en) * 2012-03-23 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
DE112013002672T5 (de) * 2012-05-25 2015-03-19 Nepes Co., Ltd Halbleitergehäuse, Verfahren zum Herstellen desselben und Gehäuse auf Gehäuse
US10115671B2 (en) 2012-08-03 2018-10-30 Snaptrack, Inc. Incorporation of passives and fine pitch through via for package on package
US8975726B2 (en) * 2012-10-11 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. POP structures and methods of forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9111930B2 (en) * 2013-03-12 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package with cavity in interposer
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8980691B2 (en) * 2013-06-28 2015-03-17 Stats Chippac, Ltd. Semiconductor device and method of forming low profile 3D fan-out package
CN103531550B (zh) * 2013-10-31 2016-04-13 华进半导体封装先导技术研发中心有限公司 改进的小间距塑封的封装结构及封装方法
MX2016006825A (es) 2013-12-06 2016-11-28 Halliburton Energy Services Inc Control de operaciones de pozos.
EP3087599A4 (en) * 2013-12-23 2017-12-13 Intel Corporation Package on package architecture and method for making
US9576926B2 (en) * 2014-01-16 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure design in fan-out package
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9281297B2 (en) * 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10453785B2 (en) * 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
US9646918B2 (en) * 2014-08-14 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9679842B2 (en) * 2014-10-01 2017-06-13 Mediatek Inc. Semiconductor package assembly
TWI548043B (zh) * 2014-11-17 2016-09-01 矽品精密工業股份有限公司 封裝結構及其製法
US10032704B2 (en) * 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US20160240457A1 (en) * 2015-02-18 2016-08-18 Altera Corporation Integrated circuit packages with dual-sided stacking structure
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
CN105225965B (zh) * 2015-11-03 2019-01-25 中芯长电半导体（江阴）有限公司 一种扇出型封装结构及其制作方法
KR101681031B1 (ko) * 2015-11-17 2016-12-01 주식회사 네패스 반도체 패키지 및 그 제조방법
US9871009B2 (en) 2016-06-15 2018-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer

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US11417620B2 (en) 2022-08-16
US20210005562A1 (en) 2021-01-07
CN108695267A (zh) 2018-10-23
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US10784220B2 (en) 2020-09-22
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US11887952B2 (en) 2024-01-30

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