TWI497620B - 矽貫通孔晶粒及封裝 - Google Patents

矽貫通孔晶粒及封裝 Download PDF

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Publication number
TWI497620B
TWI497620B TW101116397A TW101116397A TWI497620B TW I497620 B TWI497620 B TW I497620B TW 101116397 A TW101116397 A TW 101116397A TW 101116397 A TW101116397 A TW 101116397A TW I497620 B TWI497620 B TW I497620B
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Taiwan
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die
contact
major surface
mask
contacts
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TW101116397A
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TW201246415A (en
Inventor
Hao Liu
Yi Sheng Anthony Sun
Ravi Kanth Kolan
Chin Hock Toh
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United Test & Assembly Ct Lt
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Publication of TW201246415A publication Critical patent/TW201246415A/zh
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Description

矽貫通孔晶粒及封裝
長期以來，具有增加之功能性及高密度記憶體之消費性電子產品的小型化一直是半導體封裝發展中的主要驅動力之一。極度密集之電子產品可藉由將具有互連接線之薄矽晶片以垂直方向堆曡而建立。矽貫通孔(TSV)製程係封裝業中使用的技術之一，其使薄矽積體電路(IC)可堆曡以提供異質整合及可能增加一些電子系統之功能的實體密度。另外，此項技術藉由顯著增加一給定IC之區域互連能力而使得適於多個IC層間之真垂直整合的潛在架構組態成為可能。
希望改良TSV技術，舉例而言，簡化設計及處理以改良良率，減少成本及/或改良生產量。
實施例大致上係關於晶片封裝。更具體言之，實施例係關於3D晶片封裝。3D晶片封裝可藉由TSV晶粒而促進。
一方面，本文提供了一種用於製備一用於封裝之晶粒的方法。該方法包括提供一具有第一及第二主表面的晶粒。孔被形成於該晶粒之第一主表面上。該方法包括在第一主表面上形成一遮罩層。該遮罩包含曝露孔的遮罩開口。遮罩開口被填充以一導電材料。此外該方法包括回焊以至少部分地填充孔及接點開口以在孔中形成孔接點及在遮罩開口中形成表面接點。
在另一實施例中，揭示了一種包括提供具有孔接點穿過晶粒之主表面之n個晶粒的封裝方法。該方法包括堆曡n個晶粒以形成一晶粒堆曡，其中n=1係底部晶粒，n=n係堆曡之頂部晶粒，其中第n個晶粒上之孔被耦合至相鄰晶粒或多個晶粒的孔。堆曡之晶粒中的至少一個包含一回焊類型晶粒，該回焊類型晶粒包含一具有第一及第二主表面以及穿過該等主表面之孔的晶粒基板。該回焊類型晶粒包括在一具有與孔對應之接點開口之第一主表面上的一遮罩，及孔中之孔接點及接點開口中之表面接點，其中形成接點包含用一導電材料填充接點開口及回焊以填充孔開口。
另一方面，本文提出一種包括一具有第一及第二主表面之晶粒基板的晶粒。該晶粒包括穿過晶粒之第一及第二表面的孔以及第一主表面上的一接點遮罩。該接點遮罩包含與孔對應之遮罩開口。此外該晶粒包括填充孔及遮罩開口以在孔中形成孔接點及在遮罩開口中形成表面接點的一種導電材料。
通過參考以下描述及附圖，此等及其他目的連同本文揭示之本發明的優點及特徵一起將變得明顯。此外，應瞭解本文所描述之多種實施例的特徵並不互斥且可以多種組合及置換之形式存在。
圖式中，相同參考字符一般係指所有不同圖中之相同部分。又，圖式不必按比例衡量，而重點大致上係在於說明本發明之原理。以下描述中，本發明之多種實施例係參考以下圖式來描述。
實施例大致上係關於製備晶片以用於封裝以及晶片封裝。其他類型之應用亦可有用。多種類型之晶片或IC可被封裝。舉例而言，IC可為一記憶體裝置諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)以及包括可程式唯讀記憶體(PROM)及快閃記憶體的多種類型之非揮發性記憶體，一光電子裝置，一邏輯裝置，一通信裝置，一數位信號處理器(DSP)，一微控制器，一晶片上系統，以及其他類型之裝置。IC可被併入多種產品中，諸如電話機、電腦、個人數位助理或其他類型的適當產品。
圖1顯示一TSV晶粒或晶片100的一實施例。該晶粒包含一具有第一(底部)及第二(頂部)主表面的基板110，該等主表面具有電路組件形成於其中。該基板包含一半導體基板，諸如矽。其他類型之基板，舉例而言，絕緣體上矽，亦係有用的。
至少一個貫通孔140被提供。貫通孔穿過基板110之主表面。在一實施例中，貫通孔包含一漸縮側壁輪廓。舉例而言，側壁被漸縮大約70°至90°。側壁的漸縮促進孔的填充。舉例而言，漸縮側壁促使孔之側壁及基底的均勻材料覆蓋，此減少空隙之形成。提供具有一非漸縮側壁輪廓之孔亦係有用的。
孔用一導電材料填充以形成孔接點144。晶粒之表面包含至少一表面接點150。表面接點被耦合至孔接點。一般而言晶粒包含複數個孔及表面接點。孔及表面接點可以一期望圖案被配置。舉例而言，接點可以一柵或陣列圖案被配置。其他圖案，諸如將接點定位於晶粒之周邊附近，亦係有用的。較佳地，孔及表面接點包含相同材料。在一實施例中，孔及表面接點包含焊錫。多種類型之焊錫可被使用。舉例而言，焊錫包含鉛或無鉛焊錫。
一接點遮罩130被安置於晶粒之頂部表面上。該接點遮罩包含曝露表面接點的接點開口133。在一實施例中，接點遮罩包含一圖案化光阻。其他類型之材料可被用於當作接點遮罩。舉例而言，接點遮罩可包含一焊錫遮罩。在一實施例中，接點遮罩促進形成孔及表面接點。舉例而言，接點遮罩提供可作為用於安置導電材料以形成孔及表面接點之模板的接點開口。一晶粒附接(DA)層170可被提供於接點遮罩之上。舉例而言，該DA層包含晶粒附接膜或B-階段(半硬化階段)晶粒附接黏著劑及被用於將另一晶粒牢固地堆曡於其上。複數個晶粒可被共同堆曡以形成一晶粒堆曡。
圖2顯示一封裝205之一實施例。該封裝包括一具有底部及頂部主表面211及212之載體或封裝基板220。舉例而言，載體可為一單一或多層積層基板。其他類型之載體亦係有用的。封裝接點(未顯示)被安置於主表面其中之一上。在一實施例中，封裝接點被定位於底部表面上。封裝接點可包含以一柵圖案配置以形成一BGA的球形結構或球體。舉例而言，球體包含焊錫。多種類型之焊錫可被使用，諸如鉛或無鉛合金。以其他圖案配置接點或提供其他類型之接點或材料亦係有用的。
在一實施例中，一晶粒接合區260被提供於載體之頂部表面上。該晶粒接合區包含接合接點265。接合接點包含球形結構或球體。接合接點可以多種圖案配置。舉例而言，接點可以一柵圖案配置。接合接點之圖案應對應於待安裝至其上之晶片的孔圖案。其他類型之圖案亦係有用的。舉例而言，接合接點包含焊錫。多種類型之焊錫可被使用，諸如鉛或無鉛合金。接合接點被互連至載體之底部表面上的封裝接點。
在一實施例中，一晶粒堆曡202被安裝至封裝上。該晶粒堆曡包含n個晶粒1001 -100n ，其中n2。一DA層270可被提供以促進晶粒堆曡在一起。舉例而言，晶粒包含如圖1中所述之TSV晶片。在一實施例中，堆曡之底部晶片(n=1)的孔接點被耦合至封裝之接合接點。對於其他晶片，孔接點被耦合至下方晶片之表面接點。晶粒堆曡之晶粒可具有相同類型及/或大小。提供具有不同類型及/或大小之晶片的晶粒堆曡亦係有用的。至於堆曡之頂部的晶粒，其可為一TSV或其他類型之晶粒。舉例而言，頂部晶粒可為一倒裝晶片。一DA膜可被提供於晶粒之頂部表面上以促進堆曡。
在一實施例中，一底部填充材料268，諸如環氧樹脂可被提供於晶片與載體之間所形成之空腔內以囊封及保護接合接點。舉例而言，底部填充材料可用於減少凸塊與接點墊之間的熱應力，改良可靠性。較佳地，底部填充材料填充晶片與載體之間的空間，完全包住凸塊。多種技術可用於將底部填充材料提供至空腔內。舉例而言，底部填充材料可沿著晶粒邊緣進行針式分配及藉由毛細管作用流入晶粒與載體之間的空間內及被固化以形成一永久接合。用於施加底部填充材料之其他技術亦係有用的。一帽狀物(未顯示)可被提供以囊封晶片堆曡。舉例而言，該帽狀物包含一模製化合物。
圖3a-k顯示一用於製備一晶粒及將晶粒整配在一封裝內之製程的一實施例。圖3a顯示一晶粒300。該晶粒包含一具有第一(底部)及第二(頂部)主表面的基板310。該基板包含一半導體基板，諸如矽。其他類型之基板，舉例而言，絕緣體上矽，亦係有用的。該基板製備有電路組件，諸如電晶體、電阻器、電容器及互連接線以形成一IC。一鈍化層可被提供以保護晶粒。一般而言，複數個晶粒在用作該等晶粒之基板的晶圓上被並行處理。舉例而言，晶圓之厚度可為大約700 μm。提供具有其他厚度之晶圓亦係有用的。
論及圖3b，盲孔340被形成。在一實施例中，孔係藉由雷射鑽孔形成。其他技術，諸如深反應性離子蝕刻(DRIE)亦係有用的。舉例而言，DRIE包括在晶粒上形成一遮罩層且進行圖案化以曝露晶粒中將形成孔之部分。舉例而言，遮罩層包含光阻。其他類型之遮罩，諸如一硬遮罩亦係有用的。晶粒之曝露部分藉由DRIE蝕刻，形成盲孔。在一實施例中，盲孔被形成為具有一漸縮輪廓。舉例而言，孔包含一大約為70°至90°之漸縮側壁輪廓。側壁的漸縮促進孔的填充。舉例而言，漸縮側壁促使孔之側壁及基底的均勻材料覆蓋，此減少空隙之形成。提供具有一非漸縮側壁輪廓之孔亦係有用的。蝕刻遮罩在孔形成後可被移除。UBM電鍍可在晶粒之表面上執行以形成一與接點相容之介面。多種習知之UBM製程可被使用。
在圖3c中，一接點遮罩330形成於晶粒之頂部表面上。舉例而言，接點遮罩包含光阻。其他類型之接點遮罩亦係有用的。光阻用一曝光光源被選擇性地曝光且顯影以形成曝露孔的接點開口333。或者，一焊錫遮罩可被用作為接點遮罩。舉例而言，焊錫遮罩可被模板印刷至具有曝露孔之開口的晶粒之頂部表面上。遮罩厚度及開口之大小經選擇以容納足够量的導電材料以產生具有期望尺寸的表面及孔接點。
在圖3d中，一導電材料352沉積於基板上，至少填充接點開口。在一實施例中，導電材料包含焊錫膏。多種類型之焊錫膏可被使用。舉例而言，鉛或無鉛焊錫膏可被使用。使用焊錫膏印刷技術與一模板319一起可將焊錫膏形成於開口之中。模板可為網篩或金屬模板。用於將焊錫印刷於接點開口中之其他技術亦係有用的。
論及圖3e，模板在印刷焊錫膏之後被移除。一回焊製程被執行。由於毛細管效應，回焊至少部分填充孔以形成孔接點344。回焊亦在孔接點上方之接點開口內形成半球形表面接點350。應瞭解，回焊溫度應取決於所使用之導電材料的類型且典型地在足以回焊及熔化導電材料之溫度下實施。
在一實施例中，如圖3f所示，晶圓之底部表面被研磨(背面研磨)以減少晶圓之厚度。背面研磨曝露孔接點之底部。一DA膜370可被形成於晶粒之頂部，如圖3g所示。舉例而言，該DA膜被形成於接點遮罩之上。DA膜當作用於將另一晶粒附接至其的黏著劑。
在一實施例中，晶圓可被分割以將晶圓分離為個體晶粒。
在圖3h中，複數個晶粒3001 -300n 被堆曡以形成一晶粒堆曡302。例示性地，該晶粒堆曡包含4個晶粒(n=4)。提供其他數目之晶粒亦係有用的。晶粒堆曡之晶粒可具有相同類型及相同大小。提供具有不同類型及/或大小之晶粒的晶粒堆曡亦係有用的。至於堆曡之頂部的晶粒，其可為一TSV或其他類型之晶粒。舉例而言，頂部晶粒可為一倒裝晶片。在一實施例中，堆曡之晶粒包含相同之類型。
堆曡之底部的晶粒(n=1)被稱為母晶粒。在一實施例中，此時，背面研磨尚未在該母晶粒上執行。這使母晶粒可提供機械支撐及避免在堆曡製程期間需要一暫時載體基板以用於支撐。在一實施例中，母晶粒係一包含複數個母晶粒之晶圓的一部分。舉例而言，晶圓之母晶粒被堆曡以晶粒以形成複數個晶粒堆曡。
在圖3i中，晶粒堆曡被回焊，導致每一晶粒之表面及孔接點的熔化以及頂部晶粒下方之晶粒之接點開口中空間的填充。回焊形成晶粒堆曡之晶粒之間的連接。應瞭解，回焊溫度應取決於形成表面及孔接點所使用之材料的類型，且典型地應為材料能熔化及形成晶粒間連接之溫度。回焊之後，在具有母晶粒之晶圓上執行背面研磨以曝露孔之底部，如圖3j所示。背面研磨之後，晶圓被分割以將其分離為複數個個體晶粒堆曡。或者，晶粒可被堆曡於一個體未研磨母晶粒上，該未研磨母晶粒隨後被減薄以曝露孔之底部。
形成晶粒堆曡之其他實施例亦係有用的。舉例而言，晶粒堆曡之晶粒仍可作為晶圓之部分。複數個晶圓被堆曡於具有母晶粒之晶圓上。這產生一包含複數個晶粒堆曡的晶圓堆曡。該製程按圖3i描述的繼續進行。
在另一實施例中，母晶粒可為與晶粒堆曡之其他晶粒相同的個體母晶粒。或者，具有母晶粒之晶圓的背面研磨可在將晶圓與堆曡之晶粒堆曡在一起以形成一晶圓堆曡之前執行。即，堆曡之前，母晶粒已被減薄。這可能是有利的，因為晶粒堆曡之回焊步驟可被整合至一後續回焊製程中。對於經減薄之母晶粒，一暫時載體基板可在堆曡製程期間被用作一支撐及其後被移除。
論及圖3k，晶粒堆曡被整配至晶片封裝305之載體320上。在一實施例中，堆曡被安裝於被安置在載體之接合區之上的接合接點365上。舉例而言，接合區被定位於載體之頂部表面上。接合接點係與母晶粒上之孔成對的。接合接點被耦合至位於例如在載體之底部表面上的封裝接點(未顯示)。一回焊被執行以形成接合接點與孔的永久連接。應瞭解，回焊溫度取決於接合接點之材料，且一般應為足以熔化及形成與封裝接點之互連的溫度。一底部填充材料368可被提供以填充晶粒堆曡與載體之間的空間。
如所描述的，本發明提出使用焊錫膏來填充矽貫通孔。與使用Cu填充之目前TSV製程相比較，用於形成焊錫凸塊之焊錫電鍍及回焊以及孔洞填充係相對更快且更便宜的。另外，在晶圓之第二表面上不需要底層凸塊金屬化(UBM)及凸塊化，因為在回焊製程期間使用焊錫建立連接。由於焊錫在回焊溫度下之液態特性，空隙或氣泡可容易地經由孔洞通道被移除。此外，對於其中母晶粒或晶圓一直保持為未研磨直到晶粒或晶圓堆曡完成之後的應用，在堆曡期間不需要一暫時支撐載體以支撐堆曡總成及因此特定接合及脫膠需求係無必要的。
在不脫離本發明之精神及基本特性下，本發明可以其他特定形式實施。因此，前述實施例在所有方面均應被視為說明性而非限制本文所述之發明。
100．．．TSV晶粒/晶片
1001 ．．．晶粒
100n ．．．晶粒
110．．．基板
130．．．接點遮罩
133．．．接點開口
140．．．貫通孔
144．．．孔接點
150．．．表面接點
170．．．晶粒附接(DA)層
202．．．晶粒堆曡
205．．．封裝
211．．．底部主表面
212．．．頂部主表面
220．．．載體/封裝基板
260．．．晶粒接合區
265．．．接合接點
268．．．底部填充材料
270．．．DA層
300．．．晶粒
3001 ．．．晶粒
300n ．．．晶粒
302．．．晶粒堆曡
305．．．晶片封裝
310．．．基板
319．．．模板
320．．．載體
330．．．接點遮罩
333．．．接點開口
340．．．盲孔
344．．．孔接點
350．．．表面接點
352．．．導電材料
365．．．接合接點
368．．．底部填充材料
370．．．DA膜
圖1顯示一晶片之一實施例；
圖2顯示一晶片封裝之一實施例；及
圖3a-k顯示封裝晶片之一實施例。
100．．．TSV晶粒/晶片
110．．．基板
130．．．接點遮罩
133．．．接點開口
140．．．貫通孔
144．．．孔接點
150．．．表面接點
170．．．晶粒附接(DA)層

Claims (19)

  1. 一種晶粒，其包含：一具有一第一主表面及一第二主表面的晶粒基板；穿過該晶粒之該第一主表面及該第二主表面的複數個孔；在該第一主表面上的一接點遮罩，該接點遮罩包含與該等孔相對應的複數個遮罩開口；及一回焊導電材料，其安置於該等孔及遮罩開口中以在該等孔中形成複數個孔接點及在該等遮罩開口中形成複數個表面接點，其中該等孔接點自該第一主表面延伸至該晶粒之該第二主表面並與該第二主表面共面，及該等表面接點部分地佔據該等遮罩開口並接觸該等遮罩開口之內壁，同時留下一空間於該等遮罩開口中。
  2. 如請求項1之晶粒，其中該回焊導電材料包含焊錫。
  3. 如請求項1之晶粒，其包含在該接點遮罩上的一晶粒附接膜。
  4. 如請求項1之晶粒，其中該孔接點及該表面接點係一單一整合之接點單元。
  5. 如請求項4之晶粒，其中該單一整合之接點單元包含相同的回焊導電材料。
  6. 一種晶粒堆疊，其包含：複數個晶粒(n個晶粒)，其中該等晶粒之每一者包括：一具有一第一主表面及一第二主表面的晶粒基板；穿過該晶粒之該第一主表面及該第二主表面的複數 個孔；在該第一主表面上的一接點遮罩，該接點遮罩包含與該等孔相對應的複數個遮罩開口；及一回焊導電材料，其安置於該等孔及遮罩開口中以在該等孔中形成複數個孔接點及在該等遮罩開口中形成複數個表面接點；及該晶粒堆疊之一底部晶粒係一第一晶粒(n=1)，及該晶粒堆疊之一頂部晶粒係第n個晶粒，其中該n個晶粒被堆疊而使得在下方之一晶粒(第n-1個晶粒)之該接點遮罩被安置於在上方之一晶粒(第n個晶粒)之該第二主表面下方，及其中在上方之該晶粒之該等孔接點直接接觸在下方之該晶粒之該等表面接點。
  7. 如請求項6之晶粒堆疊，其中該回焊導電材料包含焊錫。
  8. 如請求項6之晶粒堆疊，其中該孔接點及該表面接點係一單一整合之接點單元。
  9. 如請求項8之晶粒堆疊，其中該單一整合之接點單元包含相同的回焊導電材料。
  10. 如請求項6之晶粒堆疊，其中該等晶粒之每一者包含在該接點遮罩上的一晶粒附接膜。
  11. 如請求項10之晶粒堆疊，其中在下方之該第n-1個晶粒之該晶粒附接膜接觸在上方之該第n個晶粒之該第二主表面。
  12. 如請求項6之晶粒堆疊，其中該等孔接點自該第一主表 面延伸至該晶粒之該第二主表面並與該第二主表面共面，及該等表面接點至少部分地填充該等遮罩開口並接觸該等遮罩開口之內壁。
  13. 如請求項6之晶粒堆疊，其中該等孔接點自該第一主表面延伸至該晶粒之該第二主表面並與該第二主表面共面，及該等表面接點完全地填充該等遮罩開口並接觸該等遮罩開口之內壁。
  14. 如請求項6之晶粒堆疊，其中該第n個晶粒之該等孔接點被安置於該第n-1個晶粒之該等表面接點上。
  15. 一種半導體封裝，其包含：一晶粒堆疊，其中該晶粒堆疊包括：複數個晶粒(n個晶粒)，其中該等晶粒之每一者包括：一具有一第一主表面及一第二主表面的晶粒基板；穿過該晶粒之該第一主表面及該第二主表面的複數個孔；在該第一主表面上的一接點遮罩，該接點遮罩包含與該等孔相對應的複數個遮罩開口；及一回焊導電材料，其安置於該等孔及遮罩開口中以在該等孔中形成複數個孔接點及在該等遮罩開口中形成複數個表面接點；及該晶粒堆疊之一底部晶粒係一第一晶粒(n=1)，及該晶粒堆疊之一頂部晶粒係第n個晶粒，其中該n個晶粒 被堆疊而使得在下方之一晶粒(第n-1個晶粒)之該接點遮罩被安置於在上方之一晶粒(第n個晶粒)之該第二主表面下方，其中在上方之該晶粒之該等孔接點直接接觸在下方之該晶粒之該等表面接點；及一載體，其具有在該載體之一第一表面上之一接合區，其中該晶粒堆疊被安裝在該載體之該接合區上。
  16. 如請求項15之半導體封裝，其中該回焊導電材料包含焊錫。
  17. 如請求項15之半導體封裝，其中該等晶粒之每一者包含在該接點遮罩上的一晶粒附接膜。
  18. 如請求項15之半導體封裝，其中該孔接點及該表面接點係一單一整合之接點單元。
  19. 如請求項18之半導體封裝，其中該單一整合之接點單元包含相同的回焊導電材料。
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