TW202117874A - 封裝結構及其製造方法與封裝體 - Google Patents
封裝結構及其製造方法與封裝體 Download PDFInfo
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- TW202117874A TW202117874A TW108147158A TW108147158A TW202117874A TW 202117874 A TW202117874 A TW 202117874A TW 108147158 A TW108147158 A TW 108147158A TW 108147158 A TW108147158 A TW 108147158A TW 202117874 A TW202117874 A TW 202117874A
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- metal core
- semiconductor device
- package
- core solder
- solder ball
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Abstract
一種方法包括:將金屬芯焊料球放置於第一半導體裝置的導電接墊上,其中所述金屬芯焊料球包括由焊料材料包圍的金屬芯;以及形成裝置結構,形成所述裝置結構包括:將所述第一半導體裝置放置於載體基底上;用包封體包封所述第一半導體裝置,其中所述包封體覆蓋所述金屬芯焊料球;對所述包封體執行平坦化製程,其中所述平坦化製程暴露出所述金屬芯焊料球;以及在所述包封體及所述第一半導體裝置之上形成重佈線結構,其中所述重佈線結構電性連接至所述金屬芯焊料球。
Description
半導體產業藉由最小特徵大小(minimum feature size)的持續減小而不斷改善各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的積體密度,此使得更多組件能夠被整合於給定面積中,因此使得更多功能能夠被整合於給定面積中。具有高功能性的積體電路需要許多輸入/輸出(input/output)接墊。然而,在小型化為重要的應用中,可能需要小的封裝體。
積體扇出型(Integrated Fan Out,InFO)封裝技術正變得日漸流行,特別是當與晶圓級封裝(Wafer Level Packaging,WLP)技術結合時,在晶圓級封裝技術中積體電路被封裝於通常包括重佈線層(redistribution layer,RDL)或後鈍化內連線(post passivation interconnect)的封裝體中,所述重佈線層或後鈍化內連線用於對封裝體的接觸墊進行扇出型配線(fan-out wiring),以便可以較積體電路的接觸墊大的間距來進行電性接觸。此種所得封裝結構以相對低的成本來提供高功能密度以及提供高效能封裝體。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本發明。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵之上或第二特徵上可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,而不是以此表示所論述的各種實施例及/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「位於……之下(beneath)」、「位於……下方(below)」、「下部的(lower)」、「位於……上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向),且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
在本發明的實施例中,闡述裝置封裝體及其形成的各種態樣。裝置封裝體可例如為系統級封裝體(system-in-package)。在一些實施例中,封裝體內的裝置可使用金屬芯焊料球電性連接至重佈線結構(redistribution structure)。可在形成重佈線結構之前對金屬芯焊料球進行包封且然後進行平坦化以暴露出金屬芯。藉由使用金屬芯焊料球來形成電性連接,可改善裝置封裝體的電效能、良率及可靠性,且可降低裝置封裝體的總體製造成本。可在芯基底(core substrate)上形成內連結構,且然後將所述內連結構貼合至重佈線結構。內連結構可為裝置封裝體提供剛性,並減少翹曲(warping)或分層(delamination)變化。
圖1及圖2示出根據一些實施例具有金屬芯焊料球110的電子裝置100的剖視圖。圖3至圖8示出根據一些實施例形成封裝結構200(參見圖8)的中間步驟的剖視圖。圖9A及圖9B至圖12示出根據一些實施例形成封裝體400(參見圖12)的中間步驟的剖視圖。
圖1示出根據一些實施例的電子裝置100。電子裝置100可例如是晶粒(例如,積體電路晶粒、功率積體電路晶粒、邏輯晶粒等)、晶片、半導體裝置、記憶體裝置(例如,記憶體堆疊(memory stack)、動態隨機存取記憶體(dynamic random access memory,DRAM)、快閃記憶體、高頻寬記憶體(High-Bandwidth Memory,HBM)等)、被動裝置(例如,積體被動裝置(integrated passive device,IPD)、多層陶瓷電容器(multi-layer ceramic capacitor,MLCC)、電壓調節器等)、另一種類型的電子裝置、系統晶片(system-on-chip,SoC)、晶圓上組件(component on wafer,CoW)、包括一或多個晶粒或裝置等的封裝體、或其組合。電子裝置100可包括一或多個主動裝置(例如電晶體、二極體等)及/或一或多個被動裝置(例如電容器、電阻器、電感器等)。在一些實施例中,電子裝置100可為表面安裝型裝置(surface-mount device,SMD)等。在一些實施例中,電子裝置100具有在約100微米(μm)與約1200微米之間的厚度,且具有在約4平方毫米(mm2
)與約900平方毫米之間的面積。圖1所示的電子裝置100旨在作為說明性實例,且可使用其他類型、組合或配置的電子裝置。
在一些實施例中,電子裝置100包括用於在電子裝置100與其他裝置或組件之間進行電性連接的導電連接件106。在一些實施例中,導電連接件106可為電子裝置100的內連結構或重佈線結構的一部分。在一些實施例中,導電連接件106包括凸塊下金屬化物(under bump metallization,UBM),此在圖1中未單獨指示。在實施例中,導電連接件106的UBM可包括三層導電材料,例如鈦層、銅層及鎳層。然而,本技術領域中具有通常知識者可認識到,存在許多適合於形成UBM的適合的材料及層佈置,例如鉻/鉻銅合金/銅/金的佈置、鈦鎢/銅/鎳的佈置或鈦/銅/鎳/金的佈置。可用於導電連接件106的UBM的任何適合的材料或不同材料層的組合均完全包含於本申請案的範圍內。
在一些實施例中,鈍化層104可形成於導電連接件106之上。鈍化層104可被圖案化成暴露出導電連接件106的部分。在實施例中,鈍化層104可為例如氧化物(例如氧化矽等)、氮化物(例如氮化矽等)、聚苯并[口咢]唑(polybenzoxazole,PBO)、聚醯亞胺、聚醯亞胺衍生物等材料,或者另一適合的材料或材料組合。在一些實施例中,鈍化層104可在導電連接件106的部分之上延伸。UBM(若存在)可在鈍化層104形成之前或之後形成。
轉至圖2,根據一些實施例,金屬芯焊料球110被放置於導電連接件106上。金屬芯焊料球110包括可塗佈有焊料層114的金屬芯112。金屬芯112可為金屬或金屬合金,例如銅、銅合金等。在一些實施例中,金屬芯112可為近似球形的形狀,且可具有在約14微米與約600微米之間的直徑,但在其他實施例中,金屬芯112可具有其他尺寸。在其他實施例中,金屬芯112可具有不同於球形的形狀,例如圓柱形、不規則形狀或另一形狀。在放置金屬芯焊料球110之前,焊料層114可部分或完全地覆蓋金屬芯112。焊料層114可為焊料材料,例如SnAg、SnCu、SnBi、SnAgCu等。在一些實施例中,焊料層114可具有在約1微米與約200微米之間的厚度,但焊料層114可具有與所給出值不同的厚度,或者焊料層114的不同部分可具有不同的厚度。在一些實施例中,金屬芯焊料球110可為近似球形的形狀,且可具有在約15微米與約610微米之間的直徑,但在其他實施例中,金屬芯焊料球110可具有其他尺寸。在其他實施例中,金屬芯焊料球110可具有不同於球形的形狀,例如圓柱形、不規則形狀或另一形狀。
在一些情形中,金屬芯焊料球110中存在金屬芯112可使得例如電子裝置100等裝置與另一組件(例如,圖6所示的重佈線結構220)之間的傳導及連接可靠性能夠改善。在一些情形中,在高速操作(例如,大於約2十億位元/秒(Gbit/second))期間,電訊號可在導電組件的表面附近傳導。金屬芯112可具有較焊料更小的表面粗糙度,且因此使用金屬芯焊料球110可降低較高速訊號所經歷的電阻,且亦降低高速操作期間的訊號損耗(例如插入損耗(insertion loss))。此可改善高速電路(例如,串聯器/解串器(Serializer/Deserializer,「SerDes」)電路或可以較高速度運行的其他電路)的效能。在一些情形中,金屬芯112可具有小於約0.1微米的粗糙度RA。在一些情形中,金屬芯112可較焊料對於熱效應更穩健,且因此可具有較其他類型的連接更大的可靠性。
在一些實施例中,使用模板技術(stencil technique)將金屬芯焊料球110放置於導電連接件106上。例如,可將具有與導電連接件106的位置對應的開口的模板與導電連接件106對齊,且可在模板開口內放置或以其他方式沈積金屬芯焊料球110,使得金屬芯焊料球110接觸對應的導電連接件106。在一些實施例中,可在放置金屬芯焊料球110之前將焊劑材料(flux material)施加至導電連接件。可執行回焊製程(reflow process)以使金屬芯焊料球110的焊料層114的材料回焊並將金屬芯焊料球110結合至導電連接件106。在執行回焊製程之後,每一金屬芯焊料球110的金屬芯112可實體地接觸導電連接件106,或者可藉由焊料層114(及/或焊劑,若存在的話)的一部分與導電連接件106分隔開。焊料層114的此部分可較在執行回焊製程之前焊料層114的原始厚度薄。在其他實施例中,可使用植球技術(ball-placement technique)或其他適合於放置金屬芯焊料球110的技術。在一些實施例中,電子裝置100上的金屬芯焊料球110的間距可在約30微米與約1000微米之間。
圖3至圖8示出根據一些實施例使用金屬芯焊料球110來形成封裝結構200(參見圖8)的中間步驟的剖視圖。現在參照圖3,其示出根據一些實施例的上面已放置有一或多個裝置(例如電子裝置100及/或半導體裝置210(如以下所述))的載體基底202。圖3示出單個半導體裝置210及二個電子裝置100,但在其他實施例中,可在載體基底202上放置另一數目的半導體裝置210及/或另一數目的電子裝置100。電子裝置100可為相似類型的電子裝置或不同類型的電子裝置。可以任何適合的佈置或配置來放置電子裝置100及半導體裝置210。
載體基底202可例如包含矽系材料(例如矽基底(例如矽晶圓))、玻璃材料、氧化矽或其他材料(例如氧化鋁等)或其組合。在一些實施例中,載體基底202可為面板結構,其可例如是由適合的介電材料(例如玻璃材料、塑膠材料或有機材料)形成的支撐基底。面板結構可例如是矩形面板。載體基底202可為平坦的,以適應例如電子裝置100或半導體裝置210等裝置的貼合。
作為說明性實例,圖13A及圖13B示出根據一些實施例使用不同類型的載體基底202形成的封裝結構200(參見圖9A)。圖13A示出其中載體基底202是矽晶圓的實施例,且圖13B示出其中載體基底202是面板結構的實施例。圖13A至圖13B示出形成於載體基底202上的多個封裝結構200。如此一來,可使用不同類型的載體基底202來形成多個封裝結構200。亦可使用不同類型的載體基底202來形成多個封裝體400(參見圖12)。隨後可將形成於載體基底202上的封裝結構200或封裝體400單體化,以形成單獨的封裝結構200或單獨的封裝體400。
轉回至圖3,在一些實施例中,可在載體基底202的頂表面上形成釋放層204,以利於載體基底202的後續剝離。在一些實施例中,釋放層204可由聚合物系材料形成,所述釋放層可與載體基底202一起自將在後續步驟中形成的上覆結構被移除。在一些實施例中,釋放層204為當受熱時會失去其黏合性質的環氧系熱釋放材料,例如光熱轉換(Light-to-Heat-Conversion,LTHC)釋放塗層。在其他實施例中,釋放層204可為當暴露於紫外(ultra-violet,UV)光時會失去其黏合性質的紫外(UV)膠。釋放層204可以液體形態被施配並被固化,或可為疊層至載體基底202上的疊層膜(laminate film)等。釋放層204的頂表面可被整平且可具有高的共面程度。在一些實施例中,作為釋放層204的代替或補充,可使用晶粒貼合膜(die attach film,DAF)(未示出)。
半導體裝置210可包括一或多個裝置,所述一或多個裝置可包括為預期目的而設計的裝置,例如記憶體晶粒(例如,DRAM晶粒、堆疊式記憶體晶粒、高頻寬記憶體(HBM)晶粒等)、邏輯晶粒、中央處理單元(central processing unit,CPU)晶粒、系統晶片(SoC)、晶圓上組件(CoW)、積體扇出型(InFO)結構、封裝體等或其組合。在實施例中,根據特定功能的需要,半導體裝置210在其中包括積體電路裝置,例如電晶體、電容器、電感器、電阻器、金屬化層、外部連接件等。在一些實施例中,半導體裝置210可包括多於一個同一類型的裝置,或者可包括不同的裝置。在一些實施例中,半導體裝置210可與先前在圖1中所述的電子裝置100相似。
在實施例中,半導體裝置210包括接點212。在一些實施例中,接點212可為導電柱,例如銅柱(copper pillar)或銅桿(copper post)。在其他實施例中,接點212可為焊料凸塊、銅凸塊或可用於提供與半導體裝置210的電性連接的其他適合的接觸結構。所有此些接點均完全被設想包含於實施例的範圍內。在其他實施例中,接點212可使用與先前所述的金屬芯焊料球110相似的金屬芯焊料球來形成。在一些實施例中,半導體裝置上的接點212的間距可在約30微米與約300微米之間。
轉至圖4,根據一些實施例,使用包封體214來包封電子裝置100及半導體裝置210。可在模塑裝置(molding device)中執行所述包封,或者可使用另一技術沈積包封體214。包封體214可例如是模塑化合物,例如樹脂、聚醯亞胺、聚苯硫醚(polyphenylene sulfide,PPS)、聚醚醚酮(polyether ether ketone,PEEK)、聚醚碸(polyether sulfone,PES)、另一材料等或其組合。包封體214可包圍及/或覆蓋金屬芯焊料球110及接點212,如圖4所示。
在圖5A至圖5B中,根據一些實施例,對包封體214執行平坦化製程,以暴露出金屬芯焊料球110及接點212。可例如使用機械研磨(mechanical grinding)製程或化學機械拋光(chemical mechanical polishing,CMP)製程等來執行所述平坦化製程。所述平坦化製程移除包封體214的多餘部分,並暴露出金屬芯焊料球110及接點212。在一些情形中,金屬芯焊料球110及/或接點212的上部分可藉由所述平坦化製程被移除。例如,轉至圖5B,示出根據一些實施例在已執行平坦化製程之後電子裝置100的放大視圖。如圖5B所示,平坦化製程已移除金屬芯焊料球110的金屬芯112之上的焊料層114的一部分,且亦已移除金屬芯焊料球110的金屬芯112的上部分。在平坦化製程之後,金屬芯焊料球110可具有近似平整的暴露表面。電子裝置100的一些或全部金屬芯焊料球110可具有齊平的表面,且一些或全部金屬芯焊料球110可具有與包封體214的表面及/或接點212的暴露表面齊平的表面(圖5A所示)。在一些情形中,在平坦化製程之後,金屬芯112的暴露表面可具有在約10微米與約300微米之間的寬度W1。在一些情形中,金屬芯112的暴露表面可為近似圓形的形狀,且寬度W1對應於直徑。如圖5B所示,金屬芯焊料球110的金屬芯112使得能夠使用包封及平坦化製程來為隨後形成的與電子裝置100的電性連接(例如圖6所示的重佈線結構220)形成相對均勻及平坦的導電表面。如此一來,使用金屬芯焊料球110以此種方式形成導電表面可改善與電子裝置100的電性連接的可靠性、降低所述電性連接的電阻並改善所述電性連接的良率。
轉至圖6,根據一些實施例,在電子裝置100、半導體裝置210及包封體214之上形成重佈線結構220。重佈線結構220與電子裝置100的金屬芯焊料球110及半導體裝置210的接點212進行電性連接。所示的重佈線結構220包括絕緣層222A至222F(為了清楚起見,並未標示所有絕緣層222A至222F)且包括重佈線層224A至224F(為了清楚起見,並未標示所有重佈線層224A至224F)。在其他實施例中,可在重佈線結構220中形成與圖6所示者不同數目的絕緣層或重佈線層。例如,在一些實施例中,重佈線結構220可包括約1至約15個絕緣層或重佈線層或者另一數目的絕緣層或重佈線層。在一些實施例中,重佈線結構220可例如是扇出型結構。
仍參照圖6,在電子裝置100、半導體裝置210及包封體214之上形成絕緣層222A。絕緣層222A可由一或多種適合的介電材料(例如氧化物(例如氧化矽)、氮化物(例如氮化矽)、聚合物材料、聚醯亞胺材料、低介電常數(low-k)介電材料、模塑材料、另一介電材料等或其組合)製成。絕緣層222A可藉由例如旋轉塗佈(spin-coating)、疊層、化學氣相沈積(chemical vapor deposition,CVD)等或其組合等製程形成。絕緣層222A可具有在約1微米與約50微米之間(例如約5微米)的厚度,但可使用任何適合的厚度。可使用適合的微影遮罩(photolithographic mask)及蝕刻製程(etching process)向絕緣層222A中形成開口。例如,可在絕緣層222A之上形成光阻並將所述光阻圖案化,且利用一或多個蝕刻製程(例如,濕式蝕刻製程或乾式蝕刻製程)來移除絕緣層222A的部分。在一些實施例中,絕緣層222A由感光性聚合物(例如PBO、聚醯亞胺、苯並環丁烯(benzocyclobuten,BCB)等)形成,可使用微影遮罩及蝕刻製程在絕緣層222A中直接圖案化出開口。絕緣層222A中的開口可暴露出電子裝置100的金屬芯焊料球110及半導體裝置210的接點212。
然後,在絕緣層222A之上形成重佈線層224A。重佈線層224A可為經圖案化的導電層(例如金屬化圖案),其包括在絕緣層222A的主表面上並沿著所述主表面延伸的線部分(亦稱為導電線)。重佈線層224A更包括延伸穿過絕緣層222A的通孔部分(亦稱為導電通孔),以實體地且電性耦合電子裝置100及半導體裝置210。在實施例中,重佈線層224A可藉由首先形成晶種層(未示出)來形成。在一些實施例中,晶種層是金屬層,其可為單個層或包括由不同材料形成的多個子層的複合層(composite layer)。在一些實施例中,晶種層包括鈦層及所述鈦層之上的銅層。晶種層可使用適合的形成製程(例如物理氣相沈積(physical vapor deposition,PVD)、CVD、濺鍍(sputtering)等)來形成。在絕緣層222A之上以及由絕緣層222A中的開口暴露出的電子裝置100的金屬芯焊料球110及半導體裝置210的接點212之上形成晶種層。然後可形成光阻(亦未示出)以覆蓋晶種層,且然後將所述光阻圖案化以暴露出晶種層的位於隨後將形成重佈線層224A之處的那些部分。一旦光阻已被形成及圖案化,便可在晶種層上形成導電材料。所述導電材料可為例如銅、鈦、鎢、鋁、另一金屬等或其組合等的材料。所述導電材料可藉由例如電鍍(electroplating)、無電鍍覆(electroless plating)等沈積製程形成。然而,儘管所論述的材料及方法適合於形成導電材料,但該些僅為實例。作為另一選擇,可使用任何其他適合的材料或任何其他適合的形成製程(例如CVD或PVD)來形成重佈線層224A。一旦已形成導電材料,便可藉由適合的移除製程(例如灰化製程(ashing process)或化學剝除製程(chemical stripping process),例如使用氧電漿等)來移除光阻。另外,在移除光阻之後,可例如藉由適合的濕式蝕刻製程或乾式蝕刻製程來移除晶種層的被光阻覆蓋的那些部分,所述濕式蝕刻製程或乾式蝕刻製程可使用所述導電材料作為蝕刻遮罩。晶種層的剩餘部分及導電材料形成重佈線層224A。在一些實施例中,重佈線層224A的在絕緣層222A之上延伸的部分可具有在約1微米與約25微米之間的厚度,但可使用任何適合的厚度。如此一來,重佈線層224A可形成與電子裝置100及半導體裝置210的電性連接。在一些情形中,當重佈線層224A由銅或銅合金製成時,在金屬芯焊料球110中使用由銅或銅合金形成的金屬芯112可改善電子裝置100與重佈線結構220之間的電性連接的效能及可靠性。例如,在金屬芯焊料球110與重佈線層224A之間形成的銅-銅結合可較例如銅與焊料材料之間的結合更導電且對熱問題更不敏感。
然後,可在重佈線層224A及絕緣層222A之上形成附加的絕緣層222B至222F及重佈線層224B至224F,以在重佈線結構220內提供附加的佈線(routing)以及電性連接。絕緣層222B至222F及重佈線層224B至224F可形成為交替的層,且可使用與用於絕緣層222A或重佈線層224A的製程及材料相似的製程及材料來形成。例如,可在重佈線層(例如,重佈線層224A)之上形成絕緣層(例如,絕緣層222B),且然後使用適合的微影遮罩及蝕刻製程穿過絕緣層形成開口以暴露出下伏重佈線層的部分。可在絕緣層之上形成晶種層,且在晶種層的部分上形成導電材料,而形成上覆重佈線層(例如,重佈線層224B)。可重複該些步驟以形成具有適合數目及配置的絕緣層及重佈線層的重佈線結構220。作為另一選擇,絕緣層222B至222F或重佈線層224B至224F可與絕緣層222A或重佈線層224A不同地形成。在其他實施例中,重佈線結構220可以與本文所述者不同的製程形成。
轉至圖7,在重佈線結構220上形成外部連接件226。在一些實施例中,首先在重佈線結構220的最頂部重佈線層(例如,圖6中的重佈線層224F)的部分上形成凸塊下金屬化結構(UBM,未示出)。所述UBM可例如包括三層導電材料,例如鈦層、銅層及鎳層。然而,可使用適合於形成UBM的其他材料及層佈置,例如鉻/鉻銅合金/銅/金的佈置、鈦/鈦鎢/銅的佈置或銅/鎳/金的佈置。可用於UBM的任何適合的材料或材料層均完全被設想包含於本申請案的範圍內。可藉由在重佈線結構220之上形成UBM的每一層來形成UBM。每一層的形成可使用鍍覆製程(例如電鍍或無電鍍覆)來執行,但作為另一選擇,視所需的材料而定,可使用其他形成製程,例如濺鍍、蒸鍍(evaporation)或電漿增強化學氣相沈積(plasma enhanced chemical vapor deposition,PECVD)製程。一旦已形成所需的層,然後可藉由適合的微影遮蔽及蝕刻製程移除所述層的部分,以移除非所需的材料並使UBM呈所需的形狀,例如圓形、八邊形、正方形或矩形,但作為另一選擇,可形成任何所需的形狀。在一些實施例中,作為重佈線結構220的形成的一部分,在最頂部重佈線層之上形成UBM,此可包括使用用於形成最頂部重佈線層的相同微影步驟。例如,可在最頂部重佈線層之上沈積UBM的各層,且然後在同一製程中移除最頂部重佈線層及UBM的多餘材料。在一些實施例中,UBM可為重佈線結構220的最頂部重佈線層的一部分,且可例如延伸穿過重佈線結構220的最頂部絕緣層(例如,圖6中的絕緣層222F)。
在圖7中,然後,在重佈線結構220的最頂部重佈線層上(例如,在重佈線層224F上或在UBM(若存在的話)上)形成外部連接件226。外部連接件226可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、微凸塊、由化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。外部連接件226可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中,藉由利用蒸鍍、電鍍、印刷、焊料轉移、植球等首先形成焊料層來形成外部連接件226。一旦已在結構上形成焊料層,便可執行回焊,以將材料成形為所需的凸塊形狀。在另一實施例中,外部連接件226包括藉由濺鍍、印刷、電鍍、無電鍍覆、CVD等形成的金屬柱(例如銅柱)。金屬柱可為無焊料的,且具有實質上垂直的側壁。在一些實施例中,在金屬柱的頂部上形成金屬頂蓋層(metal cap layer)。金屬頂蓋層可包含鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金等或其組合,且可藉由鍍覆製程形成。在一些實施例中,外部連接件226的間距可在約150微米與約1250微米之間。
仍參照圖7,將一或多個積體裝置228貼合至重佈線結構220的最頂部重佈線層(或UBM,若存在的話),以與重佈線結構220進行電性連接。積體裝置228可例如是半導體裝置、或者包括一或多個被動裝置(例如電容器、電阻器、電感器等)在內的其他裝置。積體裝置228可例如是積體被動裝置(IPD)。貼合至重佈線結構220的各積體裝置228可為相似的裝置或者可為不同類型的裝置。圖7示出放置了二個積體裝置228,但在其他實施例中,可貼合更多或更少的積體裝置228。在其他實施例中,可在形成外部連接件226之前貼合積體裝置228。可例如藉由以下方式來貼合積體裝置228:將積體裝置228的連接件(例如,導電凸塊或接墊)(例如焊料球(未示出))依序浸入焊劑中,且然後使用拾放工具(pick-and-place tool)以將積體裝置228的連接件與重佈線結構220的對應區域實體地對齊。在一些情形中,可執行回焊製程來結合積體裝置228的連接件。在一些情形中,可對積體裝置228及外部連接件226二者執行回焊製程。
在一些實施例中,在每一積體裝置228與重佈線結構220之間形成底部填充膠(underfill)230,進而包圍積體裝置228的連接件。底部填充膠230可減小應力並保護接點(joint)免受由回焊製程造成的損壞。底部填充膠230可在積體裝置228被貼合之後藉由毛細流動製程(capillary flow process)形成,或者可在積體裝置228被貼合之前藉由適合的沈積方法形成。在其中使用焊劑來貼合積體裝置228的一些實施例中,焊劑可充當底部填充膠。
轉至圖8,根據一些實施例,剝離載體基底202,以將載體基底202自電子裝置100、半導體裝置210及包封體214分離(或「剝離」)。如此一來,可藉由使用金屬芯焊料球110結合電子裝置100來形成封裝結構200,此可改善裝置效能及良率。在一些實施例中,剝離包括將光(例如雷射光或UV光)投射於釋放層204上,使得釋放層204在光的熱量下分解,且載體基底202可被移除。在一些實施例中,多個封裝結構200形成於載體基底202上,並被單體化以形成單獨的封裝結構200。在一些實施例中,可例如使用熱黏合劑將可選的蓋體(lid)232貼合至封裝結構200。蓋體232可用以利於熱量耗散並保護封裝結構200,且可由適合的材料(例如金屬、半導體材料、介電材料或其組合)形成。
圖9A及圖9B至圖12示出根據一些實施例形成封裝體400(參見圖12)的中間步驟的剖視圖。封裝體400包括圖9A所示的封裝結構200,其可與參照圖7所述的封裝結構200(例如,在剝離載體基底202之前)相似。例如,圖9A所示的封裝結構200包括使用金屬芯焊料球110連接的電子裝置100。圖9A所示的封裝結構200貼合至內連結構300(參見圖9B),以形成封裝體400。內連結構300為封裝結構200提供附加佈線及穩定性。例如,內連結構300可減少封裝結構200的翹曲,尤其是對於具有大面積(例如,大於約90平方毫米)的封裝結構200。在一些實施例中,內連結構300可包括與佈線層(例如,圖9B中的佈線層308A至308B或309A至309B)一起形成的電源平面或接地平面,可為提供給封裝結構200的電力提供附加穩定性,且可提供改善的電源/接地同步。如此一來,內連結構300可為封裝體400中的封裝結構200提供實體及操作上的益處。
轉至圖9B,示出根據一些實施例的內連結構300。在一些實施例中,內連結構300可例如是中介層(interposer)或「半成品基底(semi-finished substrate)」,且可無主動裝置。在一些實施例中,內連結構可包括形成於芯基底302上的佈線層。芯基底302可包含例如以下材料:味之素構成膜(Ajinomoto build-up film,ABF)、預浸漬複合纖維(預浸體(prepreg))材料、環氧樹脂、模塑化合物、環氧模塑化合物、玻璃纖維強化(fiberglass-reinforced)樹脂材料、印刷電路板(printed circuit board,PCB)材料、二氧化矽填料、聚合物材料、聚醯亞胺材料、紙、玻璃纖維、非織玻璃纖維布(non-woven glass fabric)、玻璃、陶瓷、其他疊層等或其組合。在一些實施例中,芯基底可為雙面敷銅層板(copper-clad laminate,CCL)基底等。芯基底302可具有在約30微米與約2000微米之間(例如約500微米或約1200微米)的厚度。
內連結構300可具有形成於芯基底302的每一側上的一或多個佈線結構312/313以及延伸穿過芯基底302的穿孔(through via)310。佈線結構312/313及穿孔310提供附加的電性佈線及內接。佈線結構312/313可包括一或多個佈線層308A至308B/309A至309B及一或多個介電層318/319。在一些實施例中,佈線層308A至308B/309A至309B及/或穿孔310可包括一或多層銅、鎳、鋁、其他導電材料等或其組合。在一些實施例中,介電層318/319可包含例如堆積(build-up)材料、ABF、預浸體材料、疊層材料、與以上針對芯基底302所述的材料相似的另一材料等或其組合等的材料。圖9B所示的內連結構300示出總共具有四個佈線層的二個佈線結構,但在其他實施例中,可在芯基底302的任一側上形成更多或更少的佈線層。
在一些實施例中,芯基底302中用於穿孔310的開口可填充有填料材料(filler material)311。填料材料311可為穿孔310的導電材料提供結構支撐及保護。在一些實施例中,填料材料311可為例如以下材料:模塑材料、環氧樹脂、環氧模塑化合物、樹脂、包含單體(monomer)或寡聚物(oligomer)的材料(例如丙烯酸酯化胺基甲酸酯(acrylated urethane)、橡膠改質的丙烯酸酯化環氧樹脂(rubber-modified acrylated epoxy resin)或多官能單體(multifunctional monomer))等或其組合。在一些實施例中,填料材料311可包括顏料或染料(例如,用於顏色)或改變流變性(rheology)、改善黏合力或影響填料材料311的其他性質的其他填料及添加劑。在一些實施例中,穿孔310的導電材料可完全填充穿孔310,而省略填料材料311。
在一些實施例中,內連結構300可包括形成於內連結構300的一或多個側之上的鈍化層307。鈍化層307可為例如氮化物、氧化物、聚醯亞胺、低溫聚醯亞胺、阻焊劑、其組合等材料。一旦形成,鈍化層307可被圖案化(例如,使用適合的微影及蝕刻製程),以暴露出佈線結構312/313的佈線層308A至308B/309A至309B的部分。
圖10示出根據一些實施例將內連結構300放置成與封裝結構200電性連接。圖10示出單個內連結構300結合至單個封裝結構200,但在一些實施例中,多個內連結構300可結合至形成於載體基底202上的多個封裝結構,且隨後被單體化以形成多個單獨的封裝體400。在實施例中,使用例如拾放製程將內連結構300放置成與封裝結構200上的外部連接件226實體接觸。內連結構300可被放置成使得佈線結構(例如,佈線結構313)的最頂部佈線層的暴露區域與封裝結構200的對應外部連接件226對齊。一旦實體接觸,便可利用回焊製程將封裝結構200的外部連接件226結合至內連結構300。在一些實施例中,作為在封裝結構200上形成外部連接件226的代替或補充,在內連結構300上形成外部連接件。在一些實施例中,在封裝結構200上未形成外部連接件226,且使用例如熱壓結合技術(thermocompression bonding technique)等直接結合技術將內連結構300結合至封裝結構200。
在圖11中,沿著內連結構300的側壁以及在內連結構300與封裝結構200之間的間隙中沈積底部填充膠320。底部填充膠320可為例如模塑化合物、環氧樹脂、底部填充膠、模塑底部填充膠(molding underfill,MUF)、樹脂等材料。底部填充膠320可保護外部連接件226且為封裝結構200提供結構支撐。在一些實施例中,底部填充膠320可在沈積之後被固化。在一些實施例中,底部填充膠320可在沈積之後被薄化。所述薄化可例如使用機械研磨或CMP製程執行。在一些實施例中,可在佈線結構312之上沈積底部填充膠320,且所述薄化可暴露出佈線結構312的最頂部佈線層。
在圖12中,在內連結構300之上形成外部連接件322且外部連接件322電性連接至內連結構300,而形成封裝體400。外部連接件322可形成於佈線結構312的最頂部佈線層的暴露部分上。在一些實施例中,在佈線結構312上形成UBM,且在UBM之上形成外部連接件322。在一些實施例中,首先在佈線結構312之上形成保護層(未示出)。可在UBM(若存在的話)之上形成保護層。保護層可由例如以下一或多種適合的介電材料形成:聚苯并[口咢]唑(PBO)、聚合物材料、聚醯亞胺材料、聚醯亞胺衍生物、氧化物、氮化物等或其組合。可在保護層中形成開口以暴露出佈線結構312(其可包括UBM(若存在的話))的部分。在佈線結構312的暴露部分之上形成外部連接件322,且外部連接件322與佈線結構312進行電性連接。外部連接件322可例如為接觸凸塊或焊料球,但可利用任何適合類型的連接件。在其中外部連接件322是接觸凸塊的實施例中,外部連接件322可包含例如錫等材料或例如銀、無鉛錫或銅等其他適合的材料。在其中外部連接件322是錫焊料凸塊的實施例中,可藉由首先使用例如蒸鍍、電鍍、印刷、焊料轉移、植球等此種技術形成錫層來形成外部連接件322。一旦在所述結構上形成錫層,便可執行回焊以將所述材料成形為外部連接件322所需的凸塊形狀。在一些實施例中,外部連接件322可具有在約150微米與約1250微米之間的間距。在一些實施例中,外部連接件322可與以上參照圖7所述的外部連接件226相似。在形成外部連接件226之後,可以與圖8中所述的剝離相似的方式執行對載體基底202的剝離。
亦可包括其他特徵及製程。例如,可包括測試結構以幫助對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或基底上形成的測試接墊(test pad),以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外,本文中所揭露的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法結合使用以提高良率並降低成本。
藉由利用本文中所述的實施例,裝置封裝體的效能可得到改善,裝置封裝體的成本可減少,且裝置封裝體的可靠性可得到改善。本文中所述的實施例的不同特徵可進行組合以達成該些及其他益處。在一些情形中,使用所述的金屬芯焊料球可改善電性連接的傳導及可靠性,且在高速操作期間能夠具有更少的訊號損耗。在一些情形中,本文中所述的技術可在具有其他典型製作製程的製程流程中執行,且因此可對現有製程增加很少或不增加附加成本。另外,使用所述的金屬芯焊料球可使得良率得到改善,尤其是對於具有較大面積的裝置封裝體。在一些情形中,使用本文中所述的金屬芯焊料球可較例如覆晶技術(flip-chip technique)等的其他技術具有更低成本。本文中所述的技術及實施例可應用於其他類型或配置的封裝體,例如晶圓上晶片(chip-on wafer,CoW)結構、系統級封裝(system-in-package,SiP)結構、積體扇出型層疊式封裝(integrated fan-out package-on-package,InFO-PoP)結構等。本文中所述的技術亦可達成「組件優先(component-first)」製程,在此製程中,組件(例如,裝置或晶片)是在形成重佈線結構或其他連接結構之前放置。
在實施例中,一種封裝結構製造方法包括:將金屬芯焊料球放置於第一半導體裝置的導電接墊上,其中所述金屬芯焊料球包括由焊料材料包圍的金屬芯;以及形成裝置結構,形成所述裝置結構包括:將所述第一半導體裝置放置於載體基底上;用包封體包封所述第一半導體裝置,其中所述包封體覆蓋所述金屬芯焊料球;對所述包封體執行平坦化製程,其中所述平坦化製程暴露出所述金屬芯焊料球;以及在所述包封體及所述第一半導體裝置之上形成重佈線結構,其中所述重佈線結構電性連接至所述金屬芯焊料球。在實施例中,所述方法包括在將所述金屬芯焊料球放置於所述導電接墊上之後,對所述金屬芯焊料球執行回焊製程。在實施例中,所述方法包括將第二半導體裝置放置於所述載體基底上。在實施例中,所述第二半導體裝置包括金屬芯焊料球,其中所述重佈線結構電性連接至所述第二半導體裝置的所述金屬芯焊料球。在實施例中,所述第二半導體裝置包括焊料凸塊,其中所述重佈線結構電性連接至所述焊料凸塊。在實施例中,所述平坦化製程移除所述金屬芯焊料球的上部分。在實施例中,在執行所述平坦化製程之後,每一所述金屬芯焊料球具有與所述包封體的表面齊平的表面。在實施例中,所述金屬芯包含銅。在實施例中,所述方法包括將內連結構貼合至所述重佈線結構。在實施例中,所述方法包括將蓋體貼合至所述裝置結構,所述蓋體在所述第一半導體裝置及所述包封體之上延伸。
在實施例中,一種封裝結構包括:多個半導體裝置,在載體基底上,其中每一所述半導體裝置包括設置於所述半導體裝置的與所述載體基底相對的一側上的金屬芯焊料球;模塑材料,在所述多個半導體裝置之上,其中所述多個半導體裝置中的每一者由所述模塑材料分隔開,其中每一所述半導體裝置的所述金屬芯焊料球具有與所述模塑材料齊平的平坦表面;重佈線結構,在所述多個半導體裝置之上,其中所述重佈線結構電性連接至所述多個半導體裝置中的每一者,其中所述重佈線結構電性連接至每一所述半導體裝置的所述金屬芯焊料球;以及多個導電連接件,在所述重佈線結構上,其中所述導電連接件電性連接至所述重佈線結構。在實施例中,所述金屬芯焊料球包括包含銅的芯及所述芯之上的焊料層。在實施例中,所述裝置包括貼合至所述重佈線結構的積體被動裝置。在實施例中,所述裝置包括貼合至所述導電連接件的內連結構。在實施例中,所述內連結構包括芯基底及多個佈線層。在實施例中,每一所述金屬芯焊料球的所述平坦表面具有在10微米與300微米之間的直徑。
在實施例中,一種封裝體包括:裝置結構,包括電性連接至至少一個第一半導體裝置的重佈線結構,其中所述至少一個第一半導體裝置藉由多個金屬芯焊料球電性連接至所述重佈線結構,其中所述多個金屬芯焊料球中的每一者包括至少部分地由焊料材料覆蓋的金屬球,且其中所述重佈線結構及所述至少一個第一半導體裝置由模塑材料包圍。在實施例中,所述封裝體包括電性連接至所述重佈線結構的內連結構及在所述重佈線結構與所述內連結構之間延伸的底部填充材料,所述內連結構包括形成於基底之上的佈線結構。在實施例中,所述至少一個第一半導體裝置包括記憶體晶粒。在實施例中,所述裝置結構更包括至少一個第二半導體裝置,其中所述重佈線結構藉由焊料凸塊電性連接至所述至少一個第二半導體裝置。
以上概述了若干實施例的特徵,以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應理解,他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到,該些等效構造並不背離本發明的精神及範圍,而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
100:電子裝置
104、307:鈍化層
106:導電連接件
110:金屬芯焊料球
112:金屬芯
114:焊料層
200:封裝結構
202:載體基底
204:釋放層
210:半導體裝置
212:接點
214:包封體
220:重佈線結構
222A、222C、222E、222F:絕緣層
224A、224B、224C、224E、224F:重佈線層
226、322:外部連接件
228:積體裝置
230、320:底部填充膠
232:蓋體
300:內連結構
302:芯基底
308A、308B、309A、309B:佈線層
310:穿孔
311:填料材料
312、313:佈線結構
318、319:介電層
400:封裝體
W1:寬度
結合附圖閱讀以下詳細說明,會最佳地理解本發明的各個態樣。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的電子裝置的剖視圖。
圖2示出根據一些實施例放置於電子裝置上的金屬芯焊料球(metal-core solder ball)的剖視圖。
圖3至圖8示出根據一些實施例形成封裝結構的中間步驟的剖視圖。
圖9A示出根據一些實施例的封裝結構的剖視圖。
圖9B示出根據一些實施例的內連結構(interconnect structure)的剖視圖。
圖10至圖12示出根據一些實施例形成封裝體的中間步驟的剖視圖。
圖13A及圖13B示出根據一些實施例在不同類型的載體基底上形成封裝結構的中間步驟。
100:電子裝置
110:金屬芯焊料球
200:封裝結構
210:半導體裝置
214:包封體
220:重佈線結構
226:外部連接件
228:積體裝置
232:蓋體
Claims (20)
- 一種封裝結構製造方法,包括: 將金屬芯焊料球放置於第一半導體裝置的導電接墊上,其中所述金屬芯焊料球包括由焊料材料包圍的金屬芯;以及 形成裝置結構,形成所述裝置結構包括: 將所述第一半導體裝置放置於載體基底上; 用包封體包封所述第一半導體裝置,其中所述包封體覆蓋所述金屬芯焊料球; 對所述包封體執行平坦化製程,其中所述平坦化製程暴露出所述金屬芯焊料球;以及 在所述包封體及所述第一半導體裝置之上形成重佈線結構,其中所述重佈線結構電性連接至所述金屬芯焊料球。
- 如申請專利範圍第1項所述的封裝結構製造方法,更包括在將所述金屬芯焊料球放置於所述導電接墊上之後,對所述金屬芯焊料球執行回焊製程。
- 如申請專利範圍第1項所述的封裝結構製造方法,更包括將第二半導體裝置放置於所述載體基底上。
- 如申請專利範圍第3項所述的封裝結構製造方法,其中所述第二半導體裝置包括金屬芯焊料球,其中所述重佈線結構電性連接至所述第二半導體裝置的所述金屬芯焊料球。
- 如申請專利範圍第3項所述的封裝結構製造方法,其中所述第二半導體裝置包括焊料凸塊,其中所述重佈線結構電性連接至所述焊料凸塊。
- 如申請專利範圍第1項所述的封裝結構製造方法,其中所述平坦化製程移除所述金屬芯焊料球的上部分。
- 如申請專利範圍第6項所述的封裝結構製造方法,其中在執行所述平坦化製程之後,每一所述金屬芯焊料球具有與所述包封體的表面齊平的表面。
- 如申請專利範圍第1項所述的封裝結構製造方法,其中所述金屬芯包含銅。
- 如申請專利範圍第1項所述的封裝結構製造方法,更包括將內連結構貼合至所述重佈線結構。
- 如申請專利範圍第1項所述的方法,更包括將蓋體貼合至所述裝置結構,所述蓋體在所述第一半導體裝置及所述包封體之上延伸。
- 一種封裝結構,包括: 多個半導體裝置,在載體基底上,其中每一所述半導體裝置包括設置於所述半導體裝置的與所述載體基底相對的一側上的金屬芯焊料球; 模塑材料,在所述多個半導體裝置之上,其中所述多個半導體裝置中的每一者由所述模塑材料分隔開,其中每一所述半導體裝置的所述金屬芯焊料球具有與所述模塑材料齊平的平坦表面; 重佈線結構,在所述多個半導體裝置之上,其中所述重佈線結構電性連接至所述多個半導體裝置中的每一者,其中所述重佈線結構電性連接至每一所述半導體裝置的所述金屬芯焊料球;以及 多個導電連接件,在所述重佈線結構上,其中所述導電連接件電性連接至所述重佈線結構。
- 如申請專利範圍第11項所述的封裝結構,其中所述金屬芯焊料球包括包含銅的芯及所述芯之上的焊料層。
- 如申請專利範圍第11項所述的封裝結構,更包括貼合至所述重佈線結構的積體被動裝置。
- 如申請專利範圍第11項所述的封裝結構,更包括貼合至所述多個導電連接件的內連結構。
- 如申請專利範圍第14項所述的封裝結構,其中所述內連結構包括芯基底及多個佈線層。
- 如申請專利範圍第11項所述的封裝結構,其中每一所述金屬芯焊料球的所述平坦表面具有在10微米與300微米之間的直徑。
- 一種封裝體,包括: 裝置結構,包括電性連接至至少一個第一半導體裝置的重佈線結構,其中所述至少一個第一半導體裝置藉由多個金屬芯焊料球電性連接至所述重佈線結構,其中所述多個金屬芯焊料球中的每一者包括至少部分地由焊料材料覆蓋的金屬球,且其中所述重佈線結構及所述至少一個第一半導體裝置由模塑材料包圍。
- 如申請專利範圍第17項所述的封裝體,更包括電性連接至所述重佈線結構的內連結構及在所述重佈線結構與所述內連結構之間延伸的底部填充材料,所述內連結構包括形成於基底之上的佈線結構。
- 如申請專利範圍第17項所述的封裝體,其中所述至少一個第一半導體裝置包括記憶體晶粒。
- 如申請專利範圍第17項所述的封裝體,其中所述裝置結構更包括至少一個第二半導體裝置,其中所述重佈線結構藉由焊料凸塊電性連接至所述至少一個第二半導體裝置。
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US11735564B2 (en) * | 2019-12-04 | 2023-08-22 | Sj Semiconductor (Jiangyin) Corporation | Three-dimensional chip packaging structure and method thereof |
US11894318B2 (en) * | 2020-05-29 | 2024-02-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacture |
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Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001319994A (ja) | 2000-02-29 | 2001-11-16 | Allied Material Corp | 半導体パッケージとその製造方法 |
JP2007103737A (ja) * | 2005-10-05 | 2007-04-19 | Sharp Corp | 半導体装置 |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
KR20130050406A (ko) | 2011-11-07 | 2013-05-16 | 오수미 | 머지 모드에서의 움직임 정보 생성 방법 |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9257333B2 (en) | 2013-03-11 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
US9263839B2 (en) | 2012-12-28 | 2016-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved fine pitch joint |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US9196532B2 (en) | 2012-06-21 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit packages and methods for forming the same |
US9443783B2 (en) | 2012-06-27 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC stacking device and method of manufacture |
US9275924B2 (en) | 2012-08-14 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package having a recess filled with a molding compound |
KR20140070057A (ko) * | 2012-11-30 | 2014-06-10 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9196559B2 (en) | 2013-03-08 | 2015-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Directly sawing wafers covered with liquid molding compound |
US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
US8987922B2 (en) | 2013-03-11 | 2015-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for wafer level packaging |
US9275925B2 (en) | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9425126B2 (en) | 2014-05-29 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for chip-on-wafer-on-substrate |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
US9633934B2 (en) * | 2014-11-26 | 2017-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semicondutor device and method of manufacture |
US9461018B1 (en) | 2015-04-17 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out PoP structure with inconsecutive polymer layer |
US9666502B2 (en) | 2015-04-17 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Discrete polymer in fan-out packages |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
KR101830938B1 (ko) | 2015-11-30 | 2018-04-04 | 하나 마이크론(주) | 메탈 코어 솔더 볼 인터커넥터 팬-아웃 웨이퍼 레벨 패키지 |
WO2017095094A2 (ko) | 2015-11-30 | 2017-06-08 | 하나마이크론(주) | 메탈 코어 솔더 볼 인터커넥터 팬-아웃 웨이퍼 레벨 패키지 및 그 제조 방법 |
TWI652778B (zh) | 2016-01-27 | 2019-03-01 | 艾馬克科技公司 | 半導體封裝以及其製造方法 |
US10297551B2 (en) * | 2016-08-12 | 2019-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package |
US10515899B2 (en) | 2016-10-03 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure with bump |
US10153222B2 (en) | 2016-11-14 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming the same |
US10388637B2 (en) | 2016-12-07 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a 3D interposer system-in-package module |
US10770405B2 (en) | 2017-05-31 | 2020-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal interface material having different thicknesses in packages |
US10727198B2 (en) | 2017-06-30 | 2020-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method manufacturing the same |
US10224301B2 (en) * | 2017-07-05 | 2019-03-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
JP7014535B2 (ja) * | 2017-07-07 | 2022-02-01 | 新光電気工業株式会社 | 導電性ボール及び電子装置とそれらの製造方法 |
US10522526B2 (en) * | 2017-07-28 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | LTHC as charging barrier in InFO package formation |
US10522436B2 (en) * | 2017-11-15 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Planarization of semiconductor packages and structures resulting therefrom |
US11328969B2 (en) * | 2017-11-16 | 2022-05-10 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor device and manufacturing method thereof |
CN110299329A (zh) | 2018-03-21 | 2019-10-01 | 华为技术有限公司 | 一种封装结构及其制作方法、电子设备 |
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US20210118835A1 (en) | 2021-04-22 |
US11145614B2 (en) | 2021-10-12 |
KR102386542B1 (ko) | 2022-04-14 |
CN112687628A (zh) | 2021-04-20 |
KR20210047225A (ko) | 2021-04-29 |
TWI785296B (zh) | 2022-12-01 |
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