CN112530818A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN112530818A CN112530818A CN201911337793.5A CN201911337793A CN112530818A CN 112530818 A CN112530818 A CN 112530818A CN 201911337793 A CN201911337793 A CN 201911337793A CN 112530818 A CN112530818 A CN 112530818A
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Abstract
本发明描述集成扇出装置、晶圆级封装以及其制造方法。管芯附接衬垫和调平膜用以将多个异质半导体管芯附接到衬底以在第一位准处对准半导体管芯的外部触点。调平膜还可在包封体的沉积期间使用以至少部分地填充半导体管芯之间的间隙。一旦将调平膜去除,便在半导体管芯上方和由调平膜在包封期间留下的包封体的凹部内形成保护层。在保护层上方形成重布线层和外部接点以形成集成扇出装置,且可将中介物附接到重布线层以形成晶圆级封装。
Description
技术领域
本发明的实施例是有关于一种半导体装置的制造方法。
背景技术
半导体行业通过使最小特征大小不断降低而持续提高各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度(integration density),这实现将更多组件,因而将更多功能集成到给定区域中。具有高功能性的集成电路需要许多输入/输出衬垫。然而,在小型化至关重要的应用中,可能需要较小封装。
集成扇出(Integrated Fan Out,InFO)封装技术变得越来越普及,尤其在与晶圆级封装(Wafer Level Packaging,WLP)技术组合时,在所述晶圆级封装技术中,集成电路封装于通常包含重布线层(redistribution layer,RDL)或用以对封装的接触衬垫进行扇出布线的后钝化内连线的封装中,以使得可以比集成电路的接触衬垫更大的间距形成电触点。这类所得封装结构提供具有相对较低成本的高功能密度和高性能封装。晶圆制作工艺(例如背侧研磨、化学机械平面化(chemical mechanical planarization,CMP)、退火(annealing)以及类似工艺)向所制作封装的材料和结构引入应力(例如晶圆翘曲、热循环以及类似应力)。这些应力可导致缺陷,例如模制化合物和重布线层的微开裂,从而导致较低生产良率、材料浪费、较高生产成本以及增加的生产时间。
发明内容
本发明实施例提供一种半导体装置的制造方法,包括以下步骤。使用第一管芯附接衬垫将第一半导体装置附接到衬底。使用第二管芯附接衬垫将第二半导体装置附接到衬底。使用包封体填充第一管芯附接衬垫与第二管芯附接衬垫之间的间隙且至少部分地填充第一半导体装置与第二半导体装置之间的间隙。在包封体上方以及第一半导体装置和第二半导体装置上方沉积保护涂层,沉积保护涂层填充第一半导体装置与第二半导体装置之间的间隙的剩余部分。以及,在保护涂层上方形成重布线结构。
本发明实施例提供一种半导体装置的制造方法,包括以下步骤。在衬底上形成第一管芯附接衬垫和与第一管芯附接衬垫分隔的第二管芯附接衬垫。在第一管芯附接衬垫上放置第一半导体管芯,且在第二管芯附接衬垫上放置第二半导体管芯。在第一半导体管芯和第二半导体管芯上方放置调平膜。使用调平膜将第一半导体管芯和第二半导体管芯调平到第一位准。在衬底上方沉积模制化合物且至少部分地填充在第一半导体管芯与第二半导体管芯之间从衬底到调平膜的管芯间隙,调平膜与模制化合物之间的界面处于或低于第一半导体管芯和第二半导体管芯的拐角区域。去除调平膜。在模制化合物以及第一半导体管芯和第二半导体管芯上方沉积介电层。以及在介电层上方形成重布线层。
本发明实施例提供一种半导体装置,包括第一半导体管芯、第二半导体管芯、包封体、保护层以及重布线结构。第一半导体管芯具有第一外部触点。第二半导体管芯具有第二外部触点,其中第一外部触点和第二外部触点安置于同一位准处。包封体至少部分地填充第一半导体管芯与第二半导体管芯之间的间隙。保护层位于包封体、第一半导体管芯以及第二半导体管芯上方,其中保护层与包封体之间的界面安置在第一半导体管芯与第二半导体管芯的侧壁之间。以及重布线结构位于保护层上方,其中重布线结构包括电耦合到第一外部触点中的至少一个的金属化物层。
附图说明
当结合附图阅读时,从以下详细描述最好地理解本公开的各方面。应注意,根据行业中的标准惯例,各种特征未按比例绘制。实际上,出于论述清楚起见,可任意增大或减小各种特征的尺寸。
图1A到图8示出根据一些实施例的形成集成扇出装置的中间步骤的横截面视图。
图9示出根据一些其它实施例的集成扇出装置的横截面视图。
图10A和图10B示出根据一些实施例的包括图9的集成扇出装置的晶圆级封装的横截面视图。
附图标号说明
100:集成扇出装置;
102:载体衬底;
103:管芯附接衬垫;
104A、104B、104C、104D、104E:半导体装置;
105:第一装置触点;
106:包封体;
107:第二装置触点;
111:调平膜;
113:平坦化工具;
120:保护涂层;
122:前侧重布线结构;
124、128、132、136:介电层;
126、130、134:金属化图案;
138:UBM;
150:导电接点;
206:第二包封体;
212:第一外部接点;
250:第一区域;
300:内连线结构;
302:核心衬底;
304:导电层;
306:导电通孔;
307:介电穿孔核心;
308:第一导电布线层;
309:第二导电布线层;
310、314:额外介电层;
311、315:其它额外布线层;
312、316:布线结构;
313、317:金属化通孔;
350:调平工艺;
400:包封工艺;
402:模制底填充料;
404:保护层;
406:第二外部接点;
438:第二UBM;
440:第二导电接点;
450:第二区域;
501:凹部;
700:研磨工艺;
701:保护接合部;
900:第二集成扇出装置;
1000:晶圆级封装;
1050:第三区域;
D1:第一距离;
dg1、dg2、dg3:管芯间隙;
dTh1:第一变形厚度;
dTh2:第二变形厚度;
dTh3:第三变形厚度;
H1:第一高度;
H2:第二高度;
H3:第三高度;
jrD1:接合凹部深度;
Lvl1:第一位准;
Lvl2:第二位准;
S1、S2、S3:大小;
sd1、sd2、sd3:密封深度;
Th1:第一厚度;
ThPM:厚度;
W1:第一宽度;
W2:第二宽度;
W3:第三宽度;
Δ1、Δ2、Δ3:悬突余量。
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例以简化本公开。当然,这些特定实例只是实例且并不意图为限制性的。举例来说,在以下描述中,第一特征在第二特征上方或第二特征上形成可包含第一特征与第二特征直接接触地形成的实施例,且还可包含可在第一特征与第二特征之间形成额外特征以使得第一特征与第二特征可不直接接触的实施例。另外,本公开可在各种实例中重复附图标记和/或字母。此重复是出于简单和清楚的目的,且本身并不指示所论述的各种实施例和/或配置之间的关系。
此外,为易于描述,可在本文中使用如“在…下方”、“在…下”、“下部”、“在…上方”、“上部”以及类似术语的空间相对术语来描述如图中所示出的一个元件或特征与另一(一些)元件或特征的关系。除了图中所描绘的定向以外,空间相对术语意图涵盖装置在使用或操作中的不同定向。设备可以其它方式定向(旋转90度或处于其它定向),且本文中所使用的空间相对描述词可同样相应地进行解释。
在本公开中,描述装置封装和其形成的各个方面。装置封装可以是例如系统级封装(system-in-package)。在一些实施例中,系统级封装可集成嵌入在使用PM涂层的模制化合物内的异质管芯以保护管芯间拐角(die-to-die corner)区域,从而降低由于晶圆翘曲和/或由于在加工(例如研磨、通过可靠性应力进行的拷打、多回焊(multi-reflow)、热循环(thermal cycling)以及类似加工)期间施加到晶圆的物理和热应力而传播到PM涂层的模制化合物内的开裂。根据一些实施例,重布线结构(例如扇出结构)可在PM涂层上方形成。如此,PM涂层防止细线开裂传播到重布线结构中。如此,PM涂层为装置封装提供刚性,且防止归因于在晶圆制作期间的翘曲和/或剥离的损坏。集成具有PM涂层的异质管芯的这类方法提供高制造可靠性,从而针对高性能系统级封装装置以相对较低的生产成本产生高良率。在一些实施例中,内连线结构可在核心衬底上形成,且随后附接到重布线结构。通过在重布线结构内而非内连线结构内形成更多布线,可改善装置封装的电性能,且可降低装置封装的总体制造成本。这类制造方法提供高制造可靠性,从而以相对较高的功能密度和低生产成本引起高性能封装结构的高良率。
图1A到图8示出根据一些实施例的形成集成扇出(InFO)装置(例如InFO装置100)的中间步骤的横截面视图。
现参考图1A,此处绘示了根据一些实施例的其上已放置有一或多个管芯附接衬垫103的载体衬底102。载体衬底102可包含例如硅类材料,如硅衬底(例如硅晶圆)、玻璃材料、氧化硅或其它材料,如氧化铝、塑料材料、有机材料、类似物或组合。载体衬底102可以是平面以便适应装置的附接。
在一些实施例中,管芯附接衬垫103可包括释放层(图中未示)以促进载体衬底102的后续剥离。管芯附接衬垫103可由聚合物类材料形成,所述材料可与载体衬底102一起从将在后续步骤中形成的上覆结构去除。根据一些实施例,管芯附接衬垫103可具有合适的大小和形状以用于附接相应上覆结构。在一些实施例中,管芯附接衬垫103包括粘着剂,所述粘着剂在加热时或在暴露于光下时失去其粘着特性(例如环氧类热释放材料(epoxy-basedthermal-release materials)、光热转换(Light-to-Heat-Conversion,LTHC)释放涂层、紫外(ultra-violet,UV)胶或类似物)。在其它实施例中,管芯附接衬垫103包括阻焊剂墨(solder resist ink)。管芯附接衬垫103可配制为液体并固化,可以是层压到载体衬底102上的层压膜,可以是喷墨印刷(ink jet printed)或网版印刷(screen printed)到载体衬底102上,或类似物。管芯附接衬垫103的顶部表面可经过调平,且可具有高度的共面性(co-planarity)。根据一些实施例,管芯附接衬垫103形成为约1微米与约50微米之间(如约5微米)的第一厚度Th1。
参考图2A和图2B,使用合适的工艺(如取放工艺)将半导体装置104A到半导体装置104C放置在载体衬底102上方的管芯附接衬垫103上。这些图中所示的半导体装置104A到半导体装置104C中的每一个可以是设计成用于预期目的的半导体装置,如存储器管芯(例如高带宽存储器(high bandwidth memory,HBM)堆叠、堆叠存储器管芯、DRAM管芯等)、逻辑管芯、中央处理单元(central processing unit,CPU)管芯、系统单芯片(system-on-a-chip,SoC)、类似物或其组合。半导体装置104A到半导体装置104C可视特定功能性需要而在其中包含集成电路装置,如晶体管、电容器、电感器、电阻器、金属化层、外部接点以及类似物。在一些实施例中,半导体装置104A到半导体装置104C包括超过一个相同类型的装置,或可包含不同装置。
在其中半导体装置104C是高带宽存储器(HBM)堆叠的实施例中,半导体装置104C可包括独立半导体管芯的堆叠。举例来说,独立半导体管芯的堆叠可以是全部堆叠在缓冲器管芯的顶部上的存储器管芯的堆叠(例如存储器立方体),所述缓冲器管芯可以是有助于对堆叠内的单个管芯进行控制和互连的控制器管芯。另外,一旦堆叠已形成,便可用包封体(未单独标记)包封所述堆叠。
图2A绘示根据一实施例的两组的三个半导体装置104A到半导体装置104C;然而,可将任何适当数量的半导体装置放置在载体衬底102上。根据一些实施例,半导体装置104A到半导体装置104C分别具有如第一大小S1、第二大小S2以及第三大小S3的不同大小,且可包括不同类型的外部触点。在一些实施例中,第一半导体装置(例如104A)与第二半导体装置(例如104B)分隔一第一管芯间隙(dg1),第二半导体装置(例如104B)与第三半导体装置(例如104C)分隔一第二管芯间隙(dg2),且第三半导体装置(例如104C)与第一半导体装置(例如104A)分隔一第三管芯间隙(dg3)。管芯间隙(dg1、dg2以及dg3)可等距或可以是不同距离。根据一些实施例,管芯间隙(dg1、dg2以及dg3)在约25微米与约500微米之间,如约75微米。然而,可使用任何合适的距离。
此外,管芯附接衬垫103形成为合适的尺寸,如分别对应于其所附接的半导体装置104A到半导体装置104C的大小(S1、S2以及S3)的第一宽度W1、第二宽度W2以及第三宽度W3。图2A进一步示出,管芯附接衬垫103是标定尺寸的,且半导体装置104A到半导体装置104C布置在管芯附接衬垫103上方且附接到所述管芯附接衬垫,以使得半导体装置104A到半导体装置104C分别在半导体装置104A到半导体装置104C的外部周界与其所附接的管芯附接衬垫103的外部周界之间具有悬突余量(overhang margins)(例如Δ1、Δ2、Δ3)。举例来说,第一半导体装置(例如104A)具有第一悬突余量(Δ1),第二半导体装置(例如104B)具有第二悬突余量(Δ2),且第三半导体装置(例如104C)具有第三悬突余量(Δ3)。根据一些实施例,第一悬突余量Δ1可在约2微米与约75微米之间,如约5微米,第二悬突余量Δ2可在约2微米与约75微米之间,如约5微米,且第三悬突余量Δ3可在约2微米与约75微米之间,如约5微米。然而,任何合适的距离可用于悬突余量。
图2B示出图2A中突出显示的第一区域250的放大视图。根据一些实施例,半导体装置104A到半导体装置104C可具有不同类型的外部触点,且可具有不同高度。举例来说,第一半导体装置和第三半导体装置(例如104A和104C)可具有包括焊料材料的外部触点(例如第一装置触点105的微凸块),且第二半导体装置(例如104B)可具有包括接触衬垫的外部触点(例如第二装置触点107),但半导体装置104A到半导体装置104C的外部触点可相同。作为另一实例,第一半导体装置(例如104A)可具有第一高度H1,第二半导体装置(例如104B)可具有与第一高度H1不同的第二高度H2,且第三半导体装置(例如104C)可具有与第一高度H1和第二高度H2不同的第三高度H3,但所述高度可相同。根据一些实施例,第一高度H1可在约695微米与约745微米之间,如约720微米,第二高度H2可在约700微米与约740微米之间,如约720微米,且第三高度H3可在约695微米与约745微米之间,如约720微米。然而,可利用任何合适的高度。
图3A和图3B示出调平工艺350,所述调平工艺使用平坦化工具113使半导体装置104A到半导体装置104C的第一装置触点105和第二装置触点107的顶部在第一位准Lvl1处对准,且进一步将半导体装置104A到半导体装置104C粘附到载体衬底102。根据一些实施例,平坦化工具113使用调平膜111(例如调平箔(leveling foil)),所述调平膜放置为与第一装置触点105和第二装置触点107以及半导体装置104A到半导体装置104C的上部表面接触。一旦放置调平膜111,便可在处于或高于管芯附接衬垫103的熔点的处理温度下进行调平工艺350,同时将向下力(由方向箭头350指示)施加到平坦化工具113以使管芯附接衬垫103变形,以使得半导体装置104A到半导体装置104C接合到衬底,且使半导体装置104A到半导体装置104C的第一装置触点105和第二装置触点107在载体衬底102上方第一距离D1处与第一位准Lvl1对准。根据一些实施例,处理温度在约50℃与约200℃之间,如约110℃,且第一位准Lvl1的第一距离D1在约735微米与约795微米之间,如约765微米。然而,可使用任何合适的距离。
归因于半导体装置104A到半导体装置104C的外部周界与管芯附接衬垫103的外部周界之间的悬突余量(例如图2A中的Δ1、Δ2、Δ3),几乎没有变形管芯附接衬垫103的材料延伸超过半导体装置104A到半导体装置104C的周界到达管芯间隙(dg1、dg2以及dg3)中。如此,在调平工艺350期间,并未因变形管芯附接衬垫103的过量材料延伸到管芯间隙(dg1、dg2以及dg3)中且干扰调平工艺350而发生墨突起(ink protrusion)和管芯移位(dieshifting)。图3A进一步示出在调平工艺350期间结构的第一区域250。
图3B示出图3A中突出显示的第一区域250的放大视图。根据一些实施例,归因于半导体装置104A到半导体装置104C的不同高度,管芯附接衬垫103在调平工艺350期间可变形为不同厚度。举例来说,附接第一半导体装置(例如104A)的管芯附接衬垫103可由第一厚度Th1变形为第一变形厚度dTh1,附接第二半导体装置(例如104B)的管芯附接衬垫103可由第一厚度Th1变形为与第一变形厚度dTh1不同的第二变形厚度dTh2,且附接第三半导体装置(例如104C)的管芯附接衬垫103可由第一厚度Th1变形为与第一变形厚度dTh1和第二变形厚度dTh2不同的第三变形厚度dTh3,但所述厚度也可相同。根据一些实施例,第一厚度dTh1可变形为约1微米与约50微米之间的厚度,如约5微米,第二厚度dTh2可变形为约1微米与约50微米之间的厚度,如约5微米,且第三厚度dTh3可变形为约1微米与约50微米之间的厚度,如约5微米。然而,任何合适的厚度可用于变形厚度。
通过将管芯附接衬垫103彼此分隔,半导体装置104A到半导体装置104C的高度可彼此解耦且单独操控,而不具有干扰其它半导体装置104A到半导体装置104C的间隔。
图4A到图4B示出根据一些实施例的使用包封体106的半导体装置104A到半导体装置104C的包封工艺400(由方向箭头指示)。一旦半导体装置104A到半导体装置104C对准,平坦化工具113便可用作例如用于转移模制技术中的模制装置(未单独绘示)的组件。调平膜111用以在半导体装置104A到半导体装置104C的上部表面和第一装置触点105以及第二装置触点107上方形成密封件。图4A到图4B进一步示出,由调平膜111形成的密封件还延伸到半导体管芯104A到半导体装置104C之间的管芯间隙(例如dg1、dg2、dg3)中。如此,调平膜111防止第一装置触点105和第二装置触点107在包封工艺400期间嵌入包封体106中。根据一些实施例,调平膜111延伸到管芯间隙(例如dg1、dg2、dg3)中达到低于第一位准Lvl1的密封深度(例如sd1、sd2以及sd3)。密封深度可以是相同深度或可以是不同深度。根据一些实施例,密封深度(例如sd1、sd2、sd3)是范围介于约30微米与约150微米之间的深度,如约50微米。
一旦将第一装置触点105和第二装置触点107密封,便可通过转移模制(transfermolding)、压缩模制(compression molding)或类似模制来施加包封体106。包封体106在载体衬底102上方和半导体管芯104A到半导体装置104C之间的间隙区域中形成,以使得半导体管芯104A到半导体装置104C由包封体106嵌入高达包封体与调平膜111在其处介接的点。包封体106可以液体或半液体形式施加且随后相继固化。包封体106可以是模制化合物,如树脂、聚酰亚胺、聚苯硫醚(polyphenylene sulfide,PPS)、聚醚醚酮(polyether etherketone,PEEK)、聚碸(polyethersulfone,PES)、另一材料、类似物或其组合。然而,还可使用其它合适的包封技术和材料。
图5示出在包封工艺400已完成且平坦化工具113和调平膜111已去除之后结构的第二区域450的放大视图。图5示出从载体衬底102到第一位准Lvl1下方的点嵌入管芯附接衬垫103和半导体管芯104B到半导体管芯104C的包封体106。图5进一步示出在包封工艺400期间在调平膜111与包封体106介接的点处形成于包封体中的凹部501,其中凹部501的底部形成于第一位准Lvl1下方的一定距离处。根据一些实施例,凹部501的底部形成于第二密封深度sd2(见图4B)处。然而,可使用任何合适的距离。
图6示出保护涂层120在包封体106上方以及半导体装置104A到半导体装置104C的第一装置触点105和第二装置触点107的上部表面上方形成为处于或高于第一位准Lvl1的位准。如此,保护涂层120填充在包封工艺400期间形成于包封体106中的凹部501。根据一些实施例,选择具有大于包封体106(其可具有例如为零的拉伸)的热拉伸和压力拉伸特性的保护涂层120材料。举例来说,在一些实施例中,保护涂层120可具有比包封体106的热膨胀特性大至少75%的热膨胀特性。然而,可利用特性的任何适当改善。
在一些实施例中,保护涂层120可由一或多种合适的介电材料形成,如聚酰亚胺材料、氧化物(例如氧化硅)、氮化物(例如氮化硅)、聚合物材料(例如光敏聚合物材料)、低k介电材料、另一介电材料、类似物或其组合。保护涂层120可使用如旋涂、层压、化学气相沈积(chemical vapor deposition,CVD)、类似工艺或其组合的沉积工艺来形成。然而,任何合适的绝缘材料和任何合适的沉积工艺可用以形成保护涂层120。
图7示出根据一些实施例的研磨工艺700,所述研磨工艺用以薄化保护涂层120且暴露半导体装置104A到半导体装置104C的外部触点。半导体装置104A到半导体装置104C的保护涂层120和外部触点(例如第一装置触点105和第二装置触点107)可降低到处于或低于第一位准Lvl1的第二位准Lvl2。在一些实施例中,第二装置触点107可降低到约0.4微米与约10微米之间的厚度。如此,在一些实施例中,从半导体装置104A到半导体装置104C的外部触点去除焊料材料(例如第一装置触点105的微凸块,如果存在),且通过保护涂层120暴露外部触点(例如第一装置触点105和第二装置触点107)。
图7进一步示出保护涂层120,所述保护涂层包括形成于包封体106的凹部501内的保护接合部701。根据一些实施例,一旦使保护涂层120降低到第二位准Lvl2,保护涂层120便在半导体装置104A到半导体装置104C与第二位准Lvl2之间具有约3微米与约20微米之间的厚度ThPM,如约10微米,且保护接合部701具有范围介于约0微米与约20微米之间的接合凹部深度(jrD1),如约10微米。
归因于保护接合部701的所添加厚度以及由于保护涂层120的材料特性(例如弹性、刚性、拉伸强度等),保护涂层120在进一步加工(如研磨、通过可靠性应力进行的拷打)期间为吸收应力(例如管芯间拐角区域应力),在多回焊和/或热循环期间为晶圆翘曲和/或组件翘曲提供缓冲。如此,在进一步晶圆加工期间,保护涂层120可吸收由半导体装置104A到半导体装置104C的拐角施加到管芯间隙(例如dg1、dg2以及dg3)之间的区域的应力,进而增大制造工艺的集成可靠性窗口。如此,可降低或消除在这些工艺中先前已由模制化合物开裂诱发且随后传播到上覆层中的细线开裂故障。
图8示出根据一些实施例的前侧重布线结构122的形成。前侧重布线结构122包括介电层124、介电层128、介电层132以及介电层136;以及金属化图案126、金属化图案130以及金属化图案134。金属化图案也可称作重布线层或重布线线路。将前侧重布线结构122绘示为具有三层金属化图案的一实例。可在前侧重布线结构122中形成更多或更少介电层和金属化图案。如果将形成更少介电层和金属化图案,那么便可省略下文论述的步骤和工艺。如果将形成更多介电层和金属化图案,那么便可重复下文论述的步骤和工艺。前侧重布线结构122在本文中也可称为集成扇出(InFO)结构。
在图8中,第一介电层124沉积在保护涂层120、半导体装置104A到半导体装置104C以及由保护涂层120暴露的外部触点(例如第一装置触点105和第二装置触点107)上方。在一些实施例中,第一介电层124由可使用光刻掩模来图案化的光敏材料形成,如聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)或类似物。第一介电层124可通过旋涂、层压、CVD、类似方法或其组合形成。随后图案化第一介电层124。图案化形成开口,所述开口暴露半导体装置104A到半导体装置104C的外部触点(例如第一装置触点105和第二装置触点107)的部分。图案化可通过可接受的工艺来进行,如在第一介电层124是光敏材料时通过使第一介电层124暴露于光下来进行,或通过使用例如各向异性刻蚀进行刻蚀来进行。如果第一介电层124是光敏材料,那么便可在暴露之后对第一介电层124显影。
随后形成第一金属化图案126。第一金属化图案126包含在第一介电层124的主表面上且沿所述主表面延伸的线路部分(也称为导线)。第一金属化图案126更包含延伸穿过第一介电层124以将半导体装置104A到半导体装置104C物理耦合且电耦合到第一金属化图案126的通孔部分(也称为导电通孔)。作为形成第一金属化图案126的一实例,晶种层在第一介电层124上方以及延伸穿过第一介电层124的开口中形成。在一些实施例中,晶种层是金属层,其可以是单个层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层以及钛层上方的铜层。晶种层可使用例如PVD或类似方法而形成。随后在晶种层上形成并图案化光刻胶。光刻胶可通过旋涂或类似方法而形成,且可暴露于光下以用于图案化。光刻胶的图案对应于第一金属化图案126。所述图案化形成穿过光刻胶的开口以暴露晶种层。随后在光刻胶的开口中以及在晶种层的暴露部分上形成导电材料。所述导电材料可通过镀覆形成,如电镀或无电极镀覆或类似方法。所述导电材料可包括金属,如铜、钛、钨、铝或类似物。晶种层的导电材料与底层部分的组合形成第一金属化图案126。去除光刻胶以及在晶种层上未形成导电材料的部分。光刻胶可通过可接受的灰化或剥离工艺去除,如使用氧等离子或类似物。一旦将光刻胶去除,便将晶种层的暴露部分去除,如通过使用可接受的刻蚀工艺(如通过湿式或干式刻蚀)来进行。
一旦第一金属化图案126已沉积,便将第二介电层128沉积在第一金属化图案126和第一介电层124上。第二介电层128可以类似于第一介电层124的方式来形成,且可由与第一介电层124类似的材料形成。
随后形成第二金属化图案130。第二金属化图案130包含在第二介电层128的主表面上且沿所述主表面延伸的线路部分。第二金属化图案130更包含延伸穿过第二介电层128以物理耦合且电耦合第一金属化图案126的通孔部分。第二金属化图案130可以与第一金属化图案126类似的方式和类似的材料形成。在一些实施例中,第二金属化图案130具有与第一金属化图案126不同的大小。举例来说,第二金属化图案130的导线和/或通孔可比第一金属化图案126的导线和/或通孔更宽或更厚。此外,第二金属化图案130可形成为比第一金属化图案126更大的间距。
一旦第二金属化图案130已沉积,便将第三介电层132沉积在第二金属化图案130和第二介电层128上。第三介电层132可以类似于第一介电层124的方式形成,且可由与第一介电层124类似的材料形成。
随后形成第三金属化图案134。第三金属化图案134包含在第三介电层132的主表面上且沿所述主表面延伸的线路部分。第三金属化图案134更包含延伸穿过第三介电层132以物理耦合且电耦合第二金属化图案130的通孔部分。第三金属化图案134可以与第一金属化图案126类似的方式和类似的材料形成。第三金属化图案134是前侧重布线结构122的最顶部金属化图案。如此,前侧重布线结构122的所有中间金属化图案(例如第一金属化图案126和第二金属化图案130)安置在第三金属化图案134与保护涂层120之间。在一些实施例中,第三金属化图案134具有与第一金属化图案126和第二金属化图案130不同的大小。举例来说,第三金属化图案134的导线和/或通孔可比第一金属化图案126和第二金属化图案130的导线和/或通孔更宽或更厚。此外,第三金属化图案134可以比第二金属化图案130更大的间距形成。
图8进一步示出第四介电层136在第三金属化图案134和第三介电层132上方的沉积。第四介电层136可以类似于第一介电层124的方式形成,且可由与第一介电层124类似的材料形成。第四介电层136是前侧重布线结构122的最顶部介电层。如此,前侧重布线结构122的所有金属化图案(例如金属化图案126、金属化图案130以及金属化图案134)安置在第四介电层136与保护涂层120之间。此外,前侧重布线结构122的所有中间介电层(例如介电层124、介电层128、介电层132)安置在第四介电层136与保护涂层120之间。根据一些实施例,第四介电层136可形成为具有较大厚度,这有助于在前侧重布线结构122附接到另一衬底时降低施加于金属化图案126、金属化图案130以及金属化图案134上的机械应力。然而,第四介电层136可形成为具有与前侧重布线结构122的其它介电层124、介电层128、介电层132相同或类似的厚度。
一旦第四介电层136已沉积,便形成第一外部接点212以用于与前侧重布线结构122的外部连接。根据一些实施例,第一外部接点212包括UBM 138和导电接点150。UBM 138定位于第四介电层136的主表面上且沿所述主表面延伸,且具有延伸穿过第四介电层136以物理耦合且电耦合第三金属化图案134的通孔部分。因此,UBM 138电耦合到半导体装置104A到半导体装置104C。UBM 138可通过使第四介电层136图案化以形成暴露第三金属化图案134的部分的开口而形成。图案化可通过可接受的工艺来进行,如在第四介电层136是光敏材料时通过使第四介电层136暴露于光下来进行,或通过使用例如各向异性刻蚀进行刻蚀来进行。如果第四介电层136是光敏材料,那么便可在暴露之后使第四介电层136显影。
一旦使第四介电层136图案化,便在第四介电层136上方和第四介电层136的图案化开口中形成UBM 138。在一些实施例中,UBM 138包括金属晶种层,所述金属晶种层可以是单层或复合层,所述复合层包括使用例如物理气相沉积(physical vapor deposition,PVD)工艺或类似工艺由不同材料形成的多个子层(例如钛层以及钛层上方的铜层)。UBM138包括在晶种层(如果设置有)上方形成的导电材料。可通过旋涂或类似方法来沉积光刻胶且随后使其图案化(例如通过暴露于光下)以使得光刻胶中的开口对应于UBM138。一旦将光刻胶图案化,便在对应于UBM 138的光刻胶的开口中形成导电材料。导电材料包括金属(例如铜、钛、钨、铝、其合金、其组合或类似物)且可通过镀覆(例如电镀或无电极镀覆或类似方法)形成。随后,将光刻胶去除(例如经由灰化或剥离工艺,如使用氧等离子或类似物),且将晶种层(如果设置有)未由导电材料覆盖的暴露部分去除(例如通过使用可接受的刻蚀工艺,如通过湿式或干式刻蚀)。如此,UBM 138在第四介电层136中的图案化开口上方并穿过图案化开口而形成,且与第三金属化图案134接触。在其中UBM 138以不同方式形成的其它实施例中,可利用更多光刻胶和图案化步骤。此外,UBM 138可形成为具有任何合适的厚度(例如在约10微米到约40微米的范围内,如约30微米)且具有任何合适的宽度以使得施加于第三金属化图案134上的机械应力降低。如此,UBM 138的各种厚度和宽度使得前侧重布线结构122的机械可靠性增强。
图8进一步示出形成于UBM 138上的导电接点150。导电接点150可以是球栅阵列(ball grid array,BGA)接点、焊球、金属柱、受控塌陷芯片连接(controlled collapsechip connection,C4)凸块、微凸块、无电镀镍钯浸金技术(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸块或类似物。导电接点150可包含导电材料,如焊料、铜、铝、金、镍、银、钯、锡、类似物或其组合。在一些实施例中,导电接点150通过蒸镀、电镀、印刷、焊料转移、植球或类似方法初始地形成焊料层而形成。一旦在所述结构上形成焊料层,便可执行回焊以便使材料塑形为所要凸块形状。在另一实施例中,导电接点150包括通过溅镀、印刷、电镀、无电极镀覆、CVD或类似方法形成的金属柱(如铜柱)。金属柱可不含焊料且具有大体上竖直侧壁。在一些实施例中,在金属柱的顶部上形成金属顶盖层。金属顶盖层可包含镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金、类似物或其组合,且可通过镀覆工艺来形成。根据一些实施例,InFO装置100可从载体衬底102到第四介电层136嵌入于第二包封体(图中未示)中,同时使导电接点150暴露。
随后,执行载体衬底剥离以将载体衬底102从图8中所示结构的背侧(例如管芯附接衬垫103与包封体106的共面表面)拆离(或剥离)。根据一些实施例,剥离包含将如激光或UV光的光投射于管芯附接衬垫103上,以使得管芯附接衬垫103在光的热量下分解且可完全去除载体衬底102。一旦将载体衬底102去除,便使用研磨工艺或化学机械平面化(CMP)工艺来去除管芯附接衬垫103且暴露半导体管芯104B到半导体管芯104C。
通过使用调平膜111以防止包封体106在半导体装置104A到半导体装置104C上方延伸,且还防止包封体106完全填充半导体装置104A到半导体装置104C之间的区域,可使用保护涂层120来填充这些区域。因此,因为保护涂层120具有可更好地耐受出现于稍后工艺中的应力的更好的保护特性,所以保护层120的存在可更好地保护那些区域。如此,可降低或消除可能在后续制造期间出现的开裂和其它缺陷,进而增加制造工艺的总良率。
图9示出根据其它实施例的第二InFO装置900的横截面视图。第二InFO装置900可使用上文针对形成InFO装置100所阐述的材料中的任一种和工艺中的任一种而形成。根据一实施例,第二InFO装置900包括例如嵌入于第二包封体206内的一对半导体装置,但可利用任何适当数量的半导体装置。所述对半导体装置104D到半导体装置104E可以是设计成用于如上文关于半导体装置104A到半导体装置104C所阐述的预期目的的一对半导体装置。根据一实施例,所述对半导体装置104D到半导体装置104E包括例如第四半导体装置104D,如系统单芯片(SoC);以及第五半导体装置104E,如存储器管芯。然而,可使用任何合适的半导体管芯。
图9进一步示出包括如上文关于图4A到图8所描述而形成的包封体106、保护涂层120以及前侧重布线结构122的第二InFO装置900。包封体106填充第四半导体装置104D与第五半导体装置104E之间的大部分管芯间隙。保护涂层120在半导体装置104D到半导体装置104E之间延伸且包括保护接合部701,且在第二位准Lvl2处安置于包封体106、所述对半导体装置104D到半导体装置104E以及第二包封体206上方。前侧重布线结构122安置于保护涂层120上方,且包括UBM 138和导电接点150。
图10A和图10B示出根据一些实施例的并入有图9的第二InFO装置900和内连线结构300的晶圆级封装(WLP)1000的横截面视图。内连线结构300附接到第二InFO装置900且提供额外电布线。内连线结构300不含有源装置。在一些实施例中,内连线结构300可以是例如中介物或“半加工衬底”。内连线结构300还可对所附接装置结构(例如第二InFO装置900)提供稳定性和刚性,且可降低所附接装置结构的翘曲。
根据一些实施例,内连线结构300包括核心衬底302,所述核心衬底具有安置在相对表面上的导电层304。在一些实施例中,核心衬底302可包含如下材料:味之素堆积膜(Ajinomoto build-up film,ABF)、预浸复合物光纤(预浸料)材料、环氧树脂、模制化合物、环氧模制化合物、玻璃纤维增强树脂材料、印刷电路板(printed circuit board,PCB)材料、二氧化硅填充剂、聚合物材料、聚酰亚胺材料、纸、玻璃纤维、无纺玻璃织物、玻璃、陶瓷、其它层压物、类似物或其组合。在一些实施例中,核心衬底302可以是双侧铜包覆层压(copper-clad laminate,CCL)衬底或类似物。核心衬底302可具有约30微米与约2000微米之间的厚度,如约8000微米或约1200微米。导电层304可以是在核心衬底302的相对侧上层压或形成的一或多个铜层、镍层、铝层、其它导电材料层、类似层或其组合。在一些实施例中,导电层304可具有约1微米与约30微米之间的厚度。
图10A进一步示出形成于核心衬底302中的导电通孔306,所述导电通孔通过核心衬底302将第一导电布线层308连接到第二导电布线层309。第一导电布线层308形成为在核心衬底302的一侧上与导电层304接触,且第二导电布线层309形成为在核心衬底302的相对侧上与导电层304接触。核心衬底302中的用于导电通孔306的开口可使用在核心衬底302中形成开口的任何合适的技术(例如激光钻孔、机械钻孔、刻蚀或类似技术)来形成。导电层304、导电通孔306、第一导电布线层308以及第二导电布线层309可使用任何合适的光刻材料(例如光刻胶)和任何合适的光刻工艺(例如湿式化学刻蚀、干式刻蚀,如灰化)且使用如上文所阐述的适用于形成导电层304的任何合适的导电材料和任何合适的沉积工艺(例如镀覆、无电极镀覆或类似工艺)来形成。在一些实施例中,使导电通孔306、第一导电布线层308以及第二导电布线层309的材料沉积为约2微米与约50微米之间的厚度。
在一些实施例中,在沿开口的侧壁形成导电通孔306之后,可随后由介电穿孔核心307使用如下材料来填充开口:模制材料、环氧树脂、环氧模制化合物、树脂、包含单体或寡聚物的材料,如丙烯酸化氨基甲酸乙酯、经过橡胶改性的丙烯酸化环氧树脂或多功能单体、类似物或其组合。在一些实施例中,介电穿孔核心307可包含颜料或染料(例如用于显色),或改变流变性、提高粘着性或影响介电穿孔核心307的其它特性的其它填充剂和添加剂。介电穿孔核心307可使用例如旋涂工艺或另一工艺来形成。在一些实施例中,导电材料可完全填充导电通孔306,从而省略介电穿孔核心307。
额外介电层310和介电层314以及额外布线层311和布线层315可在第一导电布线层308和第二导电布线层309上方形成以形成布线结构312和布线结构316。布线结构312和布线结构316在核心衬底302的相对侧上形成,且可在内连线结构300内提供额外电布线。布线结构312和布线结构316分别电连接到第一导电布线层308和第二导电布线层309。布线结构312和布线结构316中的每一个可分别包括任何适当数量的额外介电层310和介电层314以及任何适当数量的额外布线层311和布线层315。在一些实施例中,布线结构312或布线结构316中的一个或两个可省略。在一些情况下,布线结构312或布线结构316中的其它额外布线层311和布线层315的数量可通过增加所附接装置结构(例如第二InFO装置900)的前侧重布线结构122中的重布线层的数量来降低。
使用如上文所阐述的适合于形成核心衬底302的介电层的介电材料和沉积工艺中的任一种在第一导电布线层308和第二导电布线层309上方形成额外介电层310和介电层314。在一些实施例中,额外介电层310和介电层314可具有约2微米与约50微米之间的厚度。在暴露第一导电布线层308和第二导电布线层309的部分的额外介电层310和介电层314中形成开口(图中未示)以用于后续电连接。可使用如上文所阐述的适合于在核心衬底302中形成开口的材料和技术中的任一种来在额外介电层310和介电层314中形成开口。一旦暴露,导电材料便沉积在额外介电层310和介电层314上方以形成额外布线层311和布线层315,其中金属化通孔313和金属化通孔317形成为分别与第一导电布线层308和第二导电布线层309接触。在一些实施例中,可在额外介电层310和介电层314上方形成导电层(图中未示),所述导电层可充当用于沉积用以形成额外布线层311和布线层315的导电材料的晶种层。导电材料可以是例如金属箔,如铜箔;或另一类型的材料,如上文针对导电层304所描述的那些材料。在一些实施例中,沉积导电材料以使额外布线层311和布线层315形成为约2微米与约50微米之间的厚度。如此,布线结构312和布线结构316的额外布线层311和布线层315可通过穿透金属化通孔313和金属化通孔317以及导电通孔306而彼此电性连接。
在一些实施例中,保护层404首先在布线结构312和布线结构316上方形成。在一些实施例中,保护层404首先在布线结构312和布线结构316上方形成。保护层404可在第二UBM438(如果存在)上方形成。保护层404可由一或多种合适的介电材料形成,如聚苯并恶唑(polybenzoxazole,PBO)、聚合物材料、聚酰亚胺材料、聚酰亚胺衍生物、氧化物、氮化物、类似物或其组合。保护层404可通过如以下的工艺而形成:旋涂、层压、CVD、类似工艺或其组合。保护层404可具有约0.5微米与约50微米之间的厚度,如约20微米,但可使用任何合适的厚度。
可随后在保护层404中形成开口以暴露布线结构312(其可包含第二UBM 438,如果存在)的部分。保护层404中的开口可使用合适的技术来形成,如激光钻孔或光刻掩模以及刻蚀工艺。一旦已在保护层404中形成开口,第二外部接点406便在布线结构312的暴露部分上方形成且形成与布线结构312的电连接。根据一些实施例,第二外部接点406包括第二UBM438和第二导电接点440。在一些实施例中,第二UBM 438在布线结构312上形成,且第二外部接点406在第二UBM 438上方形成。第二导电接点440可包括例如接触凸块或焊球,但可利用任何适当类型的接点。在其中第二外部接点406包括如接触凸块的第二导电接点440的一实施例中,第二外部接点406可包含如锡的材料,或其它合适的材料,如银、无铅锡或铜。在其中第二外部接点406是锡焊料凸块的一实施例中,第二外部接点406可通过初始地使用如蒸发、电镀、印刷、焊料转移、植球等的此类技术形成锡层而形成。一旦在结构上形成锡层,便可执行回焊以便将材料塑形成第二外部接点406的所要凸块形状。在一些实施例中,第二外部接点406可具有约2微米与约1000微米之间的厚度。在一些实施例中,第二外部接点406可具有约250微米与约1250微米之间的间距。在一些实施例中,第二外部接点406可类似于上文所描述的第一外部接点212。图10A进一步示出虚线轮廓,所述虚线轮廓突出显示在第二InFO装置900附接到内连线结构300之后结构的第三区域1050。
在一些实施例中,保护层404可在布线结构312和布线结构316上方形成作为例如阻焊剂材料,且可形成以保护布线结构312或布线结构316的表面。在一些实施例中,保护层404可以是通过印刷、层压、旋涂或类似方法形成的光敏材料。光敏材料可随后暴露于光学图案并显影,从而在光敏材料中形成开口。在其它实施例中,保护层404可通过以下操作形成:沉积非光敏介电层(例如氧化硅、氮化硅、类似物或组合),使用合适的光刻技术在介电层上方形成图案化光刻胶掩模,且随后使用图案化光刻胶掩模使用合适的刻蚀工艺(例如湿式刻蚀或干式刻蚀)来刻蚀介电层。可在布线结构312和布线结构316上方使用相同技术来形成保护层404且使其图案化。在一些实施例中,保护层404可具有约10微米与约300微米之间的厚度。也可使用其它工艺和材料。
图10A和图10B进一步示出根据一些实施例的使内连线结构300与第二InFO装置900电连接。虽然图10A和图10B示出包括接合到单个内连线结构(例如内连线结构300)的单个InFO装置(例如第二InFO装置900)的晶圆级封装(WLP)1000,但应理解,在其它实施例中,在将多个装置结构单体化为多个相异晶圆级封装(例如晶圆级封装(WLP)1000)之前,晶圆级封装(WLP)1000可包括接合到多个InFO装置(例如第二InFO装置900)的多个内连线结构(例如内连线结构300)。在一实施例中,使用例如取放工艺使内连线结构300与第二InFO装置900的第一外部接点212(包括例如UBM 138和导电接点150)物理接触。内连线结构300可放置成使得最顶部布线层(例如布线结构312的额外布线层311)的暴露区域与第一外部接点212的对应接点对准。一旦对准且呈物理接触,便可使用回焊工艺来将第二InFO装置900的第一外部接点212接合到内连线结构300。在一些实施例中,替代在第二InFO装置900上形成的第一外部接点212或除所述第一外部接点以外,在内连线结构300上形成外部接点。在一些实施例中,第一外部接点212不在第二InFO装置900上形成,且使用直接接合技术将内连线结构300接合到第二InFO装置900,所述直接接合技术如热压缩接合技术或其它接合技术,如混合接合、介电与介电接合、金属与金属接合、这些接合的组合或类似技术。
在图10A和图10B中,模制底填充料402沉积在内连线结构300与第二InFO装置900之间的间隙中。模制底填充料402可以是如模制化合物、环氧树脂、底填充料、模制底填充料(molding underfill,MUF)、树脂或类似物的材料。模制底填充料402可保护第一外部接点212,且为晶圆级封装(WLP)1000提供结构支撑。在一些实施例中,模制底填充料402可在沉积之后固化。
另外,在上述实施例中的每一个中,还可包含其它特征和工艺。举例来说,可包含测试结构以辅助对3D封装或3DIC装置的校验测试。测试结构可包含例如形成于重布线层中或衬底上的测试衬垫,所述衬底允许对3D封装或3DIC的测试、对探针和/或探针卡的使用以及类似操作。可对中间结构以及最终结构执行校验测试。另外,本文中所公开的结构和方法可与并入有已知良好管芯的中间校验的测试方法结合使用以增大良率并减少成本。
在一些实施例中,一种半导体装置的制造方法包含:使用第一管芯附接衬垫将第一半导体装置附接到衬底;使用第二管芯附接衬垫将第二半导体装置附接到衬底;使用包封体填充第一管芯附接衬垫与第二管芯附接衬垫之间的间隙且至少部分地填充第一半导体装置与第二半导体装置之间的间隙;使保护涂层沉积在包封体上方以及第一半导体装置和第二半导体装置上方,沉积保护涂层填充第一半导体装置与第二半导体装置之间的间隙的剩余部分;以及在保护涂层上方形成重布线结构。在一实施例中,第一半导体装置包括系统芯片。在一实施例中,第二半导体装置包括高带宽存储器堆叠。在一实施例中,在第一半导体装置与第二半导体装置之间的间隙内的保护涂层的一部分具有小于约20微米的厚度。在一实施例中,沉积保护涂层包括沉积聚酰亚胺材料。在一实施例中,方法更包含在重布线结构上方形成外部接点,第一半导体装置和第二半导体装置的外部触点电耦合到外部接点。在一实施例中,方法更包含将内连线结构附接到与第一半导体装置和第二半导体装置相对的重布线结构。
根据一些实施例,一种半导体装置的制造方法包含:在衬底上形成第一管芯附接衬垫和与第一管芯附接衬垫分隔的第二管芯附接衬垫;在第一管芯附接衬垫上放置第一半导体管芯且在第二管芯附接衬垫上放置第二半导体管芯;在第一半导体管芯和第二半导体管芯上方放置调平膜;使用调平膜将第一半导体管芯和第二半导体管芯调平到第一位准;在衬底上方沉积模制化合物且至少部分地填充第一半导体管芯与第二半导体管芯之间从衬底到调平膜的管芯间隙,调平膜与模制化合物之间的界面处于或低于第一半导体管芯和第二半导体管芯的拐角区域;去除调平膜;在模制化合物以及第一半导体管芯和第二半导体管芯上方沉积介电层;以及在介电层上方形成重布线层。在一实施例中,放置调平膜包括在第一半导体管芯的上部表面和外部触点上方使用调平膜形成密封件。在一实施例中,形成密封件包括在第一半导体管芯的交叉侧壁的拐角区域上方形成密封件。在一实施例中,将第一半导体管芯和第二半导体管芯调平到第一位准更包括使第一管芯附接衬垫变形为第一厚度且使第二管芯附接衬垫变形为小于第一厚度的第二厚度,以使得第一半导体管芯和第二半导体管芯的外部触点在第一位准处对准。在一实施例中,形成第一管芯附接衬垫和第二管芯附接衬垫包括使第一管芯附接衬垫和第二管芯附接衬垫形成为相同初始厚度和不同宽度。在一实施例中,方法更包含在重布线层上方形成外部接点,外部接点电耦合到第一半导体管芯的外部触点。在一实施例中,方法更包含将中介物结构附接到与第一半导体管芯和第二半导体管芯相对的重布线层。
根据一些实施例,一种半导体装置包含:第一半导体管芯,具有第一外部触点;第二半导体管芯,具有第二外部触点,其中第一外部触点和第二外部触点安置于同一位准处;包封体,至少部分地填充第一半导体管芯与第二半导体管芯之间的间隙;保护层,位于包封体、第一半导体管芯以及第二半导体管芯上方,其中保护层与包封体之间的界面安置在第一半导体管芯与第二半导体管芯的侧壁之间;以及重布线结构,位于保护层上方,其中重布线结构包括电耦合到第一外部触点中的至少一个的金属化物层。在一实施例中,在第一半导体管芯与第二半导体管芯的侧壁之间的保护层的一部分具有小于约20微米的厚度。在一实施例中,保护层更包括界面,界面具有第一半导体管芯和第二半导体管芯的侧壁。在一实施例中,第一半导体管芯和第二半导体管芯中的一个是系统芯片装置,且第一半导体管芯和第二半导体管芯中的另一个是高带宽存储器立方体。在一实施例中,半导体装置更包含位于重布线结构上方的外部接点,所述外部接点电耦合到第一半导体管芯和第二半导体管芯的接触衬垫。在一实施例中,半导体装置更包含在重布线结构上方的中介物结构,其中中介物结构的外部触点通过重布线结构来电耦合到第一半导体管芯和第二半导体管芯。
前文概述若干实施例的特征以使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解,其可易于将本公开用作设计或修改用于实施本文中所引入的实施例的相同目的和/或实现相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到,这类等效构造并不脱离本公开的精神和范围,且其可在不脱离本公开的精神和范围的情况下在本文中做出各种改变、替代以及更改。
Claims (1)
1.一种半导体装置的制造方法,其特征在于,包括:
使用第一管芯附接衬垫将第一半导体装置附接到衬底;
使用第二管芯附接衬垫将第二半导体装置附接到所述衬底;
使用包封体填充所述第一管芯附接衬垫与所述第二管芯附接衬垫之间的间隙且至少部分地填充所述第一半导体装置与所述第二半导体装置之间的间隙;
在所述包封体上方以及所述第一半导体装置和所述第二半导体装置上方沉积保护涂层,所述沉积所述保护涂层填充所述第一半导体装置与所述第二半导体装置之间的所述间隙的剩余部分;以及
在所述保护涂层上方形成重布线结构。
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