CN106409816A - 具有对准标记的集成电路管芯及其形成方法 - Google Patents
具有对准标记的集成电路管芯及其形成方法 Download PDFInfo
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- CN106409816A CN106409816A CN201610557174.7A CN201610557174A CN106409816A CN 106409816 A CN106409816 A CN 106409816A CN 201610557174 A CN201610557174 A CN 201610557174A CN 106409816 A CN106409816 A CN 106409816A
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Abstract
本发明的实施例提供了具有对准标记的管芯及其形成方法。一种方法包括:在第一工件的第一侧面上形成沟槽,所述第一工件的管芯介于相邻的沟槽之间;去除管芯的一部分以形成对准标记,对准标记延伸穿过管芯的整个厚度。减薄第一工件的第二侧面,直到管芯被分割,第二侧面与第一侧面相对。
Description
技术领域
本发明总体涉及半导体领域,更具体地,涉及集成电路管芯及其形成方法。
背景技术
半导体器件用于多种电子应用,诸如个人计算机、手机、数码相机和其他的电子设备。通常通过以下步骤来制造半导体器件:在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层;以及使用光刻来图案化该多个材料层,以在该多个材料层上形成电路组件和元件。通常在单个半导体晶圆上制造数十或数百集成电路。通过沿着划割线锯切集成电路来切割单独的管芯。然后,通常以多芯片模块或以其他的封装类型将单独的管芯分别封装。
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成度不断提高,半导体行业已经历了快速的发展。在很大程度上,集成度的这种提高源自于最小特征尺寸的不断减小(例如,将半导体工艺节点减小至亚20nm节点),这允许在给定区域内集成更多的组件。由于近来对小型化、更高速度、更大带宽以及更低功耗和更小延迟的需求的增长,已经产生对更小且更富创造性的半导体管芯封装技术的需要。
随着半导体技术的进一步发展,已经出现了堆叠的半导体器件(例如,三维集成电路(3DIC))作为进一步减小半导体器件的物理尺寸的有效替代。在堆叠的半导体器件中,在不同的半导体晶圆上制造诸如逻辑电路、存储器电路、处理器电路等的有源电路。两个或更多的半导体晶圆可以彼此安装或堆叠在另一个的顶面以进一步降低半导体器件的形状因数。叠层封装件(POP)器件是一种类型的3DIC,其中,封装管芯然后将管芯与另一封装过的管芯或管芯封装在一起。
发明内容
根据本发明的一个方面,提供了一种方法,包括:在第一工件的第一侧面上形成沟槽,所述第一工件的管芯介于相邻的沟槽之间;去所述除管芯的一部分以形成对准标记,所述对准标记延伸穿过所述管芯的整个厚度;以及减薄所述第一工件的第二侧面,直到所述管芯被分割,所述第二侧面与所述第一侧面相对。
优选地,所述管芯是分立的半导体器件芯片。
优选地,该方法还包括:使用所述对准标记将所述管芯与第二工件对准;以及将所述管芯附着至所述第二工件。
优选地,所述第二工件是集成电路封装件,所述管芯附着至所述集成电路封装件的一个或多个再分布层(RDL)。
优选地,同时形成所述沟槽和所述对准标记。
优选地,去除所述管芯的一部分包括:自顶往下看,从所述管芯的侧面去除多边形部分。
优选地,去除所述管芯的一部分包括:自顶往下看,从所述管芯的角部去除多边形部分。
根据本发明的另一方面,提供了一种方法,包括:在第一工件的第一侧面上形成第一凹槽,所述第一凹槽暴露管芯的侧面;在所述第一工件的第一侧面上形成第二凹槽以在所述管芯上形成对准标记,所述第一凹槽和所述第二凹槽具有相同的深度;以及减薄所述第一工件的第二侧面,直到所述管芯被分割,所述第二侧面与所述第一侧面相对。
优选地,所述管芯是分立的半导体器件芯片。
优选地,该方法还包括:使用所述对准标记将所述管芯与第二工件对准;将所述管芯附着至所述第二工件;以及将所述第二工件切割为单独的器件。
优选地,所述第二工件包括多个密封的芯片以及所述多个密封的芯片上方的一个或多个再分布层(RDL),所述管芯附着至所述一个或多个RDL,所述一个或多个RDL介于所述管芯与所述多个密封的芯片之间。
优选地,同时形成所述第一凹槽和所述第二凹槽。
优选地,自顶往下看,形成所述第二凹槽从所述管芯的侧面去除了多边形部分。
优选地,自顶往下看,形成所述第二凹槽从所述管芯的角部去除了多边形部分。
根据本发明的又一方面,提供了一种半导体器件,包括:管芯,包括:衬底;器件,位于所述衬底上;和介电层,位于所述衬底和所述器件上方;以及对准标记,位于所述管芯上,所述对准标记完全延伸穿过所述介电层和所述衬底。
优选地,该半导体器件还包括:第一工件,附着至所述管芯,所述第一工件包括:密封的芯片;以及一个或多个再分布层(RDL),位于所述密封的芯片上方,所述一个或多个RDL介于所述管芯与所述密封的芯片之间。
优选地,所述管芯是分立的半导体器件芯片。
优选地,所述对准标记是所述管芯的侧面中的空隙。
优选地,所述对准标记是所述管芯的被切开的角部。优选地,所述对准标记是所述管芯的角部中的刻痕。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增加或减少。
图1A至图3B是根据一些实施例的制造具有一个或多个对准标记的集成电路管芯期间的各个处理步骤的顶视图和截面图。
图4是根据一些实施例的集成电路管芯的顶视图。
图5是根据一些实施例的集成电路管芯的顶视图。
图6是根据一些实施例的集成电路管芯的顶视图。
图7是根据一些实施例的集成电路管芯的顶视图。
图8是示出了根据一些实施例的形成具有一个或多个对准标记的集成电路管芯的方法的流程图。
图9至图13是根据一些实施例的制造集成电路封装件期间的多个处理步骤的截面图。
图14是示出了根据一些实施例的形成集成电路封装件的方法的流程图。
具体实施方式
以下公开内容提供了许多不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外,空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可同样地作相应地解释。
在具体地描述所示出的实施例之前,通常描述所公开的实施例的特定优势特征和各方面。下文描述的是具有对准标记的各个集成电路管芯及用于形成这种集成电路管芯的方法。另外,下文描述了使用集成电路管芯来形成集成电路封装件的方法。通过形成具有一个或多个对准标记的集成电路管芯,可以在形成集成电路封装件时减少或避免集成电路管芯的不期望的偏移或旋转。此外,可以减少或避免由未对准导致的对于集成电路管芯的损害。
图1A至图3B是根据一些实施例的制造具有对准标记的集成电路管芯期间的各个处理步骤的顶视图和截面图,其中,“A”图表示顶视图,并且“B”图表示沿着相应的“A”图的线B-B'得到的截面图。
参考图1A和图1B,示出了具有通过划线103(也称为切割线或切割区)分隔的管芯区域101的工件100的一部分。如下文更加详细地示出的,将沿着划线103切割工件100,以形成单独的集成电路管芯(诸如图3A和图3B示出的集成电路管芯301)。在一些实施例中,工件100包括衬底105、衬底105上的一个或多个有源和/或无源器件115以及衬底105和一个或多个有源和/或无源器件115上方的一个或多个金属化层117。在一些实施例中,衬底105可以由硅形成,但是其还可以由其他III族、IV族和/或V族元素形成,诸如,硅、锗、镓、砷、以及它们的组合。衬底105也可以呈绝缘体上硅(SOI)的形式。SOI衬底可以包括形成在绝缘层(如,掩埋氧化物等)上方的半导体材料层(如,硅、锗等),其中,绝缘层形成在硅衬底上。另外,可以使用的其他衬底包括多层衬底、梯度衬底、混合取向衬底、它们的任意组合等。在其他的实施例中,衬底105可以包括介电材料,诸如氧化硅、氧化铝等或它们的组合。
在一些实施例中,一个或多个有源和/或无源器件115可以包括诸如晶体管的各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件、电容器、电阻器、二极管、光电二极管、熔丝等。在一些实施例中,集成电路管芯(见图3A和图3B)可以是分立的半导体器件芯片(有时称为表面贴装器件(SMD)或集成无源器件(IPD))。在这种实施例中,衬底105可以包括各种器件,诸如RLC电路、电容器、电感器、变压器、换衡器(baluns)、微带(micro-stripe)、共面波导等,并且可以基本不含有源器件。
一个或多个金属化层117可以包括形成在衬底105上方的层间介电层(ILD)/金属间介电层(IMD)。例如,可以通过本领域内已知的任何合适的方法(诸如,旋涂方法、化学汽相沉积(CVD)、等离子体增强的CVD(PECVD)等或它们的组合)由低K介电材料(诸如,磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等)形成ILD/IMD层。在一些实施例中,例如,可以使用镶嵌工艺、双镶嵌工艺等在ILD/IMD中形成互连结构。在一些实施例中,互连结构可以包括铜、铜合金、银、金、钨、钽、铝等。在一些实施例中,互连结构可以在形成在衬底上的一个或多个有源和/或无源器件115之间提供电连接。
在一些实施例中,工件100还包括形成在一个或多个金属化层117上方的接触焊盘107,并且可以通过一个或多个金属化层117中的各个互连结构电耦接至一个或多个有源和/或无源器件115。如下文更加详细的描述,将在接触焊盘107上形成连接件。在一些实施例中,接触焊盘107可以包括导电材料,诸如铝、铜、钨、银、金等或它们的组合。在一些实施例中,例如,可以使用物理汽相沉积(PVD)、原子层沉积(ALD)、电化学镀、无电镀等或它们的组合来在一个或多个金属化层117上方形成导电材料。随后,图案化导电材料以形成接触焊盘107。在一些实施例中,可以使用光刻技术来图案化导电材料。通常,光刻技术包括沉积光刻胶材料(未示出),随后,对该光刻胶材料进行照射(曝光)以及显影,以去除部分光刻胶材料。剩余的光刻胶材料保护下面的材料(诸如接触焊盘107的导电材料)免受随后的诸如蚀刻的处理步骤。可以将诸如反应离子蚀刻(RIE)或其他干蚀刻、各向同性或各向异性的湿蚀刻的合适的蚀刻工艺或其他任何合适的蚀刻或图案化工艺应用于导电材料,以去除导电材料的暴露部分,从而形成接触焊盘107。在导电材料为铝的一些实施例中,可以使用80%的磷酸、5%的硝酸、5%的乙酸和10%的去离子(DI)水的混合物来蚀刻导电材料。随后,例如,可以使用灰化工艺随后通过湿清洗工艺来去除光刻胶材料。
还参考图1A和图1B,在一些实施例中,钝化层109形成在衬底105和接触焊盘107上方。在一些实施例中,钝化层109可以包括一层或多层可光图案化的介电材料,诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等,并且可以使用旋涂工艺等来形成。可以使用与光刻胶材料类似的光刻方法容易地图案化这种可光图案化的介电材料。在其他的实施例中,钝化层109可以包括一层或多层不可光图案化的介电材料,诸如氮化硅、氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等,并且可以使用CVD、PVD、ALD、旋涂工艺等或它们的组合来形成。
在钝化层109中形成开口以暴露接触焊盘107。在钝化层109由可光图案化的介电材料形成的一些实施例中,可以使用与光刻胶材料类似的光刻方法来图案化钝化层109。在钝化层109由不可光图案化的介电材料形成的其他的实施例中,在钝化层109上方形成光刻胶材料(未示出)。随后,对光刻胶材料进行照射(曝光)以及显影,以去除部分光刻胶材料。随后,例如使用合适的蚀刻工艺去除钝化层109的暴露部分以形成开口。在钝化层109由氧化硅形成的一些实施例中,例如,使用缓冲的氢氟酸(HF)来蚀刻钝化层109。在钝化层109由氮化硅形成的一些实施例中,例如,使用热磷酸(H3PO4)来蚀刻钝化层109。随后,例如,可以使用灰化工艺随后通过湿清洗工艺来去除光刻胶材料。
在一些实施例中,在钝化层109的开口中,凸块下金属件(UBM)111形成在暴露的接触焊盘107上方。UBM 111可以延伸穿过钝化层109中的开口并且也沿着钝化层109的表面延伸。在一些实施例中,UBM 111可以包括三层导电材料,诸如钛层、铜层和镍层。然而,本领域的普通技术人员将意识到,可以有多种材料和层的合适的布置,诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置,这些都适用于UBM的形成。可用于UBM 111的任何合适的材料或材料层都包括在本发明的范围内。
在一些实施例中,连接件113形成在UBM 111上方并且与其电耦接。在一些实施例中,连接件113可以是焊球、金属柱、可控坍塌芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。连接件113可以包括导电材料,诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在连接件113是焊料凸块的一些实施例中,通过由诸如蒸发、电镀、印刷、焊料转移(transfer)、植球等常用的方法首先形成焊料层来形成连接件113。一旦在结构上形成焊料层,就可以执行回流,以将材料成形为期望的凸块形状。在其他的实施例中,连接件113可以是通过溅射、印刷、电化学镀、无电镀、PVD等形成的金属柱(例如,诸如铜柱)。金属柱可以不含焊料并且具有基本垂直的侧壁。在一些实施例中,在金属柱的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括焊料、镍、锡、锡-铅、金、银、钯、铟、镍-钯-金、镍-金等或它们组合并且可以通过镀法工艺等来形成。
参考图2A和图2B,在一些实施例中,管芯区域101的顶视图以及集成电路管芯的顶视图可以在旋转90°、180°和/或270°情况下几何对称。然而,管芯区域101以及集成电路管芯可以在旋转90°、180°和/或270°情况下在功能上不对称。因此,一个或多个对准标记可以形成在每一个集成电路管芯上以标示集成电路管芯的适当的方位。在一些实施例中,图案化工件100以形成沿着划线103(见图1A和图1B)的沟槽201,从而沟槽201使工件100的各管芯区域101分隔。沟槽201具有位于衬底105中的底部201B,因此,将工件100部分地切割为单个集成电路管芯。在一些实施例中,图案化工艺还从每一个管芯区域101的角部去除三角形部分203(自顶往下看)以形成对准标记205,从而使得去除三角形部分203之后形成的凹槽的底部与沟槽201的底部201B基本共面。在一些实施例中,每一个对准标记205都允许对于对应的集成电路管芯的适当的方位的识别。在一些实施例中,例如,可以使用蚀刻、锯切、激光烧蚀等或它们的组合来图案化工件100。在一些实施例中,例如,合适的蚀刻工艺可以包括深反应离子蚀刻(DRIE)工艺,诸如Bosh工艺等。在一些实施例中,可以在大约10秒至大约600秒之间的时间段内、在大约室温与大约100℃之间的温度下、在大约几mTorr与大约几百mTorr之间的压力下,使用诸如SF6/Ar等的蚀刻气体,以及使用诸如C4F8等的源气体来执行Bosh工艺。
参考图3A和图3B,在一些实施例中,减薄衬底105的背侧105B,直到去除沟槽201的底部201B。这种减薄工艺将工件100分割为单独的集成电路管芯301,并且对准标记205延伸穿过集成电路管芯301的整个厚度。在一些实施例中,例如,可以使用合适的蚀刻工艺、化学机械抛光(CMP)工艺、机械研磨工艺等或它们的组合来减薄衬底105的背侧105B。随后,可以测试每一个集成电路管芯301以识别已知良好管芯(KGD)以用于进一步的处理。如下文更加详细的描述,集成电路管芯301将用于形成集成电路封装件。
在示出的实施例中,每一个集成电路管芯301都包括四个接触焊盘(诸如接触焊盘107)、四个连接件(诸如连接件113)以及单个钝化层(诸如钝化层109)。本领域的普通技术人员将意识到,仅是为了说明的目的而提供钝化层、接触焊盘以及连接件的数量,而不是对于本发明保护范围的限制。在其他的实施例中,根据集成电路管芯301的设计需要,每一个集成电路管芯301都可以包括适当个数的钝化层、接触焊盘以及连接件。
图4是根据一些实施例的一个集成电路管芯301的顶视图。在一些实施例中,集成电路管芯301的第一侧面可以具有介于大约500μm和大约10000μm之间的宽度W1,并且集成电路管芯301的第二侧面可以具有介于大约500μm和大约10000μm之间的宽度W2。在一些实施例中,三角形部分203的第一侧面(平行于集成电路管芯301的第一侧面)可以具有介于大约W1/10和大约W1/2之间的第一长度L1,并且三角形部分203的第二侧面(平行于集成电路管芯301的第二侧面)可以具有介于大约W2/10和大约W2/2之间的第二长度L2。
图5是根据一些实施例的集成电路管芯500的顶视图。在一些实施例中,可以使用与以上参考图1A至图3B所述的集成电路管芯301类似的材料和方法形成集成电路管芯500,并且类似元件用类似标号标记,因此本文不再重复描述。在一些实施例中,在以上参考图2A和图2B所述的图案化工艺期间,分别从集成电路管芯500的第一角部和第二角部(与第一角部相对)去除第一三角形部分501和第二三角形部分503(自顶往下看),以形成第一对准标记505和第二对准标记507。在一些实施例中,第一三角形部分501的尺寸可以等于第二三角形部分503的尺寸。在其他的实施例中,第一三角形部分501和第二三角形部分503可以具有不同的尺寸。在一些实施例中,集成电路管芯500的第一侧面可以具有介于大约500μm和大约10000μm之间的宽度W1,并且集成电路管芯500的第二侧面可以具有介于大约500μm和大约10000μm之间的宽度W2。在一些实施例中,第一三角形部分501的第一侧面(平行于集成电路管芯500的第一侧面)可以具有介于大约W1/10和大约W1/2之间的第一长度L3,并且第一三角形部分501的第二侧面(平行于集成电路管芯500的第二侧面)可以具有介于大约W2/10和大约W2/2之间的第二长度L4。在一些实施例中,第二三角形部分503的第一侧面(平行于集成电路管芯500的第一侧面)可以具有介于大约W1/10和大约W1/2之间的第一长度L5,并且第二三角形部分503的第二侧面(平行于集成电路管芯500的第二侧面)可以具有介于大约W2/10和大约W2/2之间的第二长度L6。
图6是根据一些实施例的集成电路管芯600的顶视图。在一些实施例中,可以使用与以上参考图1A至图3B所述的集成电路管芯301类似的材料和方法形成集成电路管芯600,并且类似元件用类似标号来标记,因此本文不再重复描述。在一些实施例中,在以上参考图2A和图2B所述的图案化工艺期间,从集成电路管芯600的角部去除矩形部分601(自顶往下看)以形成对准标记603。在一些实施例中,集成电路管芯600的第一侧面可以具有介于大约500μm和大约10000μm之间的宽度W1,并且集成电路管芯600的第二侧面可以具有介于大约500μm和大约10000μm之间的宽度W2。在一些实施例中,矩形部分601的第一侧面(平行于集成电路管芯600的第一侧面)可以具有介于大约W1/10和大约9W1/10之间的第一长度L7,并且矩形部分601的第二侧面(平行于集成电路管芯600的第二侧面)可以具有介于大约W2/10和大约9W2/10之间的第二长度L8。
图7是根据一些实施例的集成电路管芯700的顶视图。在一些实施例中,可以使用与以上参考图1A至图3B所述的集成电路管芯301类似的材料和方法形成集成电路管芯700,并且类似元件用类似标号标记,因此本文不再重复描述。在一些实施例中,在以上参考图2A和图2B所述的图案化工艺期间,从集成电路管芯700的侧壁去除矩形部分701(自顶往下看)以形成对准标记703。在一些实施例中,集成电路管芯700的第一侧面可以具有介于大约500μm和大约10000μm之间的宽度W1,并且集成电路管芯700的第二侧面可以具有介于大约500μm和大约10000μm之间的宽度W2。在一些实施例中,矩形部分701的第一侧面(平行于集成电路管芯700的第一侧面)可以具有介于大约W1/10和大约W1/2之间的第一长度L9,并且矩形部分701的第二侧面(平行于集成电路管芯700的第二侧面)可以具有介于大约W2/10和大约W2/2之间的第二长度L10。
还参考图4至图7,在示出的实施例中,从管芯区域101去除三角形部分和矩形部分,以形成集成电路管芯301、500、600和700的对准标记。在其他的实施例中,根据集成电路管芯的设计需要,可以从管芯区域101去除圆形、椭圆形或多边形部分,以形成对准标记。
图8是示出了根据一些实施例的形成具有一个或多个对准标记的集成电路管芯的方法800的流程图。方法开始于步骤801,其中,图案化工件(诸如工件100)以形成工件的管芯区域(诸如管芯区域101)之间的沟槽(诸如沟槽201)并且从以上参考图2A和图2B所述的每一个管芯区域去除一部分(诸如三角形部分203)。在步骤803中,减薄工件的背侧,直到将工件切割为如以上参考图3A和图3B所述的单独的集成电路管芯(诸如集成电路管芯301)。
图9至图13是根据一些实施例的制造集成电路封装件期间的多个处理步骤的截面图。如下文更加详细的描述,集成电路管芯(例如,诸如图4至图7所示的集成电路管芯301、500、600、700)将用于形成集成电路封装件(诸如图13所示的集成电路封装件1215)。
参考图9,在一些实施例中,脱模层(release layer)903形成在载体901上方,并且一个或多个介电层905形成在脱模层903上方以开始形成集成电路封装件。在一些实施例中,载体901可以由石英、玻璃等形成并且为随后的操作提供机械支撑。在一些实施例中,脱模层903可以包括光热转换(LTHC)材料、UV胶等,并且可以使用旋涂工艺、印刷工艺、层压工艺等形成。在一些实施例中,当由LTHC材料形成的脱模层903暴露于光下时,其会部分或完全地失去粘合强度,因此载体901可以容易地从随后形成的结构的背侧处去除。在一些实施例中,可以使用与以上参考图1A和图1B所述的钝化层109类似的材料和方法来形成一个或多个介电层905,因此本文不再重复描述。
还参考图9,导电通孔907形成在一个或多个介电层905上。在一些实施例中,晶种层(未示出)形成在一个或多个介电层905上。晶种层可以包括铜、钛、镍、金等或它们的组合,并且可以使用电化学镀、ALD、PVD、溅射等或它们的组合来形成。在一些实施例中,牺牲层(未示出)形成在晶种层上方。多个开口形成在牺牲层中以暴露晶种层的一部分。在牺牲层包括光刻胶材料的一些实施例中,可以使用合适的光刻方法形成牺牲层。在一些实施例中,使用电化学镀工艺、无电镀工艺、ALD、PVD等或它们的组合,利用导电材料(诸如铜、铝、镍、金、银、钯等或它们的组合)填充牺牲层的开口以形成导电通孔907。在完成导电通孔907的形成之后,去除牺牲层。在牺牲层包括光刻胶材料的一些实施例中,例如,可以使用灰化工艺并且之后通过湿清洗工艺来去除牺牲层。随后,例如,使用合适的蚀刻工艺去除晶种层的暴露部分。
参考图10,使用粘合层1001将集成电路管芯1003附着至一个或多个介电层905。在一些实施例中,例如,使用贴片(pick-and-place)装置将集成电路管芯1003放置在一个或多个介电层905上。在其他的实施例中,手动或使用其他任何合适的方法将集成电路管芯1003放置在一个或多个介电层905上。在一些实施例中,粘合层1001可以包括LTHC材料、UV胶、管芯附着膜等,并且可以使用旋涂工艺、印刷工艺、层压工艺等形成。
在一些实施例中,集成电路管芯1003安装至一个或多个介电层905上,从而使得管芯接触件1005背向或远离一个或多个介电层905。管芯接触件1005提供至形成在集成电路管芯1003上的电路系统的电连接。管芯接触件1005可以形成在集成电路管芯1003的有源侧上,或者可以形成在背侧上并且包括通孔。管芯接触件1005还可以包括在集成电路管芯1003的第一侧和第二侧之间提供电连接的通孔。在一些实施例中,管芯接触件1005可以包括铜、钨、铝、银、金、锡、它们的组合等。在一些实施例中,可以使用诸如以上参考图1A至图3B所讨论的方法来形成集成电路管芯1003,并且可以包括诸如以上参考图4至图7所讨论的一个或多个对准标记。如以上所讨论的,使用一个或多个对准标记具有多种优势。例如,在将集成电路管芯1003安装至一个或多个介电层905上时,可以减少或避免集成电路管芯1003的不期望的偏移或旋转。此外,可以减少或避免由未对准而导致的对于集成电路管芯1003的损害。
参考图11,密封剂1101形成在载体901上方,并且形成在集成电路管芯1003和导电通孔907上方以及围绕该集成电路管芯和导电通孔。在一些实施例中,密封剂1101可以包括模塑料,诸如环氧树脂、树脂、可模制的聚合物等。可以在其基本为液态时应用模塑料,然后可以通过化学反应固化,诸如形成环氧树脂或树脂。在其他的实施例中,模塑料可以是紫外光(UV)固化聚合物或热固化聚合物,其可以以胶体或可塑固体形式施用且能够设置在集成电路管芯1003和导电通孔907周围以及它们之间。
还参考图11,在一些实施例中,使用CMP工艺、研磨工艺等或它们的组合来平坦化所得到的结构。在一些实施例中,执行平坦化工艺,直到暴露集成电路管芯1003的管芯接触件1005。在一些实施例中,管芯接触件1005的顶面与导电通孔907和密封剂1101的顶面基本共面。
参考图12,一个或多个再分布层(RDL)1201形成在集成电路管芯1003、导电通孔907和密封剂1101上方。在一些实施例中,RDL 1201包括一个或多个介电层1203和设置在一个或多个介电层1203内的一个或多个导电部件1205。在一些实施例中,一个或多个介电层1203可以包括介电材料,诸如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等,并且可以使用旋涂工艺等来形成。在一些实施例中,一个或多个导电部件1205可以包括铜、钨、铝、银、金等或它们的组合,并且可以电化学镀工艺、无电镀工艺、ALD、PVD等或它们的组合来形成。
还参考图12,凸块下金属件(UBM)1207形成在RDL 1201上方并与其电耦接。在一些实施例中,可以使用与以上参考图1A和图1B所述的UBM 111类似的材料和方法来形成UBM1207,因此本文不再重复描述。在一些实施例中,连接件1209形成在一些UBM 1207上方并与其电连接。在一些实施例中,可以使用与以上参考图1A和图1B所述的连接件113类似的材料和方法来形成连接件1209,因此本文不再重复描述。
集成电路管芯1211安装在RDL 1201上方并且与其电耦接。在一些实施例中,可以使用与以上参考图1A至图3B所述类似的方法来形成集成电路管芯1211,因此本文不再重复描述。在一些实施例中,集成电路管芯1211可以具有诸如以上参考图4至图7所述的一个或多个对准标记。在一些实施例中,使用集成电路管芯1211的连接件1213将集成电路管芯1211附着至UBM 1207。在一些实施例中,例如,使用贴片装置将集成电路管芯1211放置在RDL 1201上。在一些实施例中,贴片装置可以使用集成电路管芯1211的一个或多个对准标记来将集成电路管芯1211适当地对准至RDL1201上方。通过使用对准标记,可以减少或避免集成电路管芯1211的不期望的偏移或旋转。此外,可以减少或避免由未对准导致的对于集成电路管芯1211的损害。在其他的实施例中,手动或使用其他任何合适的方法将集成电路管芯1211放置在RDL 1201上。在示出的实施例中,集成电路管芯1211是分立的半导体器件芯片。然而,在其他的实施例中,集成电路管芯1211可以是提供期望的功能的任何合适的集成电路管芯。
在一些实施例中,在集成电路管芯1211安装在RDL 1201上方之后,所得到的结构从载体901脱离并且被分割以形成单独的集成电路封装件1215。在一些实施例中,可以通过锯切、激光切除方法等来切割所得到的结构。随后,可以测试每一个集成电路管芯1215以识别已知良好管芯(KGD)以用于进一步的处理。
参考图13,在一些实施例中,可以使用连接件1209将集成电路封装件1215接合至工件1301,从而使得集成电路管芯1211介于RDL 1201与工件1301之间。在示出的实施例中,工件1301是印刷电路板(PCB)。然而,在其他的实施例中,工件1301可以是集成电路封装件、一个或多个管芯、封装结构、中介片等。在一些实施例中,底部填充材料(未示出)可以注入或以其他方式形成在工件1301与集成电路封装件1215之间的空间中,并且围绕连接件1209和集成电路管芯1211。例如,底部填充材料可以是分布在各结构之间的液态环氧树脂、可变形的胶体、硅橡胶等,然后被固化以变硬。除此之外,底部填充材料可以用于减少对于连接件1209和集成电路管芯1211的损害并且保护该连接件和集成电路管芯。
图14是示出了根据一些实施例的形成集成电路封装件的方法1400的流程图。方法1400开始于步骤1401,其中,如以上参考图9所述,一个或多个介电层(诸如一个或多个介电层905)形成在载体(诸如载体901)上方。随后,如以上参考图9所述,导电通孔(诸如导电通孔907)形成在一个或多个介电层上方。在步骤1403中,如以上参考图10所述,第一集成电路管芯(诸如集成电路管芯1003)附着至一个或多个介电层。在步骤1405中,如以上参考图11所述,形成密封剂(诸如密封剂1101)以密封导电通孔和第一集成电路管芯。在步骤1407中,如以上参考图12所述,一个或多个再分布层(诸如RDL 1201)形成在密封的第一集成电路管芯和导电通孔上方。在步骤1409中,如以上参考图12所述,连接件(诸如连接件1209)形成在一个或多个RDL上方。在步骤1411中,如以上参考图12所述,第二集成电路管芯(诸如集成电路管芯1211)安装在一个或多个RDL上。在步骤1413中,如以上参考图12所述,所得到的结构从载体脱离并且被切割以形成单独的集成电路封装件(诸如集成电路封装件1215)。
根据实施例,一种方法包括:在第一工件的第一侧面上形成沟槽,第一工件的管芯插接在相邻的沟槽之间。去除管芯的一部分以形成对准标记,对准标记延伸穿过管芯的整个厚度。减薄第一工件的第二侧面,直到管芯被分割,第二侧面与第一侧面相对。
根据另一实施例,一种方法包括:在第一工件的第一侧面上形成第一凹槽,第一凹槽暴露管芯的侧面。在第一工件的第一侧面上形成第二凹槽以在管芯上形成对准标记,第一凹槽和第二凹槽具有相同的深度。减薄第一工件的第二侧面,直到管芯被分割,第二侧面与第一侧面相对。
根据又一实施例,半导体器件包括管芯。管芯包括衬底、衬底上的器件以及衬底和器件上方的介电层。半导体器件还包括管芯上的对准标记,对准标记完全延伸穿过介电层和衬底。
上面论述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。
Claims (10)
1.一种方法,包括:
在第一工件的第一侧面上形成沟槽,所述第一工件的管芯介于相邻的沟槽之间;
去所述除管芯的一部分以形成对准标记,所述对准标记延伸穿过所述管芯的整个厚度;以及
减薄所述第一工件的第二侧面,直到所述管芯被分割,所述第二侧面与所述第一侧面相对。
2.根据权利要求1所述的方法,其中,所述管芯是分立的半导体器件芯片。
3.根据权利要求1所述的方法,还包括:
使用所述对准标记将所述管芯与第二工件对准;以及
将所述管芯附着至所述第二工件。
4.根据权利要求3所述的方法,其中,所述第二工件是集成电路封装件,所述管芯附着至所述集成电路封装件的一个或多个再分布层(RDL)。
5.根据权利要求1所述的方法,其中,同时形成所述沟槽和所述对准标记。
6.一种方法,包括:
在第一工件的第一侧面上形成第一凹槽,所述第一凹槽暴露管芯的侧面;
在所述第一工件的第一侧面上形成第二凹槽以在所述管芯上形成对准标记,所述第一凹槽和所述第二凹槽具有相同的深度;以及
减薄所述第一工件的第二侧面,直到所述管芯被分割,所述第二侧面与所述第一侧面相对。
7.根据权利要求6所述的方法,其中,所述管芯是分立的半导体器件芯片。
8.根据权利要求6所述的方法,还包括:
使用所述对准标记将所述管芯与第二工件对准;
将所述管芯附着至所述第二工件;以及
将所述第二工件切割为单独的器件。
9.一种半导体器件,包括:
管芯,包括:
衬底;
器件,位于所述衬底上;和
介电层,位于所述衬底和所述器件上方;以及
对准标记,位于所述管芯上,所述对准标记完全延伸穿过所述介电层和所述衬底。
10.根据权利要求9所述的半导体器件,还包括:
第一工件,附着至所述管芯,所述第一工件包括:
密封的芯片;以及
一个或多个再分布层(RDL),位于所述密封的芯片上方,所述一个或多个RDL介于所述管芯与所述密封的芯片之间。
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