CN101827782B - 使用纳米结构连接和粘接相邻层 - Google Patents

使用纳米结构连接和粘接相邻层 Download PDF

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CN101827782B
CN101827782B CN200880107351.5A CN200880107351A CN101827782B CN 101827782 B CN101827782 B CN 101827782B CN 200880107351 A CN200880107351 A CN 200880107351A CN 101827782 B CN101827782 B CN 101827782B
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nanostructured
conductive
layer
adhering film
substrate
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CN101827782A (zh
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穆罕默德·沙菲奎尔·卡比尔
安杰·布鲁德
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Smoltek AB
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Smoltek AB
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Abstract

一种装置，包括两个导电表面或层、以及粘合到两个导电表面或层的纳米结构组件，从而在两个导电表面或层之间建立电或者热连接，以及一种制备同样组件的方法。

Description

使用纳米结构连接和粘接相邻层
技术领域
在此描述的技术涉及一种纳米结构，更具体地说，涉及使用纳米结构连接和粘接导电材料的相邻层。
背景技术
在电子器件的生产和制造中有许多实例，要求将例如一个组件中存在的材料层通常在特定的位置连接到例如晶圆(wafer)或者晶片(die)之类的基底上。在这样的实例中，连接的完整性，不论是机械的、热的或者是电的，对于器件的性能来说都是至关重要的。
这些例子包括：将倒装芯片连接或者粘接到衬底(基底，例如晶片)，在LCD制造中所使用的微细间距覆晶薄膜(fine-pitch chip-on-flex)技术；以及用于以微细间距建立电接触的晶圆级焊球(bump)。在所有这些应用中，目前的技术都受到严重的限制，这部分归因于对电子器件的小型化的需求渐增。
对“倒装芯片”技术的使用正在快速增长，该技术目前用于例如移动电话、MP3播放器、智能卡、显示器、计算机外围设备之类的设备中。但是，在复杂性和产品成本方面，倒装芯片技术存在缺陷，这归因于需要复杂的工艺，包括将芯片粘接和连接到晶片上。这些工艺包括焊料熔融镀覆(solder fluxcoating)、芯片/板的设置、焊球回流工艺(solder bump reflow process)、焊剂清除工艺、底层填料、以及固化工艺(cure process)。
用于粘接和连接倒装芯片的技术正朝向增加更多数量的I/O触点、触点之间的间距也越来越小的方法发展。参见例如Peter J.Opdahl的“AnisotropicConductive Film for Flipchip Applications：An Introduction”，可在以下网址找到：www.flipchips.com/tutorial05.html，通过全文引用合并于此。
作为球焊(solder bumping)的替代方案，已经出现了异方性导电膜(ACF)，它作为无铅、环保、无焊剂的粘接解决方案，由分散在聚合物基中的导电微粒组成，该聚合物是例如带粘性的树脂。ACF通过将导电微粒包裹在一个导电表面(例如，倒装芯片上的导电焊球)和另一个导电表面(例如与倒装芯片上的导电焊球对应的基底上的导电焊盘)之间来起作用，而相邻的微粒之间彼此绝缘。
在最近的几十年中，ACF已经被广泛用于平板显示器行业的封装技术，从而电气和机械地将集成电路驱动器连接到显示器的玻璃基底上。最近，已经证明ACF是其它直接芯片连接技术的流行替代方案，以满足在更小尺寸下更精细的间距要求。对于ACF材料来说，这意味着要使导电微粒尽可能小、产生更高的微粒密度、并确保微粒在ACF中极其平均地分布。此外，聚合物基的流动必须被尽可能好地控制。目前，3.5μm的小尺寸微粒被用于要求苛刻的应用中。
长久以来，已经意识到ACF受到许多限制。如果微粒过大，或者有太多的微粒，将会在倒装芯片上的两个相邻焊球之间产生短路的危险。这意味着对微粒之间可能最小的间距有限制，因为如果微粒彼此太靠近，短路的危险会增加。这在例如显示器行业特别明显，其中当发生短路时会出现黑点。由于没有办法能够准确预知微粒在聚合物基中分布的均匀度，因此短路的风险会一直存在。避免由于微粒导致的短路的风险的影响在于，触点(I/O触点)的最大可能数量受到限制，因此当使用ACF连接倒装芯片时，最大可能间距受到限制。
覆晶薄膜(Chip On Flex，简称COF)是相关的技术，也利用ACF，随着对更小间距产品的要求增加(目前的产品是小于40-50μm)、以满足成本和尺寸的要求，产生了与“倒装芯片”技术类似的问题(特别是LCD行业)。采用目前的粘接工艺，在精细间距的COF封装中存在两个主要问题：引线断裂(leadbreakage)和失配(misalignment)。
由于组装过程中在任何情况和任何位置都可能发生引线断裂，视觉检查几乎是不可能的。当两个导电表面之间缺少被包裹的导电微粒时，可能发生引线断裂；被包裹的微粒数少于一个，极可能产生电连接开路，这将会导致电气故障。为了避免这个问题，必须增加微粒密度，这通过减少微粒的直径来实现。如果COF的脚距是40μm，可使用微粒直径小于3μm的异向性导电粘接剂(ACA)，以获得几率为99.5％的良好电连接(至少一个被包裹的微粒)。
但是，即使在较高的连接完整性的几率下，误差幅度也不能被忽略。例如，对于带有400个焊球(bumps)的封装，五个芯片中的一个可能会有断开的(未连接的)焊球/引线连接(lead joint)。此外，如果焊球和引线之间的间隙变化幅度超过3μm可能会发生开路连接故障，即使采用带有被包裹微粒的正常连接。因此，总的来说，将异向性导电粘接剂(ACA)应用于精细间距的COF互连要求减少微粒尺寸，并更精确地控制焊球/引线高度和芯片/薄膜共面程度。
对于更精细的引线间距，失配也成为更大的风险，因为更精细的间距要求以更高的精度控制薄膜和导电表面之间的对准。现有的公差要求最终会被新的标准替代，以得到满意的产量。COF组装过程中失配的原因是各种各样的，可能存在于薄膜、芯片、粘接设备等等。粘接公差与变化特性相关。
因此，ACF的主要问题可以总结如下：(1)需要均匀分布的微粒尺寸；(2)需要控制粘接压力，以破坏微粒的表面镀层从而产生接触；(3)在微粒的分布方面对微粒的尺寸限制-不能降至亚微米级；以及(4)制造限制-不能在亚微米级以良好的可再现的均匀度进行制造。因此，需要更好的方式在芯片和基底之间建立连接，并将芯片连接到基底上。
晶圆级焊球受到类似的关注。采用“焊球”以更小的尺寸和更精细的间距通过分布或者接触通道产生电接触，要求更高重现度的制造工艺。电连接由焊球建立，但是对这些焊球的尺寸有限制；采用当前的制造工艺不可能降至亚微米级，这受到每单位面积焊球数量的限制。因此，大量的分布通道受到产生焊球的限制。
在此讨论的背景技术用以解释技术的上下文。这并不认为承认所提及的任何材料都是在后附的所有权利要求的优先权日前公开的、已知的或者是公知技术的一部分。
在说明书的描述和权利要求中，词语“包括”及其变化形式，例如“-ing”形式和“-s”形式，并不用于排除其它附加物、组件、整体或者步骤。
发明内容
本说明书公开了一种装置，包括：第一导电表面；第二导电表面；以及两个或更多纳米结构，其中所述两个或者更多纳米结构中的每一个的方向都平行于所述两个或者更多纳米结构中的其他纳米结构，其中所述两个或者更多纳米结构包括两种或更多互相扩散的材料，所述两种或更多互相扩散的材料包括影响所述两个或更多纳米结构的形态的至少一种材料、以及影响所述第一导电表面之间的界面的电特性的至少一种材料，其中所述两个或更多纳米结构的每一个的第一端与所述第一导电表面之间存在第一粘接点，所述两个或更多纳米结构的方向与所述第一导电表面垂直，所述两个或更多纳米结构的每一个的第二端与所述第二导电表面之间存在第二粘接点，所述两个或更多纳米结构的方向与所述第二导电表面垂直。
一种使用纳米结构组件(assembly)将第一导电表面连接到第二导电表面的方法，所述方法包括：通过以下方式产生纳米结构组件：将一个或者多个中间层沉积在导电基底上，其中所述多个中间层的至少一个包括从下组中选择的材料：非晶硅和锗；将催化剂层沉积在所述一个或多个中间层上；不对基底进行第一次退火，使基底被加热至可以形成纳米结构的温度，在该温度下在催化剂层上生长两个或更多纳米结构，其中所述一个或更多中间层中的至少一个与所述催化剂层相互扩散，其中相互扩散的所述催化剂层和所述一个或更多中间层的至少一个出现在所述纳米结构中；使用粘性聚合体旋转镀覆所述纳米结构组件以形成带有内嵌纳米结构的薄膜；打磨所述薄膜以实现所述纳米结构组件的所述两个或更多纳米结构的均匀一致的期望长度；切割所述薄膜以产生一个或多个单独的衬板(pad)；将所述衬板从所述导电基底上提起；将所述一个或多个衬板插入所述第一导电表面和所述第二导电表面之间；将所述一个或多个衬板固化，从而将所述第一导电表面粘接到所述一个或多个衬板的第一表面，并将所述第二导电表面粘接到所述一个或多个衬板的第二表面。
一种使用纳米结构组件将第一导电表面连接到第二导电表面的方法，所述方法包括：通过以下方式产生纳米结构组件：将一个或者多个中间层沉积在第一导电表面上，其中所述多个中间层的至少一个包括从下组中选择的材料：非晶硅和锗；将催化剂层沉积在所述一个或多个中间层上；不对基底进行第一次退火，使基底被加热至可以形成纳米结构的温度，在该温度下在催化剂层上生长两个或更多纳米结构，其中所述一个或更多中间层中的至少一个与所述催化剂层相互扩散，其中相互扩散的所述催化剂层和所述一个或更多中间层的至少一个出现在所述纳米结构中；使用粘性聚合体旋转镀覆所述纳米结构组件以在所述第一导电表面上形成带有内嵌纳米结构的薄膜；打磨所述薄膜以实现所述纳米结构组件的所述两个或更多纳米结构的均匀一致的期望长度；切割所述薄膜和所述第一导电表面以产生一个或多个单独的衬板，每个衬板包括薄膜部分和第一导电表面部分；将所述一个或多个衬板应用于所述第二导电表面；以及将所述一个或多个衬板固化，从而将所述第二导电表面粘接到所述一个或多个衬板的表面。
一种使用纳米结构组件将第一导电表面连接到第二导电表面的方法，所述方法包括：通过以下方式产生纳米结构组件：沉积一个或多个中间层，在所述一个或多个中间层上沉积催化剂层；不对基底进行第一次退火，使基底被加热至可以形成纳米结构的温度，在该温度下在催化剂层上生长两个或更多纳米结构，其中所述一个或更多中间层中的至少一个与所述催化剂层相互扩散，其中相互扩散的所述催化剂层和所述一个或更多中间层的至少一个出现在所述纳米结构中；使用金属沉积物镀覆所述纳米结构，以在所述第一导电表面上形成镶嵌金属的纳米结构；使用粘性聚合体旋转镀覆所述纳米结构组件以在所述第一导电表面上形成带有内嵌纳米结构的薄膜；打磨所述薄膜以实现所述纳米结构组件的所述两个或更多纳米结构的均匀一致的期望长度；切割所述薄膜和所述第一导电表面以产生一个或多个单独的衬板；每个衬板包括薄膜部分和第一导电表面部分；将所述一个或多个衬板应用于所述第二导电表面；以及将所述一个或多个衬板固化，从而将所述第二导电表面粘接到所述一个或多个衬板的表面。
附图说明
图1：使用矩阵中的碳纳米纤维将晶片与基底粘接和电接触的原理；
图2：固化前、使用矩阵中的碳纳米纤维将晶片与基底粘接和电接触；
图3A、3B：固化后、使用矩阵中的碳纳米纤维将晶片与基底粘接和电接触；
图4：矩阵中的碳纳米纤维的俯视图；
图5：带有I/O衬板的矩阵中的碳纳米纤维的俯视图；
图6：带有I/O衬板的矩阵中的碳纳米纤维的横截面图；
图7：如本说明书中所描述的过程的流程图；
图8：如本说明书中所描述的过程的流程图；
图9：如本说明书中所描述的过程的流程图。
具体实施方式
本发明的技术涉及一种通过将纳米结构粘接到两个表面或者层的接触位置、从而在两个表面或者层之间产生机械、电或者热连接的方法。通过该方法，接触位置的间距可以位于2nm至1mm的范围内。本发明的技术还包括一种装置，包括第一导电表面或者层、第二导电表面或者层、以及粘接并位于两个导电表面或层之间的纳米结构组件，使得纳米结构组件的纳米结构的方向与两个导电表面或者层垂直。
在该技术的另一方面，通过在形成于基底上的金属衬底上生长纳米结构(例如碳纳米结构(CNS))，来形成粘接层。该基底可包括一个或多个金属层、半导体层、或者绝缘层、或者它们的组合。纳米结构垂直于基底表面生长。该纳米结构可以镀覆于聚合体之类的载体中，例如粘性聚合体。该载体可以是聚酰亚胺，或者可以是柔性或者固体材料。可选地，被镀覆或者未被镀覆的纳米结构可以被打磨以提供均匀一致的长度。得到的结构可以被切割成单个薄膜。可选地，聚合体和纳米结构的薄膜可以从基板上提起。然后薄膜可以被应用于晶片的表面，以提供晶片接触。
在该技术的另一方面，晶片粘接层可包括纳米结构，例如碳纳米结构(CNS)，设置在聚合体镀覆层中。该纳米结构垂直延伸到该层的顶部和底部表面。该纳米结构可以被分组，同一组中的纳米结构间隔固定距离，组之间的纳米结构间隔另一(更大的)固定距离。同一组的纳米结构可以通过放置得与共同的电极直接接触来实现电连接，也可以通过生长在多个金属衬层(电耦合的)上来实现电连接。与之形成对照的是，分开的各组的纳米结构之间是电绝缘的。
当此处使用“垂直”来描述纳米结构和层表面之间的方向时，应该理解，纳米结构是线、管、或者纤维、或者类似结构的形式，具有沿着其长度方向延伸的纵轴，该纵轴设置得垂直于该层或者表面所在的平面。还应理解，“垂直”包括与精确的垂直有微小的偏差，例如纵轴相对于平面的倾斜度为88-90°，或者相对于平面的倾斜度为85-90°。
在某些实施例中，所述纳米结构通常是刚性的，使得包括它们的层通常是不能压缩的。
纳米结构的例子包括但不限于纳米管、纳米纤维、或者纳米线。特别地，此处的纳米结构可以由碳基纳米结构制成，例如碳纳米管、碳纳米纤维、或者碳纳米线。
此处描述的纳米结构也可以由其它材料制成，例如金属、III-V、II-VI化合物、或者元素周期表的元素的组合。材料的例子包括半导体，例如GaAs、InP、InGaAs、AlGaAs，纳米线例如硅纳米线，合金例如ZnO、ZnAlO、以及可以形成纳米结构的任何其它二元或三元合金。
与此处的应用相关的纳米结构可以生长/形成/沉积在基底上，所述基底例如硅、多晶硅、氧化硅、硅氮化物、锗、硅-锗、GaAs、AlGaAs、GaN、InP、玻璃、聚酰亚胺、聚合体，金属例如W、Mo、Ti、Cr、NiCr、Al、AlOx、Pt、Pd、Au、Cu、TiN、或者元素周期表中的任何其它金属，塑料、铝箔、铝、纸、以及高k材料，例如HfO、ZrO等。对于纳米结构的生长，催化剂可以是Ni、NiCr、Pd、Pt、Fe、Au、Co、或者这些金属的组合、或者不同材料的合金，例如双金属催化剂，例如Co-V、Co-Ni、Fe-Ni等。
化学气相沉积(CVD)是生长纳米结构以供在此描述的技术使用的典型方法。但是有不同种类的CVD方法可以使用，例如，热CVD、PECVD、RPECVD、MOCVD(金属有机CVD)等、或者本领域技术人员所了解的任何其它CVD的变化形式。生长的特殊方法在申请号为11/412,060、名称为“Controlled Growthof a Nanostructure on a Substrate”、2006年4月25日申请的美国专利中进行了描述，通过引用其全文合并于此。
此外，可以使用一旦形成就允许控制纳米结构的各种特性的条件、用各种方法和材料来形成此处的纳米结构。因此，此处使用的纳米结构包括从基底上生长的纳米结构、以及位于其间的界面层，并具有以下特征。基底优选导电层例如金属层，且可以设置在支撑物上。该支撑物通常是硅晶圆或者其它半导体材料、玻璃或者在薄膜技术中使用的柔性聚合体。该金属优选地从以下这组金属材料中选择：钼、钨、铂、钯、和钽。金属层的厚度优选在1nm至1μm的范围内，更优选地在1nm至50nm的范围内。金属层优选地通过该技术领域中已知的几种方法中的任何一种沉积，包括但不限于：蒸发法例如热或者真空蒸发、分子束外延、以及电子束蒸发；辉光放电方法例如本技术领域已知的几种溅射法中的任一形式，等离子加工例如等离子增强化学气相沉积(plasma-enhanced CVD)；以及化学加工包括气相加工(比如化学气相沉积)、离子注入，液相加工(比如电镀)，以及液相外延。沉积技术的例子可参照Handbook of Thin Film Deposition，K.Seshan，Ed.，Second Edition，(William Andrew，In，2002)。
界面层(也称为中间层)包括一个或多个层，依次沉积在基底上。在界面层上面是催化剂层。纳米结构生长在催化剂层上面。
界面层可简单地由单层材料构成。在此情况下，该单层材料可以是硅或者锗。这些层可以用蒸发、溅射等技术以无定形或者晶体形式沉积。厚度通常在1nm到1μm之间，也可以在1nm到50nm之间。
界面层可含有多个不同材料的层，而且可以根据功能任意分类。比如，邻近基底的层具有影响界面电学特性的特征。邻近催化剂的层具有影响纳米结构的成分以及特性(比如电学/力学特性)的特征。
不同结构的界面层和本发明都相容。比如，可以在基底上沉积多达三层的层序列，用来控制界面的电学性质。这类配置包括(但不仅限于)：绝缘体、导体或半导体、和绝缘体的序列；邻近基底的绝缘体、和半导体层序列；半导体、绝缘体、半导体的序列；邻近基底的两个绝缘体势垒层、和半导体序列；和基底的金属不同的金属单层；和基底的金属不同的金属、以及半导体层序列。在此类配置中，绝缘体从下组材料中选择：SiOx，Al2O3，ZrOx，HfOx，SiNx，Al2O3，Ta2O5，TiO2，以及ITO。半导体可为硅或者锗。若有金属则可为钯、铂、钼、或者钨。在有两个具有同样特性的层的情况下，比如两个半导体层，该两层不需要含有相同的成分。
前述界面层的最上一层紧靠催化剂层。当最上层是半导体(比如硅或锗)时尤其如此。然而，还有可能在前述界面层上，界面层与催化剂层之间另外再加一层或者一序列的层。这类另加的或者第二个界面层被视为用来控制纳米结构的特性和成分。第二界面层可含有一对层，比如金属层和在其上的半导体层，其中半导体层接近催化剂层。另一个选择是：第二界面层也可以仅含有半导体单层。在第二界面层中的金属层在下列材料中选择为宜：钨、钼、钯、铂。在第二界面层中的半导体层是硅或锗为宜。
通常催化剂层是一层金属或者金属合金，可以包含金属或金属合金微细颗粒而不是连续薄膜。催化剂层含有从下列材料中选择的金属为宜：镍、钯、铁、镍铬合金(镍和铬的任意比例混合)和钼。
纳米结构通常具有在催化剂层和导电基底之间有至少一个材料层的叠层配置，其中的材料与催化剂和导电基底的材料不同，其中材料控制各层之间的化学反应。因此，可以控制纳米结构在不同导电基底上的生长。因此生长的纳米结构的形态和特性以及生长的纳米结构的尖端材料(tip material)可以得到控制。本技术可以拓展到含有几个不同类材料(半导体材料、铁电材料和磁性材料等等)的叠层，以控制基底/界面、纳米结构的主体和尖端的性质。并且也可能从直接沉积在基底(可以是任意种类，比如导电的、绝缘的、半导体的)上的导电层上生长纳米结构。
通常，在这样的纳米结构的生长过程中，中间层的材料有时会扩散到纳米结构中。这样的扩散可以将中间层的材料一直传送到所生长的纳米结构的尖端。在某些情况下，所扩散的材料出现在窄带中，在其它情况下，所扩散的材料遍布纳米结构。
在此描述的方法可应用于包含模拟和/或数字电子电路的电子元器件的任何组件技术。例如，这样的元器件件可以在以下产品中找到：通信工程、汽车/工业电子商品、消费电子、计算、数字信号处理和集成产品。连接技术(例如球栅阵列(BGA)、倒装芯片(FC)模块、CSP、WLP、FCOB、TCB)可利用此处的方法。集成电路(IC)类型例如RFID、CMOS、BiCMOS、GaAS、AlGAAs、MMIC、MCM可利用此处描述的方法。显示技术例如LCD、LED和OLED(如用在汽车、计算机、移动电话手持机、以及电视的那些)也可以结合此处描述的方法所做的连接。类似地，结合了这些技术的其它的电子元器件包括但不限于：ASIC芯片、存储器件、MCU、高频器件模块、集成的无源元件。
在此描述的方法也可以被用于建立互连、散热通道或者热导体或者非热导体、感应器、电容器和电阻器，使得它们从该技术获益，在两个材料层之间建立连接。该方法还可以被用于光电器件，例如光子晶体、波导、滤波器、光电电路等。这个方法还可以被用于生物学器件，或者混合生物和硅基器件，例如芯片实验室阵列、以及生物诊断学的探测器。
结构
在此描述的过程产生的装置包括载体，该载体内嵌有纳米结构，其中纳米结构生长得具有特定的形态和功能。该纳米结构的方向大致为彼此平行并垂直于基底。该纳米结构具有近似于期望的长度或高度。
图1-8示意性地示出了在此描述的方法和装置(apparatus)。应当理解，虽然图1-8l图示了使用碳纳米结构(CNF)，但是也可类似地使用其它形式的纳米结构。这样可选的纳米结构包括但不限于：纳米管、纳米线和纳米绳。这样的纳米结构可以由碳制成，掺杂有一种或多种其它元素，但不限于此。
图1示出了使用矩阵中的碳纳米纤维的衬板、使两个相邻的金属层粘接和电接触(例如将晶片连接到基底上)的总体原理。在图1中示出了三层：带有内嵌的接触衬板(contact pad)110的基底100，位于基底顶面上的是一层粘性聚合体200，粘性聚合体200包围许多垂直于基底100的碳纳米纤维(CNF)210，且一些碳纳米纤维210与接触衬板110接触，位于粘性聚合体层上方的是器件层300。器件层300包括与多个碳纳米纤维相连的I/O衬板(I/Opad)310、由例如钨制成且位于I/O衬板上方的的第一金属插头320、以及位于第一插头上方的第二金属插头330。插头320、330彼此不同、可以由钨或者在该行业内使用的其它金属制成，例如铝、铜、或者金。
图2示出了在固化前、使用矩阵中的碳纳米纤维将晶片与基底粘接和电接触的示意图，为了方便图示，在图2中仅示出了单个CNF。
图3A、3B示出了固化后、使用粘性聚合体矩阵中的碳纳米纤维将晶片与基底粘接和电接触(为了方便描述，在图3A中仅示出了单个CNF)的示意图。双箭头220表示在CNF中引起“弹性负载”的伸直力。两个单箭头230指示固化引起的收缩粘合力。
图3B示出了固化后、使用矩阵中的碳纳米纤维将晶片与基底粘接和电接触的示意图。双箭头220表示在CNF中引起“弹性负载”的伸直力。两个单箭头230指示固化引起的收缩粘合力。
图4示出了矩阵中的碳纳米纤维阵列的俯视图。图中示出了代表性的间距。相邻纳米结构之间的间距是200nm；阵列的尺寸是600nm；纳米纤维的直径是50nm。
图5示出了矩阵中的碳纳米纤维阵列的俯视图，该矩阵带有覆盖纳米结构的子集的I/O衬板。图中示出了代表性的间距。相邻纳米结构之间的间距是200nm；阵列的尺寸是600nm；纳米纤维的直径是50nm；I/O衬板的直径是400nm。
本技术领域的人员应当理解，图4和图5所示的间距是示范性的，此处的技术的操作并不依赖于如图所示的这些间距的精确数值。
图6示出了带有如图5所示的I/O衬板的矩阵中的碳纳米纤维的横截面图。一些纳米结构连接接触衬板和I/O衬板，而其它纳米结构设置在衬板的区域外，如图所示，这些其它纳米结构并不必延伸贯穿粘合层的整个厚度。
例子1：使用纳米结构和ACF产生接触的过程
这个例子提供了一种连接两个表面/层的方法(例如，第一晶片或芯片的接触表面/层与第一晶片或芯片即将连接的第二晶片或芯片的接触表面/层)。该连接通过粘合以及电/热接触来实现，其间距的范围在1mm至2nm，通常下至20nm，其中电/热接触单元基于纳米结构。
遵照本方法的结构包括：(a)载体层(例如基于柔性或者固体材料，例如聚酰亚胺)，(b)内嵌在载体中且具有特定的形态和功能的纳米结构，其中纳米结构彼此平行并垂直于载体的两个表面；以及(c)其中纳米结构可以根据国际专利申请PCT/SE2006/000487(通过引用合并于此)中描述的方法来生长，以实现对其形态、尺寸、长度、距离等的控制。
在此处使用的典型纳米结构组件包括：导电基底(例如金属)；位于导电基底上的第一催化剂层；被第一催化剂层支撑的纳米结构；以及位于导电基底和第一催化剂层之间的多个中间层，该多个中间层包括至少一个影响纳米结构的形态的层和至少一个影响导电基底和纳米结构之间界面的电特性的层。
该结构的特征包括：接触单元(纳米结构)垂直于连接表面，而纳米结构彼此平行。可以根据生长方法来定制纳米结构的特性。每个单元都可以与其它这样的单元合并，以组合成另外的结构，与积木相似，类似于乐高(Lego)积木。
图7示出了通过粘合和建立电或热接触(包括纳米结构)，连接两个表面或者层的示范性过程的步骤。该步骤包括：在导电基底上生长碳纳米结构层，在导电基底和纳米结构之间有多个中间层(701)；采用粘性聚合体旋转镀覆(spincoating)所得到的纳米结构，以形成内嵌有纳米结构的薄膜(702)；打磨薄膜以实现纳米结构的均匀一致的期望长度(703)；切割薄膜以产生单独的衬板(704)；提起衬板(705)；将每个衬板应用于第一导电表面或层(例如，晶片的表面)与第二导电表面或层(例如，芯片的接触面)之间(706)；以及固化衬板，使得晶片被粘合到衬板上，且衬板被粘合到接触表面，从而通过内嵌在衬板中的纳米结构实现晶片和接触表面之间的电或热接触(707)。
第一步骤(701)在导电基底上生长碳纳米结构层，且导电基底和纳米结构之间有多个中间层，该步骤包括通常以密度大于10纳米结构每μm的密度生长纳米结构。这样的密度，或者在给定请况下所要求的密度可以通过控制催化剂点在基底上的应用来实现。优选使用各种基于CVD方法的任意一种来生长纳米结构，但是也可以使用任何标准的技术来生长或者形成纳米结构。
第二步骤(702)采用粘性聚合体旋转镀覆所得到的纳米结构，以形成内嵌有纳米结构的薄膜，该步骤可以使用任何标准的旋转镀覆或者为纳米结构形成载体(在薄膜或者其它层中)的等同技术来完成，其中纳米结构内嵌在载体中。这样的载体可包括粘性聚合体或者能够通过固化、压力、热或者其它等同处理粘合到晶片和接触表面的任何其它等同材料。在此描述的方法并不限于旋转镀覆的示范性实施例或者使用可以被固化的粘性聚合体的示范性实施例。
第三步骤(703)打磨薄膜以实现纳米结构的均匀一致的期望长度，该步骤可以使用适合于本发明的技术的任何标准打磨技术来实现，无论是机械的、化学或者其它。类似地，可以使用该技术或相关技术中已知的或者使用的任何标准技术来确定纳米结构是否获得了均匀一致的期望长度。这个步骤是可选的。
第四步骤(704)切割载体以产生单独的衬板，该步骤可使用任何切割的标准技术或者其它产生期望形状和尺寸的单个衬垫的技术来实现。
第五步骤(705)提起单独的衬板(薄膜部分包括内嵌在粘性聚合体内的垂直排列的碳纳米结构)，该步骤可以使用提起这种衬板的任何标准技术来完成。
第六步骤(706)将每个衬板应用于第一导电表面(例如，晶片的表面)与第二导电表面(例如，芯片的接触面)之间，该步骤可以使用将这样的衬板应用和定位于这样的位置的任何标准技术来完成。
第七步骤(707)固化衬板，其结果是产生粘合，其中衬板夹在并且粘合在两个导电表面之间。通过内嵌在衬板中的纳米结构，这种粘合在两个导电表面之间产生电接触和热接触。这个步骤并不限于固化粘性聚合体，它可以包括使得内嵌在衬板中的纳米结构与衬板一侧的晶片以及衬板另一侧的接触表面产生粘合的任何标准技术。
该全部过程具有几个优点：不需要传统的焊球，减少了两个导电表面之间的最小可能间距，降低了接触点的高度和宽度，允许增加接触点的数量和密度、减少了与需要控制应用于ACF的压力强度相关的复杂性，使能通过用纳米结构代替颗粒(particle)可以得到更小的间距，并减少了失配的危险。
遵照该例子，可控制每微米的纳米结构(NS)的密度，与基于球状颗粒的现有解决方案相比，这允许增加有效的接触点。例如，100NS/平方微米(纳米结构的直径为50nm)具有100个单独的接触点(也可参照图4和图5)。给定I/O点的尺寸为20×20微米，在该区域内单个接触点的数量可以是4000。
例子2：产生弹性负载连接的过程
包括垂直排列纳米结构(NS)(彼此平行且垂直于两个载体表面，如例子1中所描述的步骤制备的那样)的载体(可以基于柔性、聚酰亚胺或者固体材料)放置于晶片的表面和接触表面之间。参照图2和图4作为例子。
通过将包括垂直排列的纳米结构的载体固化(使用热或者化学成分或者光)，载体将会收缩(晶片和接触层之间的距离下降)。
载体的收缩将会在垂直排列的纳米结构上引入收缩力，纳米结构上的收缩力的结果是纳米结构轻微弯曲。但是由于纳米结构和周围材料之间的杨氏模量的差别，纳米结构将会有伸直的趋势。
上述的力在纳米结构中产生“弹性负载”力。当内嵌在载体材料中的纳米结构放置在两个导电表面之间时，弹性负载力将会加固与纳米结构的两端的接触(例如参照图3A和3B)。
图8示出了通过将晶片粘合到基底以提供弹性负载连接、以及通过使用内嵌在载体中的纳米结构来建立和加固电接触的过程。图8的步骤与结合例子1描述的图7的步骤相同，此处不再重复。
第六步骤(806)中，对带有内嵌纳米结构的载体的衬板进行固化，固化过程可以采用热、或者化学成分或者光使得载体收缩，从而减少晶片和接触层之间的距离。
此处，可以根据与例子1中的纳米结构的相同方法，来制备该例子中的纳米结构，特别地，可以根据国际专利申请PCT/SE2006/000487(通过引用合并于此)中描述的方法来生长该例子中的纳米结构，从而控制形态、尺寸、长度、距离等。
该例子中描述的过程可以被用于解决覆晶薄膜应用中出现的引线断裂和失配问题。
与例子1中的结构类似，弹性负载结构的特性包括：接触单元(纳米结构)垂直于连接表面，而纳米结构彼此平行。可以根据生长方法来定制纳米结构的特性。每个单元可以与其它这样的单元组合，以组合成其它的结构。
该全部过程具有几个优点：减少两个导电表面之间的最小可能距离，降低接触点的高度和宽度，允许增加接触点的数量和密度从而增加有效接触面积，减少了与需要控制应用于ACF的压力大小相关的复杂性，通过用纳米结构代替颗粒(particle)可以得到更小的间距，减少了失配的风险，并使用轻微弯曲的纳米结构加固了位于相对表面之间的两个点之间的电接触。当纳米结构轻微弯曲时，可以减少由于粘合表面的表面粗糙度而产生的间隙。
遵照该例子，可控制每微米的纳米结构(NS)的密度，与基于球状颗粒的现有解决方案相比，这允许增加有效的接触点。例如，可控纳米结构的直径范围从1nm到200nm，这给出了预定的单个接触点和每平方纳米的接触面积。
例子3：晶圆级焊球(wafer lever bumping，WLB)
这个例子解释了如何通过在电子电路上的I/O点上生长纳米结构矩阵，来实现晶圆级焊球，从而为晶片产生电子组件。该方法可以是通过粘合、以及电和/或热接触来连接两个表面/层(晶片或芯片的接触表面/层、以及第一层即将连接的晶片或芯片的接触表面/层)的方法，其中间据是范围为1cm至2nm的任何间距，通常下降至1μm，其中电/热连接元件基于纳米结构。
以下三个案例解释了可能的实施例：
案例1：垂直排列的纳米结构生长在晶圆的集成电路的I/O点上，从而产生矩阵结构，并内嵌在具有粘性特性的可固化(在UV/激光/光)材料中，该矩阵对应于晶片需要连接的基板上的连接点。
案例2：垂直排列的纳米结构生长在晶圆的集成电路的I/O点上，从而产生矩阵结构，该矩阵对应于晶片需要连接的基板上的连接点，通过传统的高温焊接工艺进行连接。
案例3：垂直排列的纳米结构生长在晶圆的集成电路的I/O点上，从而产生矩阵结构，该矩阵对应于晶片需要连接的基板上的连接点。
一般来说，与例子2和3的结构类似，晶圆级焊球结构的特性包括：接触单元(纳米结构)垂直于连接表面，而纳米结构彼此平行。可以根据生长方法来定制纳米结构的特性。垂直排列的纳米结构可以形成连接结构组，尺寸从1mm至2nm。
此处，这个例子中的纳米结构可以根据与例子1和2中的纳米结构相同的方法制作，特别地，可以根据国际专利申请PCT/SE2006/000487(通过引用合并于此)中描述的方法来生长，从而控制形态、尺寸、长度、距离等。
图9示出了提供晶圆级焊球的过程。图9的步骤与结合例子1和2描述的图7和8的步骤相同，此处不再重复。
在目前的系统中，焊球可以具有500微米及以下的直径。这个例子的方法允许组装多组纳米结构，每个单独的组具有与现今的焊球相同的尺寸。但是，本技术还允许更小的焊球，甚至小至包括单个纳米结构的焊球。
基于此处描述的那些方法，可以形成复合焊球。必要时，在生长纳米结构形成符合焊球以后，可以执行标准的蒸发、电镀和/或化学镀覆。在生长纳米结构以后，可以蒸发、电镀和/或无电镀覆元素周期表中的不同金属/金属材料，例如Ti、Cr、TiW、Cu、Au或者任何其它合适的金属。必要时，也可以执行标准的浸金工艺，以进行镀金。无电镀覆工艺可以包括修整、酸刻蚀、通过不同的化学成分镀覆不同的金属，例如，Ni、Cu、Zn、Sn或者不同的合金。

Claims (6)

1.一种粘接薄膜(bonding film)，其特征在于，用于通过所述粘接薄膜将第一导电表面和第二导电表面互连，
其中所述粘接薄膜包括内嵌在聚合体载体中的多个纳米结构；
所述纳米结构的朝向彼此平行，且垂直延伸至所述聚合体载体的顶面和底面；
其中所述聚合体载体被配置成：
当设置在所述第一导电表面和所述第二导电表面之间时，黏附在所述第一导电表面和所述第二导电表面上；以及
当固化时收缩，从而在所述纳米结构内提供弹性负载力，从而在所述纳米结构与所述第一导电表面之间和所述纳米结构与所述第二导电表面之间形成可靠接触。
2.根据权利要求1所述的粘接薄膜，其特征在于，所述纳米结构的每一个都包括两种或多种互相扩散的材料，所述两种或多种互相扩散的材料包括至少一种影响所述多个纳米结构的形态的材料、以及至少一种影响所述多个纳米结构的电学特性的材料。
3.根据权利要求2所述的粘接薄膜，其特征在于，所述两种或多种互相扩散的材料中的至少一种材料出现在所述纳米结构的每一个的尖端处。
4.根据权利要求2或3所述的粘接薄膜，其特征在于，所述两种或多种互相扩散的材料中的至少一种材料从下组中选择：非晶硅和锗。
5.一种电子器件，其特征在于，包括：
具有导电表面的电子组件；
具有导电基底表面的基底；以及
根据权利要求1-4中任一项所述的粘接薄膜，设置在所述导电组件表面与所述导电基底表面之间，
其中包括在所述粘接薄膜中的所述聚合体载体处于固化状态，使得包括在所述粘接薄膜中的所述纳米结构通过弹性负载力抵压在所述导电组件表面和所述导电基底表面。
6.一种将具有导电组件表面的电子组件与具有导电基底表面的基底互连的方法，其特征在于，所述方法包括以下步骤：
将根据权利要求1-4中任一项的粘接薄膜设置在所述导电组件表面与所述导电基底表面之间；以及
固化包括在所述粘接薄膜中的所述载体，为包括在所述粘接薄膜中的纳米结构提供弹性负载力，从而在所述纳米结构与所述导电组件表面之间和所述纳米结构与所述导电基底表面之间实现可靠的接触。
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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687876B2 (en) * 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US7777291B2 (en) * 2005-08-26 2010-08-17 Smoltek Ab Integrated circuits having interconnects and heat dissipators based on nanostructures
JP5535915B2 (ja) * 2007-09-12 2014-07-02 スモルテック アーベー ナノ構造体による隣接層の接続および接合
JP5474835B2 (ja) 2008-02-25 2014-04-16 スモルテック アーベー ナノ構造処理のための導電性補助層の形成及び選択的除去
US8568027B2 (en) 2009-08-26 2013-10-29 Ut-Battelle, Llc Carbon nanotube temperature and pressure sensors
US20110076841A1 (en) * 2009-09-30 2011-03-31 Kahen Keith B Forming catalyzed ii-vi semiconductor nanowires
KR101709959B1 (ko) * 2010-11-17 2017-02-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
TW201225341A (en) 2010-12-13 2012-06-16 Hon Hai Prec Ind Co Ltd Light-emitting semiconductor chip and method for manufacturing the same
TWI438930B (zh) * 2010-12-13 2014-05-21 Hon Hai Prec Ind Co Ltd 半導體發光晶片及其製造方法
CN102569623A (zh) * 2010-12-14 2012-07-11 鸿富锦精密工业（深圳）有限公司 半导体发光芯片及其制造方法
US8558209B1 (en) 2012-05-04 2013-10-15 Micron Technology, Inc. Memory cells having-multi-portion data storage region
US9212960B2 (en) * 2012-10-22 2015-12-15 The Board Of Trustees Of The Leland Stanford Junior University Nanostructures with strain-induced resistance
US9249014B2 (en) 2012-11-06 2016-02-02 Infineon Technologies Austria Ag Packaged nano-structured component and method of making a packaged nano-structured component
US20150333024A1 (en) * 2013-01-09 2015-11-19 Hitachi Ltd Semiconductor device and method for manufacturing the same
US8907479B2 (en) 2013-03-11 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Treating copper surfaces for packaging
WO2014205193A1 (en) * 2013-06-21 2014-12-24 University Of Connecticut Low-temperature bonding and sealing with spaced nanorods
US8912637B1 (en) 2013-09-23 2014-12-16 Texas Instruments Incorporated Self-adhesive die
US9453774B2 (en) 2013-12-17 2016-09-27 The Board Of Trustees Of The Leland Stanford Junior University Surface area-based pressure sensing
EP3105300B1 (en) 2014-02-13 2019-08-21 Honeywell International Inc. Compressible thermal interface materials
US10329435B2 (en) 2014-07-01 2019-06-25 University Of Utah Research Foundation Electrothermal coating with nanostructures mixture and method for making the same
US10722174B2 (en) 2014-07-11 2020-07-28 The Board Of Trustees Of The Leland Stanford Junior University Skin-conformal sensors
US9625330B2 (en) 2014-08-01 2017-04-18 The Board Of Trustees Of The Leland Stanford Junior University Methods and apparatus concerning multi-tactile sensitive (E-skin) pressure sensors
US9397023B2 (en) * 2014-09-28 2016-07-19 Texas Instruments Incorporated Integration of heat spreader for beol thermal management
US10002826B2 (en) 2014-10-27 2018-06-19 Taiwan Semiconductor Manufacturing Company Semiconductor device structure with conductive pillar and conductive line and method for forming the same
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
US9544998B1 (en) * 2015-09-14 2017-01-10 The Boeing Company Growth of carbon nanotube (CNT) leads on circuits in substrate-free continuous chemical vapor deposition (CVD) process
US20170162536A1 (en) 2015-12-03 2017-06-08 International Business Machines Corporation Nanowires for pillar interconnects
US10781349B2 (en) 2016-03-08 2020-09-22 Honeywell International Inc. Thermal interface material including crosslinker and multiple fillers
JP6419362B1 (ja) 2016-06-10 2018-11-07 リンテック オブ アメリカ インコーポレーテッドＬｉｎｔｅｃ ｏｆ Ａｍｅｒｉｃａ， Ｉｎｃ． ナノファイバーシート
DE102016220664A1 (de) * 2016-10-21 2018-04-26 Robert Bosch Gmbh Verbindungsmittel zum Verbinden der Anschlüsse eines integrierten Schaltkreises oder eines diskreten Halbleiters
US10590539B2 (en) 2017-02-24 2020-03-17 Lintec Of America, Inc. Nanofiber thermal interface material
US10381049B2 (en) * 2017-08-14 2019-08-13 Seagate Technology Llc Data storage device housing components having a polymeric element attached to a surface thereof
US11041103B2 (en) 2017-09-08 2021-06-22 Honeywell International Inc. Silicone-free thermal gel
CA2985254A1 (en) * 2017-11-14 2019-05-14 Vuereal Inc Integration and bonding of micro-devices into system substrate
WO2019118706A1 (en) 2017-12-13 2019-06-20 Analog Devices, Inc. Structural electronics wireless sensor nodes
JP6982308B2 (ja) * 2017-12-27 2021-12-17 株式会社ソフイア 遊技機
US10177058B1 (en) 2018-01-26 2019-01-08 Powertech Technology Inc. Encapsulating composition, semiconductor package and manufacturing method thereof
US11072706B2 (en) 2018-02-15 2021-07-27 Honeywell International Inc. Gel-type thermal interface material
US10833048B2 (en) * 2018-04-11 2020-11-10 International Business Machines Corporation Nanowire enabled substrate bonding and electrical contact formation
CN109796903B (zh) * 2019-03-08 2024-06-21 深圳市润沃自动化工程有限公司 一种异向性导电胶结构及其生产方法
US11195811B2 (en) * 2019-04-08 2021-12-07 Texas Instruments Incorporated Dielectric and metallic nanowire bond layers
US11373921B2 (en) 2019-04-23 2022-06-28 Honeywell International Inc. Gel-type thermal interface material with low pre-curing viscosity and elastic properties post-curing
DE102020116671A1 (de) 2020-06-24 2021-12-30 Nanowired Gmbh Waferbonding
CN214176013U (zh) * 2020-12-23 2021-09-10 迪科特测试科技(苏州)有限公司 半导体结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1623230A (zh) * 2001-12-20 2005-06-01 英特尔公司 碳毫微管热界面结构

Family Cites Families (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445895A (en) * 1977-09-17 1979-04-11 Toshiba Machine Co Ltd Saw with set wrest and automatic jigsaw having same
JPS6386458A (ja) * 1986-09-30 1988-04-16 Toshiba Corp バンプ付ｉｃチツプの製造方法、及び製造用ウエハ
US5818700A (en) * 1996-09-24 1998-10-06 Texas Instruments Incorporated Microelectronic assemblies including Z-axis conductive films
JP3372848B2 (ja) 1996-10-31 2003-02-04 キヤノン株式会社 電子放出素子及び画像表示装置及びそれらの製造方法
JP3740295B2 (ja) 1997-10-30 2006-02-01 キヤノン株式会社 カーボンナノチューブデバイス、その製造方法及び電子放出素子
JP3497740B2 (ja) 1998-09-09 2004-02-16 株式会社東芝 カーボンナノチューブの製造方法及び電界放出型冷陰極装置の製造方法
US6146227A (en) 1998-09-28 2000-11-14 Xidex Corporation Method for manufacturing carbon nanotubes as functional elements of MEMS devices
US6283812B1 (en) * 1999-01-25 2001-09-04 Agere Systems Guardian Corp. Process for fabricating article comprising aligned truncated carbon nanotubes
CN1174916C (zh) * 1999-04-21 2004-11-10 张震 碳毫微管的形成方法
JP4078760B2 (ja) * 1999-07-23 2008-04-23 株式会社村田製作所 チップ型電子部品の製造方法
US6813017B1 (en) * 1999-10-20 2004-11-02 Becton, Dickinson And Company Apparatus and method employing incoherent light emitting semiconductor devices as particle detection light sources in a flow cytometer
US6213789B1 (en) * 1999-12-15 2001-04-10 Xerox Corporation Method and apparatus for interconnecting devices using an adhesive
US6297592B1 (en) 2000-08-04 2001-10-02 Lucent Technologies Inc. Microwave vacuum tube device employing grid-modulated cold cathode source having nanotube emitters
FR2815026B1 (fr) 2000-10-06 2004-04-09 Commissariat Energie Atomique Procede d'auto-organisation de microstructures ou de nanostructures et dispositif a microstructures ou a nanostructures
JP2002117791A (ja) 2000-10-06 2002-04-19 Hitachi Ltd 画像表示装置
JP2002141633A (ja) * 2000-10-25 2002-05-17 Lucent Technol Inc 垂直にナノ相互接続された回路デバイスからなる製品及びその製造方法
JP2002203473A (ja) 2000-11-01 2002-07-19 Sony Corp 冷陰極電界電子放出素子及びその製造方法、並びに、冷陰極電界電子放出表示装置
JP2002289086A (ja) 2001-03-27 2002-10-04 Canon Inc 電子放出素子、電子源、画像形成装置、及び電子放出素子の製造方法
EP1384322A1 (en) * 2001-03-30 2004-01-28 California Institute Of Technology Carbon nanotube array rf filter
US7084507B2 (en) * 2001-05-02 2006-08-01 Fujitsu Limited Integrated circuit device and method of producing the same
DE10127351A1 (de) * 2001-06-06 2002-12-19 Infineon Technologies Ag Elektronischer Chip und elektronische Chip-Anordnung
KR100470227B1 (ko) 2001-06-07 2005-02-05 두산디앤디 주식회사 화학기계적 연마장치의 캐리어 헤드
US6739932B2 (en) 2001-06-07 2004-05-25 Si Diamond Technology, Inc. Field emission display using carbon nanotubes and methods of making the same
JP4778667B2 (ja) * 2001-06-29 2011-09-21 富士通株式会社 アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法
US6982519B2 (en) 2001-09-18 2006-01-03 Ut-Battelle Llc Individually electrically addressable vertically aligned carbon nanofibers on insulating substrates
JP2003115257A (ja) 2001-10-03 2003-04-18 Sony Corp 冷陰極電界電子放出素子の製造方法、及び、冷陰極電界電子放出表示装置の製造方法
JP2003115259A (ja) 2001-10-03 2003-04-18 Sony Corp 電子放出装置及びその製造方法、冷陰極電界電子放出素子及びその製造方法、冷陰極電界電子放出表示装置及びその製造方法、並びに、薄膜のエッチング方法
AU2002354424A1 (en) 2001-12-06 2003-06-17 Pioneer Corporation Electron emitting device and method of manufacturing the same and display apparatus using the same
SE0104452D0 (sv) 2001-12-28 2001-12-28 Forskarpatent I Vaest Ab Metod för framställning av nanostrukturer in-situ, och in-situ framställda nanostrukturer
FR2836280B1 (fr) 2002-02-19 2004-04-02 Commissariat Energie Atomique Structure de cathode a couche emissive formee sur une couche resistive
US6858197B1 (en) 2002-03-13 2005-02-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Controlled patterning and growth of single wall and multi-wall carbon nanotubes
JP4120918B2 (ja) * 2002-03-18 2008-07-16 富士通株式会社 柱状カーボン構造物の選択成長方法及び電子デバイス
SE0200868D0 (sv) 2002-03-20 2002-03-20 Chalmers Technology Licensing Theoretical model för a nanorelay and same relay
US6699779B2 (en) 2002-03-22 2004-03-02 Hewlett-Packard Development Company, L.P. Method for making nanoscale wires and gaps for switches and transistors
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6831017B1 (en) * 2002-04-05 2004-12-14 Integrated Nanosystems, Inc. Catalyst patterning for nanowire devices
AU2003228720A1 (en) * 2002-04-29 2003-11-17 The Trustees Of Boston College Density controlled carbon nanotube array electrodes
FR2839505B1 (fr) 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede
US6774052B2 (en) 2002-06-19 2004-08-10 Nantero, Inc. Method of making nanotube permeable base transistor
JP3890470B2 (ja) 2002-07-16 2007-03-07 日立造船株式会社 カーボンナノチューブを用いた電子放出素子用電極材料およびその製造方法
JP3892359B2 (ja) * 2002-07-25 2007-03-14 松下電器産業株式会社 半導体チップの実装方法
JP2005534515A (ja) 2002-08-01 2005-11-17 ステイト オブ オレゴン アクティング バイ アンド スルー ザ ステイト ボード オブ ハイヤー エデュケーション オン ビハーフ オブ ポートランド ステイト ユニバーシティー ナノスケール構造物を所定位置に合成する方法
US20040037972A1 (en) 2002-08-22 2004-02-26 Kang Simon Patterned granulized catalyst layer suitable for electron-emitting device, and associated fabrication method
US7175494B1 (en) 2002-08-22 2007-02-13 Cdream Corporation Forming carbon nanotubes at lower temperatures suitable for an electron-emitting device
US20060022191A1 (en) 2002-11-05 2006-02-02 Bakkers Erik Petrus A M Nanostructure, electronic device having such nanostructure and method of preparing nanostructures
CN1239387C (zh) 2002-11-21 2006-02-01 清华大学 碳纳米管阵列及其生长方法
WO2004051726A1 (ja) * 2002-11-29 2004-06-17 Nec Corporation 半導体装置およびその製造方法
US6984535B2 (en) 2002-12-20 2006-01-10 Cdream Corporation Selective etching of a protective layer to form a catalyst layer for an electron-emitting device
JP2004202602A (ja) 2002-12-24 2004-07-22 Sony Corp 微小構造体の製造方法、及び型材の製造方法
JP2004261875A (ja) 2003-01-09 2004-09-24 Sony Corp 転写用原盤の製造方法および転写用原盤、ならびに基板の製造方法および基板
US6764874B1 (en) 2003-01-30 2004-07-20 Motorola, Inc. Method for chemical vapor deposition of single walled carbon nanotubes
US7316061B2 (en) * 2003-02-03 2008-01-08 Intel Corporation Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface
WO2004079450A1 (en) 2003-03-06 2004-09-16 Yissum Research Development Company Of The Hebrew University Of Jerusalem Method for manufacturing a patterned structure
JP4401094B2 (ja) * 2003-03-20 2010-01-20 富士通株式会社 炭素元素円筒型構造体へのオーミック接続構造及びその作製方法
US20040182600A1 (en) 2003-03-20 2004-09-23 Fujitsu Limited Method for growing carbon nanotubes, and electronic device having structure of ohmic connection to carbon element cylindrical structure body and production method thereof
CN100419943C (zh) 2003-04-03 2008-09-17 清华大学 一种场发射显示装置
US7608147B2 (en) 2003-04-04 2009-10-27 Qunano Ab Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
SE0301236D0 (sv) 2003-04-28 2003-04-28 Chalmers Technology Licensing Method of manufacturing a nanoscale conductive device
KR100554155B1 (ko) 2003-06-09 2006-02-22 학교법인 포항공과대학교 금속/반도체 나노막대 이종구조를 이용한 전극 구조물 및그 제조 방법
KR100537512B1 (ko) 2003-09-01 2005-12-19 삼성에스디아이 주식회사 카본나노튜브구조체 및 이의 제조방법 그리고 이를 응용한전계방출소자 및 표시장치
JP4689218B2 (ja) 2003-09-12 2011-05-25 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2005116469A (ja) 2003-10-10 2005-04-28 Sony Corp 冷陰極電界電子放出素子の製造方法
JP4271544B2 (ja) * 2003-10-10 2009-06-03 リンテック株式会社 半導体装置の製造方法
US7459839B2 (en) 2003-12-05 2008-12-02 Zhidan Li Tolt Low voltage electron source with self aligned gate apertures, and luminous display using the electron source
WO2005064639A2 (en) 2003-12-22 2005-07-14 Koninklijke Philips Electronics N.V. Fabricating a set of semiconducting nanowires, and electric device comprising a set of nanowires
TWI234211B (en) * 2003-12-26 2005-06-11 Advanced Semiconductor Eng Method for forming an underfilling layer on a bumped wafer
JP4184306B2 (ja) 2004-03-18 2008-11-19 パイオニア株式会社 電子放出素子
JP4448356B2 (ja) 2004-03-26 2010-04-07 富士通株式会社 半導体装置およびその製造方法
CN100383213C (zh) * 2004-04-02 2008-04-23 清华大学 一种热界面材料及其制造方法
US20060086994A1 (en) 2004-05-14 2006-04-27 Susanne Viefers Nanoelectromechanical components
US20050285116A1 (en) * 2004-06-29 2005-12-29 Yongqian Wang Electronic assembly with carbon nanotube contact formations or interconnections
JP2006108649A (ja) 2004-09-09 2006-04-20 Masaru Hori ナノインプリント用金型、ナノパターンの形成方法及び樹脂成型物
WO2006137893A2 (en) 2004-10-01 2006-12-28 Board Of Regents Of The University Of Texas System Polymer-free carbon nanotube assemblies (fibers, ropes, ribbons, films)
FR2876244B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant muni d'un ensemble de micropointes conductrices dures et procede de connexion electrique entre ce composant et un composant muni de protuberances conductrices ductiles
TWI463615B (zh) * 2004-11-04 2014-12-01 Taiwan Semiconductor Mfg Co Ltd 以奈米管為基礎之具方向性導電黏著
CN1976869B (zh) 2005-02-10 2010-12-22 松下电器产业株式会社 用于维持微细结构体的结构体、半导体装置、tft驱动电路、面板、显示器、传感器及它们的制造方法
KR100682863B1 (ko) 2005-02-19 2007-02-15 삼성에스디아이 주식회사 탄소나노튜브 구조체 및 그 제조방법과, 탄소나노튜브 구조체를 이용한 전계방출소자 및 그 제조방법
WO2006098026A1 (ja) * 2005-03-17 2006-09-21 Fujitsu Limited 接続機構、半導体パッケージ、およびその製造方法
KR101145146B1 (ko) 2005-04-07 2012-05-14 엘지디스플레이 주식회사 박막트랜지스터와 그 제조방법
US7687876B2 (en) 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US7402909B2 (en) * 2005-04-28 2008-07-22 Intel Corporation Microelectronic package interconnect and method of fabrication thereof
US8173525B2 (en) 2005-06-17 2012-05-08 Georgia Tech Research Corporation Systems and methods for nanomaterial transfer
JP4386012B2 (ja) * 2005-08-23 2009-12-16 株式会社デンソー バンプ接合体の製造方法
US7777291B2 (en) * 2005-08-26 2010-08-17 Smoltek Ab Integrated circuits having interconnects and heat dissipators based on nanostructures
KR101386268B1 (ko) 2005-08-26 2014-04-17 스몰텍 에이비 나노구조체에 기반한 인터커넥트 및 방열기
JP4855757B2 (ja) * 2005-10-19 2012-01-18 富士通株式会社 カーボンナノチューブパッド及び電子デバイス
KR100745734B1 (ko) * 2005-12-13 2007-08-02 삼성에스디아이 주식회사 탄소나노튜브의 형성방법 및 이를 이용한 전계방출소자의제조방법
US7371674B2 (en) * 2005-12-22 2008-05-13 Intel Corporation Nanostructure-based package interconnect
US8337979B2 (en) * 2006-05-19 2012-12-25 Massachusetts Institute Of Technology Nanostructure-reinforced composite articles and methods
JP4744360B2 (ja) * 2006-05-22 2011-08-10 富士通株式会社 半導体装置
KR100803194B1 (ko) 2006-06-30 2008-02-14 삼성에스디아이 주식회사 탄소나노튜브 구조체 형성방법
WO2008054283A1 (en) 2006-11-01 2008-05-08 Smoltek Ab Photonic crystals based on nanostructures
JP4870048B2 (ja) * 2007-08-20 2012-02-08 富士通株式会社 電子部品装置及びその製造方法
JP5535915B2 (ja) * 2007-09-12 2014-07-02 スモルテック アーベー ナノ構造体による隣接層の接続および接合
JP5474835B2 (ja) 2008-02-25 2014-04-16 スモルテック アーベー ナノ構造処理のための導電性補助層の形成及び選択的除去

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1623230A (zh) * 2001-12-20 2005-06-01 英特尔公司 碳毫微管热界面结构

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