TWI564980B - 以奈米結構連接和結合相鄰層 - Google Patents

以奈米結構連接和結合相鄰層 Download PDF

Info

Publication number
TWI564980B
TWI564980B TW104130921A TW104130921A TWI564980B TW I564980 B TWI564980 B TW I564980B TW 104130921 A TW104130921 A TW 104130921A TW 104130921 A TW104130921 A TW 104130921A TW I564980 B TWI564980 B TW I564980B
Authority
TW
Taiwan
Prior art keywords
nanostructure
conductive
nanostructures
substrate
bonding film
Prior art date
Application number
TW104130921A
Other languages
English (en)
Other versions
TW201601230A (zh
Inventor
摩哈瑪德 夏非庫爾 卡畢爾
安德烈 布魯德
Original Assignee
斯莫勒科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 斯莫勒科技公司 filed Critical 斯莫勒科技公司
Publication of TW201601230A publication Critical patent/TW201601230A/zh
Application granted granted Critical
Publication of TWI564980B publication Critical patent/TWI564980B/zh

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/12Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/06Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/10Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the pressing technique, e.g. using action of vacuum or fluid pressure
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/14Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
    • B32B37/16Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B38/00Ancillary operations in connection with laminating processes
    • B32B38/0008Electrical discharge treatment, e.g. corona, plasma treatment; wave energy or particle radiation
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J9/00Adhesives characterised by their physical nature or the effects produced, e.g. glue sticks
    • C09J9/02Electrically-conducting adhesives
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49877Carbon, e.g. fullerenes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/12Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
    • B32B2037/1253Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives curable adhesive
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/20Properties of the layers or laminate having particular electrical or magnetic properties, e.g. piezoelectric
    • B32B2307/202Conductive
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/30Properties of the layers or laminate having particular thermal properties
    • B32B2307/302Conductive
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2307/00Properties of the layers or laminate
    • B32B2307/70Other properties
    • B32B2307/706Anisotropic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/02Temperature
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/12Pressure
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2310/00Treatment by energy or chemical effects
    • B32B2310/08Treatment by energy or chemical effects by wave energy or particle radiation
    • B32B2310/0806Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation
    • B32B2310/0831Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation using UV radiation
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2313/00Elements other than metals
    • B32B2313/04Carbon
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00Electrical equipment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05026Disposition the internal layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29006Layer connector larger than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/29393Base material with a principal constituent of the material being a solid not provided for in groups H01L2224/293 - H01L2224/29391, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29499Shape or distribution of the fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10329Gallium arsenide [GaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/10336Aluminium gallium arsenide [AlGaAs]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/141Analog devices
    • H01L2924/1423Monolithic Microwave Integrated Circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24174Structurally defined web or sheet [e.g., overall dimension, etc.] including sheet or component perpendicular to plane of web or sheet

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Fluid Mechanics (AREA)
  • Plasma & Fusion (AREA)
  • Thermal Sciences (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Carbon And Carbon Compounds (AREA)
  • Laminated Bodies (AREA)

Description

以奈米結構連接和結合相鄰層
在此所述科技大體上關於奈米結構,且更特別地,關於使用奈米結構來連接和結合相鄰之傳導材料層。
在電子元件生產和製造中,許多例子係需將例如存在於一構件中之一層材料黏附至通常是在例如一晶圓或晶粒的基板上之特定位置處。在這類例子中,不管是機械性、熱性或電連接,該連接之完整性對該元件執行效率可能具有關鍵性。
範例包含:黏附或結合一覆晶至一底層(例如一晶粒的基板);液晶顯示器製造中所使用具細微間距之晶片軟板構裝(chip-on-flex,COF)技術;及在一細微間距下產生電接觸之晶圓級凸塊技術。在所有這類應用例中,目前科技正遭遇顯著的限制,部分是起因於漸增的電子元件小型化要求。
〝覆晶〞技術之使用正快速地增加,且該技術目前使用於例如行動電話、MP3播放器、智慧卡、顯示器、電腦周邊裝置之元件中。然而,就複雜度及產品成本而論,因為涉及將該覆晶結合和連接至該晶粒之複雜製程要求,覆晶技術具有一些缺點。這些製程包含焊料助焊劑塗佈、 晶片/電路板安排、焊塊回流製程、助焊劑移除製程、底部填充及固化製程。
結合並連接覆晶所使用之技術正朝向越來越多的輸出入接觸數目及該些接觸間的間距更細微來移動。見例如作者Peter J.Opdahl在網頁www.flipchips.com/tutorial05.html中所示之〝覆晶應用中之異向傳導薄膜之簡介(Anisotropic Conductive Film for Flipchip Applications:An Introduction)〞,在此將其一併整合參考之。
如同一焊料凸塊技術之替代方案,異向傳導薄膜(ACF)為一無鉛、無污染且無助焊劑之結合方案,其由散佈於例如一黏性樹脂之聚合物基質中之傳導微粒所構成。異向傳導薄膜藉由捕抓在例如一覆晶上之傳導凸塊之傳導表面及例如一基板上對應至該覆晶上傳導凸塊之傳導墊片之另一傳導表面間之傳導微粒來作用,而使相鄰微粒彼此間互相絕緣。
在最近這幾十年間,異向傳導薄膜已廣泛地使用於平面顯示器工業之封裝技術中,而將一積體電路以電及機械方式連接至一顯示器之玻璃基板上。近來,異向傳導薄膜已被證明為其它直接晶片黏附技術之常用替代方案,以滿足較小尺寸對於細微間距之要求。對於該異向傳導薄膜材料而言,代表所製造之傳導微粒越小越好,以產生高微粒密度並確保在該異向傳導薄膜內極均勻地散佈微粒。此外,該聚合物基質之流動典型地必須儘可能地受到良好地控制。目前,尺寸小至3.5微米之微粒係使用於高要求應用中。
長久以來已認知到異向傳導薄膜遇到一些限制。若該些微粒太大,或者有太多微粒,則在該覆晶上二相鄰凸塊間具有產生短路的風險。這個意謂著對微粒間之最小可行間距之限制,因為若該些微粒彼此間太過 接近則會引起短路。這個在例如顯示器工業中係特別明顯,其中,當短路出現時會出現黑點。在沒有明確方式來精準預測該聚合物基質內微粒分佈之均勻度時,短路風險總是存在。避開該些微粒所引起之短路風險而受到之衝擊係最大可行接觸(I/O)數量受到限制,因而在使用異向傳導薄膜連接一覆晶時,該最大可行間距受到限制。
晶片軟板構裝(COF)係一同樣利用異向傳導薄膜之相關技術,並在更細微間距產品(在目前產品內係小於40-50微米)之要求增加以滿足成本及尺寸之要求時觸發類似〝覆晶〞技術之問題。隨著目前結合製程而在具細微間距之晶片軟板構裝技術中所引起之二個主要議題為:引線斷裂及未對準。
既然組合製程期間之引線斷裂可在任何情況及任何位置發生,目視檢查幾乎是不可能的。引線斷裂可發生於在該二傳導表面間缺少捕抓到的傳導微粒時;小於一之捕抓微粒計數則產生高機率之電斷路,其導致電失敗。為了避免那個問題,該微粒密度必須增加,其係藉由降低該些微粒直徑而得。若該晶片軟板構裝技術之引線間距為40微米,可運用具有小於3微米的微粒直徑之異向傳導黏劑(ACA)以得到99.95%機會的良好電連接(至少一捕抓微粒)。
然而,即使在那高連接整合率下,錯誤容限也是無法忽略。例如,對於具有400凸塊封裝而言,五個晶片中的一個可能具有一斷開(斷線)之凸塊/引線接合。甚至,若凸塊及引線間之間隙變化大小超過3微米,則一斷開之接合失敗便可發生,即使其具有內含捕抓微粒之正常接合亦然。因此,總言之,將一異向傳導黏劑(ACA)應用至具細微間距之晶片軟板 構裝技術,需要降低微粒尺寸且更精確的控制凸塊/引線高度及晶片/薄膜共平面性。
未對準也使更細微引線間距具更大風險,因為更細微間距使該薄膜及該些傳導表面間之對準需要更高精確度控制。為了滿足良率,現存容忍度需求最終必被一新標準所取代。該晶片軟板構裝組件製程中未對準原因係各式各樣,且可能在該薄膜、晶片、結合設備等等中。該結合容忍度與變異天性有關。
因此,利用異向傳導薄膜之主要問題可被總結為:(1)對於均勻散佈微粒尺寸之需求;(2)對於使該些微粒之表面塗佈斷裂並產生接觸之結合壓力之控制需求;(3)對於微粒分佈之微粒尺寸上之限制-不能下降至次微米層級;及(4)製造限制-無法製造具有良好可再生均勻度之次微米層級。據此,需要有更好方式來製造晶片及基板間之連接及將一晶片附著在一基板上。
晶圓層級凸塊技術係遇到類似需要考量的問題。對於透過分佈產生電接觸或具有較低尺寸及更細微間距之接觸通道之凸塊需求乃甚至要求更大的製造精準度。電連接係由凸塊所產生,但在那些凸塊尺寸上有所限制;利用目前製程不可能降低至次微米層級,其受到每單位面積凸塊數的限制。因此,一些分佈通道正遇到產生該些凸塊的限制。
在此背景段落的討論被納入以說明該科技背景。這個並不是代表在所附申請專利範圍中任一者之優先權日所已出版、已知參考材料或部分常識中之任一者。
遍及說明書之說明及申請專利範圍中,該單字〝包括〞及其 變化,例如〝comprising〞及〝comprises〞,並非要將其它補充、構件、整體或步驟排除在外。
本揭示提供一種裝置,包括:一第一傳導表面;一第二傳導表面;及二或更多奈米結構,其中,該二或更多奈米結構中每一個係平行於該二或更多奈米結構中另一個來定向,且其中,該二或更多奈米結構包括二或更多交互擴散材料,該二或更多交互擴散材料包含影響該二或更多奈米結構形態之至少一材料及影響該第一傳導表面間界面之電特性之至少一材料,且其中,一第一結合存在於該二或更多奈米結構中每一個之第一末端及該第一傳導表面之間,且其中,該二或更多奈米結構係垂直定向於該第一傳導表面,且其中,一第二結合存在於該二或更多奈米結構中每一個之第二末端及該第二傳導表面之間,且其中,該二或更多奈米結構係垂直定向於該第二傳導表面。
一種使用一奈米結構組件來連接一第一傳導表面至一第二傳導表面之方法,該方法包括:藉由在該傳導基板上沉積一或更多中間層、在該一或更多中間層上沉積一催化劑層、在不需先退火該基板下加熱該基板至一可形成該奈米結構之溫度、及在該溫度下於該催化劑層上生長二或更多奈米結構,而產生一奈米結構組件,其中,該複數個中間層中至少其中之一包括自非結晶矽及鍺所構成之族群中選出之材料,且其中,該一或更多中間層中至少其中之一與該催化劑層進行交互擴散,且其中,該催化劑層及進行交互擴散之一或更多中間層中之至少其中之一係展現於該奈米結構中;以一絕緣材料塗佈該奈米結構組件以形成一具有內嵌式奈米結構 之薄膜;拋光該薄膜以得到用於該奈米結構組件之二或更多奈米結構之均勻想要長度;切割該薄膜以產生一或更多獨立墊片;自該傳導基板中拔出該些墊片;在該第一傳導表面及該第二傳導表面間插入該一或更多墊片;及固化該一或更多墊片,藉以將該第一傳導表面結合至該一或更多墊片中之第一表面並將該第二傳導表面結合至該一或更多墊片中之第二表面。該絕緣材料可以是例如一黏性聚合物之聚合物。
一種使用一奈米結構組件來連接一第一傳導表面至一第二傳導表面之方法,該方法包括:藉由在該第一傳導表面上沉積一或更多中間層、在該一或更多中間層上沉積一催化劑層、在不需先退火該基板下加熱該基板至一可形成該奈米結構之溫度、及在該溫度下於該催化劑層上生長二或更多奈米結構,而產生一奈米結構組件,其中,該複數個中間層中至少其中之一包括自非結晶矽及鍺所構成之族群中選出之材料,且其中,該一或更多中間層中至少其中之一與該催化劑層進行交互擴散,且其中,該催化劑層及進行交互擴散之一或更多中間層中之至少其中之一係展現於該奈米結構中;以一絕緣材料塗佈該奈米結構組件以在該第一傳導表面上形成一具有內嵌式奈米結構之薄膜;拋光該薄膜以得到用於該奈米結構組件之二或更多奈米結構之均勻想要長度;切割該薄膜及該第一傳導表面以產生一或更多獨立墊片,每一個墊片包括該薄膜中的一段及該第一傳導表面中的一段;將一或更多墊片施用至該第二傳導表面;及固化該一或更多墊片,藉以將該第二傳導表面結合至該一或更多墊片之一表面。該絕緣材料可以是例如一黏性聚合物之聚合物。
一種使用一奈米結構組件來連接一第一傳導表面至一第二 傳導表面之方法,該方法包括:藉由沉積一或更多中間層、在該一或更多中間層上沉積一催化劑層、在不需先退火該基板下加熱該基板至一可形成該奈米結構之溫度、及在該溫度下於該催化劑層上生長二或更多奈米結構,而產生一奈米結構組件,其中,該一或更多中間層中至少其中之一與該催化劑層進行交互擴散,且其中,該催化劑層及進行交互擴散之一或更多中間層中之至少其中之一係展現於該奈米結構中;利用金屬沉積法塗佈該些奈米結構以在該第一傳導表面上形成金屬內嵌式奈米結構;以一絕緣材料塗佈該奈米結構組件以在該第一傳導表面上形成一具有內嵌式奈米結構之薄膜;拋光該薄膜以得到用於該奈米結構組件之二或更多奈米結構之均勻想要長度;切割該薄膜及該第一傳導表面以產生一或更多獨立墊片,每一個墊片包括該薄膜中的一段及該第一傳導表面中的一段;將一或更多墊片施用至該第二傳導表面;及固化該一或更多墊片,藉以將該第二傳導表面結合至該一或更多墊片之一表面。該絕緣材料可以是例如一黏性聚合物之聚合物。
100‧‧‧基板
110‧‧‧接觸墊片
200‧‧‧黏性聚合物
210‧‧‧奈米碳纖維
220‧‧‧拉直力
230‧‧‧收縮黏力
300‧‧‧元件層
310‧‧‧輸出入墊片
320‧‧‧鎢插塞
330‧‧‧金屬插塞
圖1係於一基質原理中使用奈米碳纖維結合及電接觸一晶粒至一基板。
圖2係在固化前於一基質中使用奈米碳纖維結合及電接觸一晶粒至一基板。
圖3A、3B係在固化後於一基質中使用奈米碳纖維結合及電接觸一晶粒至一基板。
圖4係一基質中之奈米碳纖維俯視圖。
圖5係一具有一輸出入墊片之基質中之奈米碳纖維俯視圖。
圖6係一具有一輸出入墊片之基質中之奈米碳纖維剖視圖。
圖7顯示在此所述之流程圖。
圖8顯示在此所述之流程圖。
圖9顯示在此所述之流程圖。
本科技係針對藉由在二表面或層上結合奈米結構至接觸位置來連接該二表面或層而藉此在該二表面或層間產生機械、電或熱連接之方法。藉由這類方法,該些接觸位置之間距可落在2奈米至1毫米涵蓋範圍內。本科技進一步包含一裝置,其包括一第一傳導表面或層、一第二傳導表面或層、及一結合並定位於該二傳導表面或層間之奈米結構組件,如此,該奈米結構組件之奈米結構係垂直於該二傳導表面或層而定向。
在本科技另一觀念中,一接合層係藉由在形成於一基板上之金屬底層上生長例如奈米碳結構(CNS)之奈米結構而形成。該基板可包括一或更多的金屬、半導體材料或絕緣材料層,或者上述材料之結合。該些奈米結構垂直於該基板表面生長。該些奈米結構可塗佈於例如一黏性聚合物之聚合物類之載體中。該載體可為一絕緣材料或可為一可彎曲或堅硬之材料。選擇性地,該些奈米結構,不論是否已塗佈或未塗佈,可被拋光以提供均勻長度。所產生之結構可切割成獨立薄膜。選擇性地,該具有聚合物及奈米結構之薄膜可自該基板中拔出。接著,該薄膜可施用至一晶粒表面以提供晶圓接觸。
在該科技又一觀念中,一晶圓接合層可包含例如奈米碳結構 (CNS)之內含於例如在此所述之聚合物塗佈層中之奈米結構。該些奈米結構垂直於該層之頂部及底部表面延伸。該些奈米結構可分組成族群,一族群內之奈米結構間具有一規律空隔,而另外的族群具有另一規律(較大)空隔。不是以與一共用電極直接接觸方式來置放就是在電耦接之金屬底層上生長的方式,以電連接一族群內之奈米結構。相對地,各族群之奈米結構係彼此電絕緣。
當在此使用〝垂直〞來說明一奈米結構及一層或表面間之定向時,要了解到該奈米結構係一接線、管子或纖維形式或類似結構,其具有一沿著它的長度延伸之縱軸,且該縱軸係正交於一層或表面之平面而置放。進一步要了解到〝垂直〞包括由完全精確垂直所衍生之小偏移,例如,相對於該平面之88-90度或85-90度之縱軸傾斜之類。
在一些實施例中,該些奈米結構大體上係堅固的,使包含它們之層大體上係不可壓縮的。
奈米結構範例包含奈米管、奈米纖維或奈米線,但不限於此。尤其,在此所建立之奈米結構可由例如奈米碳管、奈米碳纖維或碳奈米線之以碳為基礎之奈米結構所構成。
在此所建立之奈米結構也可由例如金屬、三五族化合物、二六族化合物、或來自元素週期表之元素結合之其它材料所構成。材料範例包含例如砷化鎵、磷化銦、砷化銦鎵、砷化鋁鎵之半導體、例如矽奈米線之奈米線、例如氧化鋅、氧化鋁鋅之合金、及可形成奈米結構之任何其它二元或三元合金。
與在此應用例一致之奈米結構可生長/形成/沉積於例如矽、 多晶矽、氧化矽、氮化矽、鍺、矽鍺化合物、砷化鎵、砷化鋁鎵、氮化鎵、磷化銦、玻璃、聚醯亞胺、聚合物、例如鎢、鉬、鈦、鉻、鉻化鎳、鋁、鋁氧化物(AlOx)、鉑、鈀、金、銅、氮化鈦之金屬或來自該元素週期表之任何其它金屬、塑膠、鋁箔、氧化鋁、紙張、及例如氧化鉿、氧化鋯之高介電常數材料…等等之基板上。為了生長該些奈米結構,該催化劑可為鎳、鉻化鎳、鈀、鉑、鐵、金、鈷或這類金屬之結合、或例如鈷-釩、鈷-鎳、鐵-鎳等等之二金屬催化劑類之不同材料合金。
化學氣相沉積法(CVD)係一用於配合在此所述科技來使用以生長奈米結構之典型方法。然而,有幾種不同的化學氣相沉積方法可使用,例如熱化學氣相沉積法、電漿輔助化學氣相沉積法、遠距電漿輔助化學氣相沉積法、金屬有機化學氣相沉積法等等、或熟知此項技術之人士所知之任何其它化學氣相沉積法變化。特定生長方法係描述於2006年4月25日所提申之美國專利申請案序號第11/412,060號之〝控制一基板上之奈米結構生長〞之中,在此將其整體一併整合參考之。
又進一步,在此之奈米結構可由各方法及材料,運用於該些奈米結構一旦被形成時可用以控制該些奈米結構各種特性之條件來形成。因此,在此所使用之奈米結構包括具有下列特徵之自基板生長之奈米結構及位於其間之界面層。該基板較佳地係例如一金屬層之傳導層,其可配置在一支撐物上。該支撐物典型地係薄膜技術中所使用之一矽晶圓或其它半導體材料、玻璃、或適合彎曲之聚合物。該金屬較佳地係選自由鉬、鎢、鉑、鈀及鉭所構成之族群中。該金屬層厚度較佳地係在1奈米至1微米範圍內,甚至更佳地在1奈米至50奈米範圍內。該金屬層較佳地係藉由習知 技術中所知一些方法中任一者來沉積,該些方法包含但不限於下列者:例如熱或真空蒸鍍法、分子束磊晶法及電子束蒸鍍法之蒸鍍性方法;例如習知技術中所知一些濺鍍形式中任一者之輝光放電方法,及例如電漿輔助化學氣相沉積法之電漿製程;及包含例如化學氣相沉積法之氣相製程,及離子植入法,及例如電鍍法及液相磊晶法之液相製程。沉積技術範例係示於K.Seshan所編輯之第二版的薄膜沉積手冊(Handbook of Thin Film Deposition)(2002年William Andrew公司)中。
該些界面層,亦稱為中間層,包括依序沉積在該基板上之一或更多層。在該些界面層頂部係一催化劑層。該奈米結構係自該催化層頂部上開始生長。
該些界面層可簡單地由一單材料層所構成。在本環境中,該單層可為矽或鍺。該些層可以非結晶或結晶形式藉由例如蒸鍍法或濺鍍法之技術來沉積。該厚度典型地範圍自1奈米至1微米,且亦可在1奈米至50奈米範圍內。
該界面層可包括一些不同材料層並可根據功能隨意分類。例如,該基板附近各層係特徵化為影響該界面電特性之層。該催化劑附近各層係特徵化為影響例如該奈米結構之電/機械特性之組成及特性之層。
各種界面層架構係可與本發明相容。例如,基於控制該界面電特性目的,一達3層之序列可沉積在該基板上。這類架構包含:一絕緣體、導體或半導體及絕緣體序列;一鄰接至該基板之絕緣體及一半導體層序列;一半導體、絕緣體、半導體序列;一鄰接至該基板之二絕緣障礙層及一半導體序列;一不同於該基板金屬之單金屬層;及一不同於該基板金 屬之金屬及一半導體層序列;但不限於此。在這類架構中,該絕緣體可選自矽氧化物、三氧化二鋁、鋯氧化物、鉿氧化物、矽氮化物、三氧化二鋁、五氧化二鉭、二氧化鈦、及銦錫氧化物所構成之族群中。該半導體可為矽或鍺。所示金屬可為鈀、鉑、鉬或鎢。在呈現二相同特徵層的地方,例如二半導體層,該些層彼此間具有相同組合係不需要的。
前述界面層中最上層它本身可緊靠該催化劑層。一個特例是最上層係一例如矽或鍺之半導體。然而,在上述界面層它們上面置放另一層或在它們及該催化劑層間座落一序列之層係額外可行的。這類額外或第二界面層係想要做為控制該奈米結構特性及組合之用。該些第二界面層可為一對,例如一金屬層及一在其上而鄰接至該催化劑層之半導體層。替代性地,該些第二界面層可簡單地由單一半導體層所構成。出現該些界面層之金屬層較佳地係選自由鎢、鉬、鈀及鉑所構成之族群中。該些第二界面層中之半導體層較佳地係矽或鍺。
該催化劑層典型地係一金屬或金屬合金層,且可包含非常細微之金屬或金屬合金微粒以取代一連續薄膜。該催化劑層較佳地包括選自由鎳、鈀、鐵、含任意比例之鎳及鉻之鎳鉻合金、及鉬所構成之族群中之一金屬。
該些奈米結構典型地為在該催化劑層及該傳導基板間具有至少一材料層之多堆疊架構,其中,該材料類型與該催化劑及傳導基板不同,且其中,該材料控制不同層間之化學反應。因此,在不同傳導基板上之奈米結構生長可受到控制。藉此,該長成結構之形態及特性以及該長成結構之尖端材料可受到控制。目前科技可被延伸而具有一些不同類型(半導 性、鐵電性、磁性等等)材料之堆疊,其可使用於控制該奈米結構的基底/界面、本體及尖端之特性。在一可為例如傳導、絕緣或半導體之任何類型基板上自我沉積之傳導層上生長該奈米結構也是可行。
典型地,在這類奈米結構生長期間,發生有些中間層材料擴散至該些奈米結構中。這類交互擴散可傳送該些中間層材料直達長成之奈米結構頂端。在一些條件中,該擴散材料係呈現一窄帶狀;在其它條件中,該擴散材料係散佈於整個奈米結構。
在此所述方法係可應用於提供包含類比及/或數位電子電路之電子構件之任何組合技術中。例如,這類構件可建立於:通訊工程、汽車/工業電子元件物品、消費性電子元件、計算、數位信號處理及整合式產品之中。例如球閘陣列(BGA)、覆晶(FC)模組、晶片級封裝(CSP)、晶圓級封裝(WLP)、覆晶式組裝(FCOB)、熱壓接合(TCB)之附著技術可利用在此之方法。例如射頻辨識(RFID)、互補式金氧半導體(CMOS)、雙載子互補式金氧半導體(BiCMOS)、砷化鎵、砷化鋁鎵、單晶片微波積體電路(MMIC)、多晶片模組(MCM)之積體電路(IC)類型可利用在此所述方法。例如汽車、電腦、行動電話手機及電視中所使用之液晶顯示器、發光二極體及有機發光二極體之顯示器科技也可整合在此所述方法所做之連接。可以類似方式整合這類科技之其它電子構件包含:特殊用途積體電路(ASIC)晶片、記憶體元件、微控制器(MCU)、高頻元件模組、整合式被動構件等等,但不限於此。
在此所述方法也可用以產生連接、熱通孔或熱導體或非熱導體、電感器、電容器及電阻器,達到它們可由在二材料層間產生連接之技術中獲利之程度。該方法可進一步使用於例如光子晶體、波導、濾波器、 光電電路等等之光電元件。該方法也可使用於生物元件或生物及以矽為基礎之混合元件,例如實驗室晶片陣列及生物診斷用之探針。
結構
在此所述製程所產生之裝置包括一載體,其具有內嵌於該載體內之奈米結構,其中,該些奈米結構長成具有一特定形態及功能。該些奈米結構被定向以使彼此間近乎平行並垂直於該基板。該些奈米結構係具有接近想要之長度或高度。
圖1-8概略性地說明在此所述之方法及裝置。要了解,雖然使用一奈米碳纖維(CNF)來說明圖1-8,但其它形式奈米結構可以類似方式來使用。這類替代性奈米結構包含奈米管、奈米線及奈米索,但不限於此。這類奈米結構可由碳摻雜一或更多其它元素來製造,但不限於此。類似地,雖然使用一黏性聚合物來說明圖1-8,但可替代性地使用其它形式聚合物。
圖1說明於一基質中使用一奈米碳纖維墊片來結合及電接觸例如一晶粒至一基板之二相鄰金屬層之整體原理。圖1所示係三層:一具有一內嵌式接觸墊片110之基板100,基板上係一環繞著垂直於該基板100定向之許多奈米碳纖維(CNF)210的黏性聚合物層200,一些奈米碳纖維係與接觸墊片110接觸,且該黏性聚合物層之上係一元件層300。該元件層300包含:連接一些奈米碳纖維之一輸出入(I/O)墊片310、在該輸出入墊片上方而由例如鎢所製造之一第一金屬插塞320、及在該第一插塞上方之一第二金屬插塞330。插塞320、330彼此間係不同,且可由鎢或該工業中所使用之例如鋁、銅或金之任何其它金屬所構成。
圖2顯示在固化前於一基質中使用奈米碳纖維結合及電接 觸一晶粒至一基板。本圖中只顯示單一奈米碳纖維,單純是為了易於說明之故。
圖3A、3B顯示在固化後於一黏性聚合物基質中使用奈米碳纖維(為了易於說明之故,本圖中只顯示單一奈米碳纖維)結合及電接觸一晶粒至一基板。雙向箭頭220指示一感應在該奈米碳纖維中之〝彈簧負載〞之拉直力。二個單向箭頭230指示由固化所感應產生之收縮黏力。
圖3B顯示在固化後於一基質中使用奈米碳纖維結合及電接觸一晶粒至一基板。雙向箭頭220指示一感應在該奈米碳纖維中之〝彈簧負載〞之拉直力。二個單向箭頭230指示由固化所感應產生之收縮黏力。
圖4顯示一基質中之奈米碳纖維陣列之俯視圖。代表性空隔被顯示。相鄰奈米結構間之間距係200奈米;該陣列大小係600奈米;且該些奈米纖維具有一50奈米直徑。
圖5顯示一具有重疊一奈米結構子組之輸出入墊片之基質中之奈米碳纖維陣列之俯視圖。代表性空隔被顯示。相鄰奈米結構間之間距係200奈米;該陣列大小係600奈米;該些奈米纖維具有一50奈米直徑;所示輸出入墊片直徑係為400奈米。
熟知此項技術之人士要了解,圖4及圖5所示之空隔係示範性,且在此之科技操作係與該些圖形中所示之那些空隔之精確值無關。
圖6顯示一具有例如圖5所示之輸出入墊片之基質中之奈米碳纖維剖視圖。某些奈米結構連接該接觸墊片及該輸出入墊片,而其餘則置放於該些墊片如所示地共同擁有且不需延伸至該黏性層全部厚度之所在區域之外。
範例1:使用奈米結構及一異向傳導薄膜來產生接觸之製程
本範例提供一種連接二表面/層(例如,在一第一晶粒或晶片之接觸表面/層及一該第一晶片將附於其上之第二晶粒或晶片之接觸層/表面之間)。該連接係以1毫米至2奈米範圍內之任何間距(典型地下達至20奈米)進行結合及電/熱性接觸,其中,該電/熱性接觸構件係基於奈米結構。
一種與本方法一致之結構由以下所構成:(a)一載體層(例如以可彎曲或堅固材料為基礎,例如,聚醯亞胺),(b)內嵌於該載體並具有特定形態及功能之奈米結構,其中,該些奈米結構彼此間係互相平行定向並垂直於載體兩表面,且(c)其中,該些奈米結構可根據國際專利申請案PCT/SE2006/000487(在此將其一併整合參考之)所述方法來生長,以透過形態、大小、長度、距離等等來說明控制。
一在此使用之典型奈米結構組件包括:一傳導基板(例如一金屬);一在該傳導基板上之第一催化劑層;一由該第一催化劑層所支撐之奈米結構;及在該傳導基板及該第一催化劑層間之複數個中間層,該複數個中間層包含影響該奈米結構形態之至少一層及影響該傳導基板及該奈米結構之間界面電特性之至少一層。
該結構特徵包含:該接觸構件(奈米結構)係垂直於該些連接表面,即使該些奈米結構彼此間係互相平行亦然。該些奈米結構特性可根據生長方法來設計。每一單位可與其它這類單位相結合以組合成進一步結構,就像樂高積木一般。
圖7說明藉由結合及產生包括奈米結構之電或熱接觸來連接二表面或層之示範性製程中之步驟。該些步驟包括:在一傳導基板上生 長一奈米碳結構層,而在該傳導基板及該些奈米結構之間具有複數個中間層(701);以一黏性聚合物(或一些其它絕緣材料)塗佈所得之奈米結構以形成一具有內嵌式奈米結構之薄膜(702);拋光該薄膜以產生一均勻想要長度之奈米結構(703);切割該薄膜以產生獨立墊片(704);拔出該些墊片(705);施用每一個獨立墊片於一第一傳導表面或層(例如,一晶粒表面)及一第二傳導表面或層(例如,一在晶片上之接觸表面)之間(706);及固化該些墊片以將該晶粒結合至該墊片並將該墊片結合至該接觸表面,因此經由內嵌於該墊片之奈米結構而在該晶粒及該接觸表面間產生電或熱接觸(707)。
在一傳導基板上生長奈米結構層,而在該傳導基板及該些奈米結構之間具有複數個中間層,此第一步驟(701)包括生長該些奈米結構,典型地具有每一微米大於10個奈米結構之密度。這類密度或一給定例子中之所需密度可藉由控制施加在該基板上之催化劑點滴而得。奈米結構較佳地係使用以各種化學氣相沉積法為基礎之方法中任一者來生長,但也可使用任何標準技術來生長或形成。
以一黏性聚合物(或其它絕緣材料)旋塗所得之奈米結構以形成一具有內嵌式奈米結構之薄膜之第二步驟(702),可使用形成用於該些奈米結構之載體(在一薄膜或其它層中)之例如旋塗法或等效技術之任何塗佈技術來完成,其中,該些奈米結構係內嵌於該載體內。這類載體可包括一黏性聚合物或可經由固化、加壓、加熱或其它等效製程來黏附至一晶粒及一接觸表面之任何其它等效材料。在此所述方法不限於旋塗得示範實施例或使用可被固化之黏性聚合物之示範實施例。
拋光該載體以得到一用於該些奈米結構之均勻想要長度之 第三步驟(703),可使用適合本科技之任何標準拋光技術來完成,不論是機械、化學或其它方式皆可。對於該些奈米結構是否得到該均勻想要長度之判定,可同樣使用習知技術或先前技術所知或所用之任何標準技術來進行。本步驟係選擇性的。
切割該載體以產生獨立墊片之第四步驟(704),可使用任何切割或其他產生一想要外形及尺寸之獨立墊片之標準技術來完成。
拔出該些獨立墊片(由內嵌於黏性聚合物之垂直對準奈米碳結構所構成之部分薄膜)之第五步驟(705),可使用任何拔出這類墊片之標準技術來完成。
施用每一個獨立墊片於一第一傳導表面(例如,一晶粒表面)及一第二傳導表面(例如,一在晶片上之接觸表面)之間之第六步驟(706),可使用任何施加及定位這類墊片於這類位置內之標準技術來完成。
固化該些墊片之第七步驟(707)產生一結合,其中,該墊片係夾在兩傳導表面之間並結合至兩傳導表面。本結合經由內嵌於該墊片內之奈米結構而在該二傳導表面間產生電或熱接觸。本步驟不限於固化一黏性聚合物;也可包括任何在內嵌於該墊片之奈米結構及該墊片一側上之晶粒及該墊片另一側上之接觸表面之間產生黏著之標準技術。
整個製程具有一些優勢:消除傳統凸塊的需求、降低該二傳導表面間之最小可行距離、降低該些接觸點之高度及寬度兩者、允許該些接觸點在數量及密度上的增加、消除與施加至該異向傳導薄膜之壓力程度之控制需求有關之複雜性、以奈米結構取代微粒而得更細微間距、及降低未對準風險。
來與目前根據球狀微粒之解決方案做比較時,與本範例一致的係控制每一微米的奈米結構(NS)個數之密度可增加有效接觸點。例如,100個奈米結構/微米平方(奈米結構具有一50奈米直徑)給予100個獨立接觸點(同時見圖4及圖5)。假設輸出入(I/O)點大小為20X20微米,則在那個區域內之獨立接觸點數可為4000。
範例2:產生彈簧負載連接之製程
一含垂直對準之奈米結構(NS)(彼此間互相平行定向並垂直於載體兩表面,且例如由範例1所述步驟所備製)之載體(其以可彎曲、聚醯亞胺或堅固材料為基礎),係置於一晶粒表面及一接觸表面之間。見圖2及圖4範例。
藉由固化包含垂直對準之奈米結構(使用熱或化學成份或光)之載體,該載體會收縮(減少該晶粒及接觸層間之距離)。
該載體之收縮會在該垂直對準的奈米結構上感應出一收縮力。該些奈米結構上之收縮力結果會稍稍彎曲該些奈米結構。然而,因該些奈米結構及該些環繞材料間之楊氏模數之差異之故,該些奈米結構會具有拉直傾向。
上述之力在該些奈米結構內產生〝彈簧負載〞力。當內嵌於該載體材料之奈米結構被置於該二傳導表面間時,該彈簧負載力會固定該些接觸至該些奈米結構末端。(見圖3A及圖3B範例。)
一種使用內嵌於載體之奈米結構來提供結合該晶粒至該基板、產生並固定該電子接觸以提供一彈簧負載連接之製程係示於圖8。與圖7那些步驟共有之圖8步驟在此係配合範例1做說明,此處不再重複。
在第六步驟(806)中固化具有內嵌式奈米結構之載體之墊片之期間,該固化製程可使用熱或化學成份或光以引起該載體收縮,藉以降低該晶粒及接觸層間之距離。
本範例之奈米結構在此可根據與範例1之奈米結構相同之方法來產生,尤其,可根據國際專利申請案PCT/SE2006/000487(其在此被一併整合參考之)中所述方法來生長,以透過形態、大小、長度、距離等等來說明控制。
本範例中所述製程可用以解決隨晶片軟板構裝應用所引起之引線斷裂及未對準的議題。
類似範例1之結構,該彈簧負載結構之特性包含:該些接觸構件(奈米結構)係垂直於該些連接表面,即使該些奈米結構彼此間係平行亦然。該些奈米結構特性可根據生長方法來設計。每一單位可與其它這類單位相結合以組合成進一步結構。
整個製程具有一些優勢:降低該二傳導表面間之最小可行距離、降低該些接觸點之高度及寬度兩者、允許該些接觸點在數量及密度上的增加而藉此增加有效接觸區域、消除與施加至該異向傳導薄膜之壓力程度之控制需求有關之複雜性、以奈米結構取代微粒而得更細微間距、降低未對準風險、及使用稍稍彎曲之奈米結構來固定置放在相對表面上之二點間之電接觸。當該些奈米結構稍稍被彎曲時,可極小化因該結合表面中之表面粗糙度所致之間隙產生。
來與目前根據球狀微粒的解決方案做比較時,與本範例一致的係可控制每一微米的奈米結構(NS)個數之密度而增加有效接觸點。例如, 範圍自1奈米至200奈米之可控制奈米結構直徑給予一預定的獨立接觸點及每一奈米平方的一接觸區域。
範例3:晶圓級凸塊技術(WLB)
本範例說明如何藉由在電子電路之輸出入點上生長一奈米結構矩陣而得晶圓級凸塊結構,藉以產生用於晶粒之電子組件。該方法也可為一以1公分至2奈米(典型地下達1微米)範圍內之任何間距進行結合及電及/或熱接觸以連接二表面/層(該晶粒或晶片之接觸表面/層,及該第一層所連接之晶粒或晶片之接觸層/表面)之方法,其中,該電/熱接觸構件係基於奈米結構。
下列三例說明可行實施例。
例1:在一晶圓之整合電路上之輸出入點上所生長之垂直對準奈米結構,藉以產生一矩陣結構並內嵌於一具有黏性之可固化(以紫外線/雷射/光來固化)的材料,其係對應至該晶粒所需連接之基板上之連接點。
例2:在一晶圓之整合電路上之輸出入點上所生長之垂直對準奈米結構,藉以產生一矩陣結構,其係對應至該晶粒所需連接之基板上之連接點,且該附接係透過傳統高溫焊接製程來進行。
例3:在一晶圓之整合電路上之輸出入點上所生長之垂直對準奈米結構,藉以產生一矩陣結構,其係對應至該晶粒所需連接之基板上之連接點。
大體上,類似於範例2和3之結構,該晶圓級凸塊結構之特性包含:該些接觸構件(奈米結構)係垂直於該些連接表面,即使該些奈米結構彼此間係平行亦然。該些奈米結構之特性可根據生長方法來設計。該些 垂直對準的奈米結構可形成具有自1毫米降至2奈米大小之連接結構族群。
該範例中之奈米結構在此可根據與範例1和2之奈米結構相同之方法來產生,尤其,可根據國際專利申請案PCT/SE2006/000487(其在此被一併整合參考之)中所述方法來生長,以透過形態、大小、長度、距離等等來說明控制。
一種提供一晶圓級凸塊之方法係示於圖9。與圖7和圖8那些相同之圖9步驟在此係配合範例1和2來說明,在此不再重複那些說明。
在目前系統中,凸塊可具有500微米及更小之直徑。本範例方法允許組合奈米結構族群,每一獨立族群具有與現今凸塊一樣的大小。然而,本技術也允許較小的凸塊,即使減少至包括單一奈米結構之凸塊亦然。
組合式凸塊也可由此處所述方法來形成。標準蒸鍍法、電鍍法及/或無電鍍法可在生長奈米結構後實行,以在需要處形成組合式凸塊。來自週期表之不同金屬/金屬材料,例如鈦、鉻、鎢化鈦、銅、金或任何其它合適金屬,可於生長奈米結構後被蒸鍍、電鍍及/或無電鍍。標準浸金製程也可實行以在需要處塗佈金。無電鍍製程可由調節處理、酸蝕刻、透過不同化學組成鍍上例如鎳、銅、鋅、錫之不同金屬或不同合金所構成。
100‧‧‧基板
110‧‧‧接觸墊片
200‧‧‧黏性聚合物
210‧‧‧奈米碳纖維
300‧‧‧元件層
310‧‧‧輸出入墊片
320‧‧‧鎢插塞
330‧‧‧金屬插塞

Claims (18)

  1. 一種接合膜,用以藉由該接合膜互連第一傳導表面及第二傳導表面,其中該接合膜包含複數個奈米結構,其被內嵌於聚合性載體中,該奈米結構係彼此平行定向且垂直於該聚合性載體之頂部及底部表面延伸,其中該聚合性載體經組態為:當安置在該第一傳導表面及該第二傳導表面之間時,黏附至該第一傳導表面及該第二傳導表面;及當經固化時收縮以在該奈米結構中提供彈簧負載力,藉以在該奈米結構及該第一傳導表面及該二傳導表面之每一者之間達到可靠的接觸。
  2. 如請求項第1項的接合膜,其中該奈米結構係電傳導性或熱傳導性。
  3. 如請求項第2項的接合膜,其中該奈米結構之每一者包含二或更多交互擴散材料,該二或更多交互擴散材料包含影響該複數個奈米結構之形態之至少一材料及影響該複數個奈米結構之電特性之至少一材料。
  4. 如請求項第3項的接合膜,其中該二或更多交互擴散材料之至少一材料係存在於該奈米結構之每一者之尖端及基底之至少一者處。
  5. 如請求項第3項的接合膜,其中該二或更多交互擴散材料之至少一材料係選自由非結晶矽及鍺所構成之族群。
  6. 一種電子裝置,其包含:電子構件,其具有傳導構件表面;基板,其具有傳導基板表面;及如請求項第1項的接合膜,其經安置於該傳導構件表面及該傳導基板 表面之間,其中被包含在該接合膜中的該聚合性載體是在固化狀態,使得被包含在該接合膜中的該奈米結構藉由彈簧負載力被擠壓靠向該傳導構件表面及該傳導基板表面。
  7. 一種互連具有傳導構件表面的電子構件及具有傳導基板表面的基板的方法,該方法包含以下步驟:將如請求項第1項的接合膜安置在該傳導構件表面及該傳導基板表面之間;及固化被包含在該接合膜中的該載體,以在被包含在該接合膜中的該奈米結構中提供彈簧負載力,藉以在該奈米結構及該傳導構件表面及該傳導基板表面之每一者之間達到可靠的接觸。
  8. 一種形成接合膜的方法,其包含以下步驟:在傳導基板上生長複數個奈米結構,以使得該奈米結構垂直於該傳導基板延伸,該奈米結構之每一者包含二或更多交互擴散材料,該二或更多交互擴散材料包含影響該複數個奈米結構之形態之至少一材料及影響該複數個奈米結構之電特性之至少一材料;在載體中塗覆該奈米結構,以在該傳導基板上形成該接合膜;及自該傳導基板拔出該接合膜。
  9. 如請求項第8項的方法,其進一步包含以下步驟:拋光該接合膜以提供均勻長度的該奈米結構。
  10. 如請求項第8項的方法,其進一步包含以下步驟:在當該基板具有安置於其上的該接合膜的同時切割該基板。
  11. 如請求項第8項的方法,其中該載體係黏性聚合物。
  12. 如請求項第8項的方法,其中該成長的步驟包含以下步驟:在該傳導基板上沉積一或更多中間層;在該一或更多中間層上沉積催化劑層;在不需先退火該基板下,加熱該基板至可形成該奈米結構的溫度;及在該溫度下在該催化劑層上成長二或更多奈米結構,其中該一或更多中間層之至少一者係與該催化劑層進行交互擴散,及其中該催化劑層及進行交互擴散之該一或更多中間層中之至少一者係存在於該奈米結構中。
  13. 如請求項第12項的方法,進一步包含以下步驟:利用金屬沉積法塗覆該奈米結構,以在該傳導基板上形成金屬內嵌式奈米結構。
  14. 一種使用奈米結構組件連接第一傳導表面至第二傳導表面的方法,該方法包含:產生奈米結構組件,其藉由:在該第一傳導表面上沉積一或更多中間層;在該一或更多中間層上沉積催化劑層;在不需先退火基板下,加熱該基板至可形成奈米結構的溫度;及在該溫度下在該催化劑層上成長二或更多奈米結構;及將該第二傳導表面接合至該奈米結構組件,藉以連接該第一傳導表面至該第二傳導表面,其中該一或更多中間層之至少一者係與該催化劑層進行交互擴散,及其中該催化劑層及進行交互擴散之該一或更多中間層中之至少一者係存在 於該奈米結構中,該奈米結構之每一者包含二或更多交互擴散材料,該二或更多交互擴散材料包含影響該複數個奈米結構之形態之至少一材料及影響該複數個奈米結構之電特性之至少一材料。
  15. 如請求項第14項的方法,進一步包含以下步驟:以黏性聚合物塗覆該奈米結構組件,以在該第一傳導表面上形成具有內嵌式奈米結構的膜,其中該接合的步驟包含以下步驟:將具有內嵌式奈米結構的該膜夾在該第一傳導表面及該第二傳導表面之間;及固化具有內嵌式奈米結構的該膜,藉以在該內嵌式奈米結構及該第一傳導表面及該二傳導表面之每一者之間達到可靠的接觸。
  16. 一種提供具有形成於其上的組合式凸塊的積體電路的方法,其包含以下步驟:提供包含複數個積體電路的晶圓,該積體電路之每一者具有I/O點;在該積體電路的該I/O點上成長垂直對準的奈米結構;在該積體電路上沉積金屬,以在該積體電路的該I/O點上形成組合式凸塊;及切割該晶圓,以分離具有形成於其上的組合式凸塊的該積體電路。
  17. 如請求項第16項的方法,其中該成長垂直對準的奈米結構的步驟包含以下步驟:在該積體電路的該I/O點上沉積一或更多中間層;在該一或更多中間層上沉積催化劑層; 在不需先退火該基板下,加熱該基板至可形成該奈米結構的溫度;及在該溫度下在該催化劑層上成長二或更多奈米結構,其中該一或更多中間層之至少一者係與該催化劑層進行交互擴散,及其中該催化劑層及進行交互擴散之該一或更多中間層中之至少一者係存在於該奈米結構中。
  18. 如請求項第17項的方法,其中該一或更多中間層之至少一者包含選自由非結晶矽及鍺所構成之族群中的材料。
TW104130921A 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層 TWI564980B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US97185907P 2007-09-12 2007-09-12
US97404507P 2007-09-20 2007-09-20

Publications (2)

Publication Number Publication Date
TW201601230A TW201601230A (zh) 2016-01-01
TWI564980B true TWI564980B (zh) 2017-01-01

Family

ID=40452247

Family Applications (3)

Application Number Title Priority Date Filing Date
TW105136856A TWI655695B (zh) 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層
TW104130921A TWI564980B (zh) 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層
TW097135028A TWI511208B (zh) 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW105136856A TWI655695B (zh) 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW097135028A TWI511208B (zh) 2007-09-12 2008-09-12 以奈米結構連接和結合相鄰層

Country Status (8)

Country Link
US (4) US8106517B2 (zh)
EP (1) EP2197782B1 (zh)
JP (4) JP5535915B2 (zh)
KR (1) KR101487346B1 (zh)
CN (2) CN104600057B (zh)
RU (1) RU2010114227A (zh)
TW (3) TWI655695B (zh)
WO (1) WO2009035393A1 (zh)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7687876B2 (en) * 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US7777291B2 (en) * 2005-08-26 2010-08-17 Smoltek Ab Integrated circuits having interconnects and heat dissipators based on nanostructures
JP5535915B2 (ja) * 2007-09-12 2014-07-02 スモルテック アーベー ナノ構造体による隣接層の接続および接合
JP5474835B2 (ja) 2008-02-25 2014-04-16 スモルテック アーベー ナノ構造処理のための導電性補助層の形成及び選択的除去
US8568027B2 (en) 2009-08-26 2013-10-29 Ut-Battelle, Llc Carbon nanotube temperature and pressure sensors
US20110076841A1 (en) * 2009-09-30 2011-03-31 Kahen Keith B Forming catalyzed ii-vi semiconductor nanowires
KR101709959B1 (ko) * 2010-11-17 2017-02-27 삼성전자주식회사 범프 구조물, 이를 갖는 반도체 패키지 및 반도체 패키지의 제조 방법
TW201225341A (en) 2010-12-13 2012-06-16 Hon Hai Prec Ind Co Ltd Light-emitting semiconductor chip and method for manufacturing the same
TWI438930B (zh) * 2010-12-13 2014-05-21 Hon Hai Prec Ind Co Ltd 半導體發光晶片及其製造方法
CN102569623A (zh) * 2010-12-14 2012-07-11 鸿富锦精密工业(深圳)有限公司 半导体发光芯片及其制造方法
US8558209B1 (en) 2012-05-04 2013-10-15 Micron Technology, Inc. Memory cells having-multi-portion data storage region
US9212960B2 (en) * 2012-10-22 2015-12-15 The Board Of Trustees Of The Leland Stanford Junior University Nanostructures with strain-induced resistance
US9249014B2 (en) 2012-11-06 2016-02-02 Infineon Technologies Austria Ag Packaged nano-structured component and method of making a packaged nano-structured component
US20150333024A1 (en) * 2013-01-09 2015-11-19 Hitachi Ltd Semiconductor device and method for manufacturing the same
US8907479B2 (en) 2013-03-11 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Treating copper surfaces for packaging
WO2014205193A1 (en) * 2013-06-21 2014-12-24 University Of Connecticut Low-temperature bonding and sealing with spaced nanorods
US8912637B1 (en) 2013-09-23 2014-12-16 Texas Instruments Incorporated Self-adhesive die
US9453774B2 (en) 2013-12-17 2016-09-27 The Board Of Trustees Of The Leland Stanford Junior University Surface area-based pressure sensing
EP3105300B1 (en) 2014-02-13 2019-08-21 Honeywell International Inc. Compressible thermal interface materials
US10329435B2 (en) 2014-07-01 2019-06-25 University Of Utah Research Foundation Electrothermal coating with nanostructures mixture and method for making the same
US10722174B2 (en) 2014-07-11 2020-07-28 The Board Of Trustees Of The Leland Stanford Junior University Skin-conformal sensors
US9625330B2 (en) 2014-08-01 2017-04-18 The Board Of Trustees Of The Leland Stanford Junior University Methods and apparatus concerning multi-tactile sensitive (E-skin) pressure sensors
US9397023B2 (en) * 2014-09-28 2016-07-19 Texas Instruments Incorporated Integration of heat spreader for beol thermal management
US10002826B2 (en) 2014-10-27 2018-06-19 Taiwan Semiconductor Manufacturing Company Semiconductor device structure with conductive pillar and conductive line and method for forming the same
JP6165127B2 (ja) * 2014-12-22 2017-07-19 三菱重工工作機械株式会社 半導体装置及び半導体装置の製造方法
US9544998B1 (en) * 2015-09-14 2017-01-10 The Boeing Company Growth of carbon nanotube (CNT) leads on circuits in substrate-free continuous chemical vapor deposition (CVD) process
US20170162536A1 (en) 2015-12-03 2017-06-08 International Business Machines Corporation Nanowires for pillar interconnects
US10781349B2 (en) 2016-03-08 2020-09-22 Honeywell International Inc. Thermal interface material including crosslinker and multiple fillers
JP6419362B1 (ja) 2016-06-10 2018-11-07 リンテック オブ アメリカ インコーポレーテッドLintec of America, Inc. ナノファイバーシート
DE102016220664A1 (de) * 2016-10-21 2018-04-26 Robert Bosch Gmbh Verbindungsmittel zum Verbinden der Anschlüsse eines integrierten Schaltkreises oder eines diskreten Halbleiters
US10590539B2 (en) 2017-02-24 2020-03-17 Lintec Of America, Inc. Nanofiber thermal interface material
US10381049B2 (en) * 2017-08-14 2019-08-13 Seagate Technology Llc Data storage device housing components having a polymeric element attached to a surface thereof
US11041103B2 (en) 2017-09-08 2021-06-22 Honeywell International Inc. Silicone-free thermal gel
CA2985254A1 (en) * 2017-11-14 2019-05-14 Vuereal Inc Integration and bonding of micro-devices into system substrate
WO2019118706A1 (en) 2017-12-13 2019-06-20 Analog Devices, Inc. Structural electronics wireless sensor nodes
JP6982308B2 (ja) * 2017-12-27 2021-12-17 株式会社ソフイア 遊技機
US10177058B1 (en) 2018-01-26 2019-01-08 Powertech Technology Inc. Encapsulating composition, semiconductor package and manufacturing method thereof
US11072706B2 (en) 2018-02-15 2021-07-27 Honeywell International Inc. Gel-type thermal interface material
US10833048B2 (en) * 2018-04-11 2020-11-10 International Business Machines Corporation Nanowire enabled substrate bonding and electrical contact formation
CN109796903B (zh) * 2019-03-08 2024-06-21 深圳市润沃自动化工程有限公司 一种异向性导电胶结构及其生产方法
US11195811B2 (en) * 2019-04-08 2021-12-07 Texas Instruments Incorporated Dielectric and metallic nanowire bond layers
US11373921B2 (en) 2019-04-23 2022-06-28 Honeywell International Inc. Gel-type thermal interface material with low pre-curing viscosity and elastic properties post-curing
DE102020116671A1 (de) 2020-06-24 2021-12-30 Nanowired Gmbh Waferbonding
CN214176013U (zh) * 2020-12-23 2021-09-10 迪科特测试科技(苏州)有限公司 半导体结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331209B1 (en) * 1999-04-21 2001-12-18 Jin Jang Method of forming carbon nanotubes
CN1676568A (zh) * 2004-04-02 2005-10-05 清华大学 一种热界面材料及其制造方法
TW200629510A (en) * 2004-11-04 2006-08-16 Koninkl Philips Electronics Nv Nanotube-based directionally-conductive adhesive

Family Cites Families (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5445895A (en) * 1977-09-17 1979-04-11 Toshiba Machine Co Ltd Saw with set wrest and automatic jigsaw having same
JPS6386458A (ja) * 1986-09-30 1988-04-16 Toshiba Corp バンプ付icチツプの製造方法、及び製造用ウエハ
US5818700A (en) * 1996-09-24 1998-10-06 Texas Instruments Incorporated Microelectronic assemblies including Z-axis conductive films
JP3372848B2 (ja) 1996-10-31 2003-02-04 キヤノン株式会社 電子放出素子及び画像表示装置及びそれらの製造方法
JP3740295B2 (ja) 1997-10-30 2006-02-01 キヤノン株式会社 カーボンナノチューブデバイス、その製造方法及び電子放出素子
JP3497740B2 (ja) 1998-09-09 2004-02-16 株式会社東芝 カーボンナノチューブの製造方法及び電界放出型冷陰極装置の製造方法
US6146227A (en) 1998-09-28 2000-11-14 Xidex Corporation Method for manufacturing carbon nanotubes as functional elements of MEMS devices
US6283812B1 (en) * 1999-01-25 2001-09-04 Agere Systems Guardian Corp. Process for fabricating article comprising aligned truncated carbon nanotubes
JP4078760B2 (ja) * 1999-07-23 2008-04-23 株式会社村田製作所 チップ型電子部品の製造方法
US6813017B1 (en) * 1999-10-20 2004-11-02 Becton, Dickinson And Company Apparatus and method employing incoherent light emitting semiconductor devices as particle detection light sources in a flow cytometer
US6213789B1 (en) * 1999-12-15 2001-04-10 Xerox Corporation Method and apparatus for interconnecting devices using an adhesive
US6297592B1 (en) 2000-08-04 2001-10-02 Lucent Technologies Inc. Microwave vacuum tube device employing grid-modulated cold cathode source having nanotube emitters
FR2815026B1 (fr) 2000-10-06 2004-04-09 Commissariat Energie Atomique Procede d'auto-organisation de microstructures ou de nanostructures et dispositif a microstructures ou a nanostructures
JP2002117791A (ja) 2000-10-06 2002-04-19 Hitachi Ltd 画像表示装置
JP2002141633A (ja) * 2000-10-25 2002-05-17 Lucent Technol Inc 垂直にナノ相互接続された回路デバイスからなる製品及びその製造方法
JP2002203473A (ja) 2000-11-01 2002-07-19 Sony Corp 冷陰極電界電子放出素子及びその製造方法、並びに、冷陰極電界電子放出表示装置
JP2002289086A (ja) 2001-03-27 2002-10-04 Canon Inc 電子放出素子、電子源、画像形成装置、及び電子放出素子の製造方法
EP1384322A1 (en) * 2001-03-30 2004-01-28 California Institute Of Technology Carbon nanotube array rf filter
US7084507B2 (en) * 2001-05-02 2006-08-01 Fujitsu Limited Integrated circuit device and method of producing the same
DE10127351A1 (de) * 2001-06-06 2002-12-19 Infineon Technologies Ag Elektronischer Chip und elektronische Chip-Anordnung
KR100470227B1 (ko) 2001-06-07 2005-02-05 두산디앤디 주식회사 화학기계적 연마장치의 캐리어 헤드
US6739932B2 (en) 2001-06-07 2004-05-25 Si Diamond Technology, Inc. Field emission display using carbon nanotubes and methods of making the same
JP4778667B2 (ja) * 2001-06-29 2011-09-21 富士通株式会社 アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法
US6982519B2 (en) 2001-09-18 2006-01-03 Ut-Battelle Llc Individually electrically addressable vertically aligned carbon nanofibers on insulating substrates
JP2003115257A (ja) 2001-10-03 2003-04-18 Sony Corp 冷陰極電界電子放出素子の製造方法、及び、冷陰極電界電子放出表示装置の製造方法
JP2003115259A (ja) 2001-10-03 2003-04-18 Sony Corp 電子放出装置及びその製造方法、冷陰極電界電子放出素子及びその製造方法、冷陰極電界電子放出表示装置及びその製造方法、並びに、薄膜のエッチング方法
AU2002354424A1 (en) 2001-12-06 2003-06-17 Pioneer Corporation Electron emitting device and method of manufacturing the same and display apparatus using the same
US6965513B2 (en) * 2001-12-20 2005-11-15 Intel Corporation Carbon nanotube thermal interface structures
SE0104452D0 (sv) 2001-12-28 2001-12-28 Forskarpatent I Vaest Ab Metod för framställning av nanostrukturer in-situ, och in-situ framställda nanostrukturer
FR2836280B1 (fr) 2002-02-19 2004-04-02 Commissariat Energie Atomique Structure de cathode a couche emissive formee sur une couche resistive
US6858197B1 (en) 2002-03-13 2005-02-22 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Controlled patterning and growth of single wall and multi-wall carbon nanotubes
JP4120918B2 (ja) * 2002-03-18 2008-07-16 富士通株式会社 柱状カーボン構造物の選択成長方法及び電子デバイス
SE0200868D0 (sv) 2002-03-20 2002-03-20 Chalmers Technology Licensing Theoretical model för a nanorelay and same relay
US6699779B2 (en) 2002-03-22 2004-03-02 Hewlett-Packard Development Company, L.P. Method for making nanoscale wires and gaps for switches and transistors
US6872645B2 (en) 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6831017B1 (en) * 2002-04-05 2004-12-14 Integrated Nanosystems, Inc. Catalyst patterning for nanowire devices
AU2003228720A1 (en) * 2002-04-29 2003-11-17 The Trustees Of Boston College Density controlled carbon nanotube array electrodes
FR2839505B1 (fr) 2002-05-07 2005-07-15 Univ Claude Bernard Lyon Procede pour modifier les proprietes d'une couche mince et substrat faisant application du procede
US6774052B2 (en) 2002-06-19 2004-08-10 Nantero, Inc. Method of making nanotube permeable base transistor
JP3890470B2 (ja) 2002-07-16 2007-03-07 日立造船株式会社 カーボンナノチューブを用いた電子放出素子用電極材料およびその製造方法
JP3892359B2 (ja) * 2002-07-25 2007-03-14 松下電器産業株式会社 半導体チップの実装方法
JP2005534515A (ja) 2002-08-01 2005-11-17 ステイト オブ オレゴン アクティング バイ アンド スルー ザ ステイト ボード オブ ハイヤー エデュケーション オン ビハーフ オブ ポートランド ステイト ユニバーシティー ナノスケール構造物を所定位置に合成する方法
US20040037972A1 (en) 2002-08-22 2004-02-26 Kang Simon Patterned granulized catalyst layer suitable for electron-emitting device, and associated fabrication method
US7175494B1 (en) 2002-08-22 2007-02-13 Cdream Corporation Forming carbon nanotubes at lower temperatures suitable for an electron-emitting device
US20060022191A1 (en) 2002-11-05 2006-02-02 Bakkers Erik Petrus A M Nanostructure, electronic device having such nanostructure and method of preparing nanostructures
CN1239387C (zh) 2002-11-21 2006-02-01 清华大学 碳纳米管阵列及其生长方法
WO2004051726A1 (ja) * 2002-11-29 2004-06-17 Nec Corporation 半導体装置およびその製造方法
US6984535B2 (en) 2002-12-20 2006-01-10 Cdream Corporation Selective etching of a protective layer to form a catalyst layer for an electron-emitting device
JP2004202602A (ja) 2002-12-24 2004-07-22 Sony Corp 微小構造体の製造方法、及び型材の製造方法
JP2004261875A (ja) 2003-01-09 2004-09-24 Sony Corp 転写用原盤の製造方法および転写用原盤、ならびに基板の製造方法および基板
US6764874B1 (en) 2003-01-30 2004-07-20 Motorola, Inc. Method for chemical vapor deposition of single walled carbon nanotubes
US7316061B2 (en) * 2003-02-03 2008-01-08 Intel Corporation Packaging of integrated circuits with carbon nano-tube arrays to enhance heat dissipation through a thermal interface
WO2004079450A1 (en) 2003-03-06 2004-09-16 Yissum Research Development Company Of The Hebrew University Of Jerusalem Method for manufacturing a patterned structure
JP4401094B2 (ja) * 2003-03-20 2010-01-20 富士通株式会社 炭素元素円筒型構造体へのオーミック接続構造及びその作製方法
US20040182600A1 (en) 2003-03-20 2004-09-23 Fujitsu Limited Method for growing carbon nanotubes, and electronic device having structure of ohmic connection to carbon element cylindrical structure body and production method thereof
CN100419943C (zh) 2003-04-03 2008-09-17 清华大学 一种场发射显示装置
US7608147B2 (en) 2003-04-04 2009-10-27 Qunano Ab Precisely positioned nanowhiskers and nanowhisker arrays and method for preparing them
SE0301236D0 (sv) 2003-04-28 2003-04-28 Chalmers Technology Licensing Method of manufacturing a nanoscale conductive device
KR100554155B1 (ko) 2003-06-09 2006-02-22 학교법인 포항공과대학교 금속/반도체 나노막대 이종구조를 이용한 전극 구조물 및그 제조 방법
KR100537512B1 (ko) 2003-09-01 2005-12-19 삼성에스디아이 주식회사 카본나노튜브구조체 및 이의 제조방법 그리고 이를 응용한전계방출소자 및 표시장치
JP4689218B2 (ja) 2003-09-12 2011-05-25 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2005116469A (ja) 2003-10-10 2005-04-28 Sony Corp 冷陰極電界電子放出素子の製造方法
JP4271544B2 (ja) * 2003-10-10 2009-06-03 リンテック株式会社 半導体装置の製造方法
US7459839B2 (en) 2003-12-05 2008-12-02 Zhidan Li Tolt Low voltage electron source with self aligned gate apertures, and luminous display using the electron source
WO2005064639A2 (en) 2003-12-22 2005-07-14 Koninklijke Philips Electronics N.V. Fabricating a set of semiconducting nanowires, and electric device comprising a set of nanowires
TWI234211B (en) * 2003-12-26 2005-06-11 Advanced Semiconductor Eng Method for forming an underfilling layer on a bumped wafer
JP4184306B2 (ja) 2004-03-18 2008-11-19 パイオニア株式会社 電子放出素子
JP4448356B2 (ja) 2004-03-26 2010-04-07 富士通株式会社 半導体装置およびその製造方法
US20060086994A1 (en) 2004-05-14 2006-04-27 Susanne Viefers Nanoelectromechanical components
US20050285116A1 (en) * 2004-06-29 2005-12-29 Yongqian Wang Electronic assembly with carbon nanotube contact formations or interconnections
JP2006108649A (ja) 2004-09-09 2006-04-20 Masaru Hori ナノインプリント用金型、ナノパターンの形成方法及び樹脂成型物
WO2006137893A2 (en) 2004-10-01 2006-12-28 Board Of Regents Of The University Of Texas System Polymer-free carbon nanotube assemblies (fibers, ropes, ribbons, films)
FR2876244B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant muni d'un ensemble de micropointes conductrices dures et procede de connexion electrique entre ce composant et un composant muni de protuberances conductrices ductiles
CN1976869B (zh) 2005-02-10 2010-12-22 松下电器产业株式会社 用于维持微细结构体的结构体、半导体装置、tft驱动电路、面板、显示器、传感器及它们的制造方法
KR100682863B1 (ko) 2005-02-19 2007-02-15 삼성에스디아이 주식회사 탄소나노튜브 구조체 및 그 제조방법과, 탄소나노튜브 구조체를 이용한 전계방출소자 및 그 제조방법
WO2006098026A1 (ja) * 2005-03-17 2006-09-21 Fujitsu Limited 接続機構、半導体パッケージ、およびその製造方法
KR101145146B1 (ko) 2005-04-07 2012-05-14 엘지디스플레이 주식회사 박막트랜지스터와 그 제조방법
US7687876B2 (en) 2005-04-25 2010-03-30 Smoltek Ab Controlled growth of a nanostructure on a substrate
US7402909B2 (en) * 2005-04-28 2008-07-22 Intel Corporation Microelectronic package interconnect and method of fabrication thereof
US8173525B2 (en) 2005-06-17 2012-05-08 Georgia Tech Research Corporation Systems and methods for nanomaterial transfer
JP4386012B2 (ja) * 2005-08-23 2009-12-16 株式会社デンソー バンプ接合体の製造方法
US7777291B2 (en) * 2005-08-26 2010-08-17 Smoltek Ab Integrated circuits having interconnects and heat dissipators based on nanostructures
KR101386268B1 (ko) 2005-08-26 2014-04-17 스몰텍 에이비 나노구조체에 기반한 인터커넥트 및 방열기
JP4855757B2 (ja) * 2005-10-19 2012-01-18 富士通株式会社 カーボンナノチューブパッド及び電子デバイス
KR100745734B1 (ko) * 2005-12-13 2007-08-02 삼성에스디아이 주식회사 탄소나노튜브의 형성방법 및 이를 이용한 전계방출소자의제조방법
US7371674B2 (en) * 2005-12-22 2008-05-13 Intel Corporation Nanostructure-based package interconnect
US8337979B2 (en) * 2006-05-19 2012-12-25 Massachusetts Institute Of Technology Nanostructure-reinforced composite articles and methods
JP4744360B2 (ja) * 2006-05-22 2011-08-10 富士通株式会社 半導体装置
KR100803194B1 (ko) 2006-06-30 2008-02-14 삼성에스디아이 주식회사 탄소나노튜브 구조체 형성방법
WO2008054283A1 (en) 2006-11-01 2008-05-08 Smoltek Ab Photonic crystals based on nanostructures
JP4870048B2 (ja) * 2007-08-20 2012-02-08 富士通株式会社 電子部品装置及びその製造方法
JP5535915B2 (ja) * 2007-09-12 2014-07-02 スモルテック アーベー ナノ構造体による隣接層の接続および接合
JP5474835B2 (ja) 2008-02-25 2014-04-16 スモルテック アーベー ナノ構造処理のための導電性補助層の形成及び選択的除去

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331209B1 (en) * 1999-04-21 2001-12-18 Jin Jang Method of forming carbon nanotubes
CN1676568A (zh) * 2004-04-02 2005-10-05 清华大学 一种热界面材料及其制造方法
TW200629510A (en) * 2004-11-04 2006-08-16 Koninkl Philips Electronics Nv Nanotube-based directionally-conductive adhesive

Also Published As

Publication number Publication date
US8253253B2 (en) 2012-08-28
TWI511208B (zh) 2015-12-01
TW201601230A (zh) 2016-01-01
WO2009035393A1 (en) 2009-03-19
JP6149077B2 (ja) 2017-06-14
US20090072408A1 (en) 2009-03-19
EP2197782A1 (en) 2010-06-23
CN104600057B (zh) 2018-11-02
JP2017199911A (ja) 2017-11-02
EP2197782B1 (en) 2020-03-04
JP5535915B2 (ja) 2014-07-02
KR101487346B1 (ko) 2015-01-28
CN101827782A (zh) 2010-09-08
JP2014177398A (ja) 2014-09-25
US8106517B2 (en) 2012-01-31
TW200913105A (en) 2009-03-16
CN101827782B (zh) 2014-12-10
KR20100063063A (ko) 2010-06-10
US20120301607A1 (en) 2012-11-29
US20120125537A1 (en) 2012-05-24
CN104600057A (zh) 2015-05-06
TWI655695B (zh) 2019-04-01
JP2016006902A (ja) 2016-01-14
EP2197782A4 (en) 2017-11-15
TW201709366A (zh) 2017-03-01
US8815332B2 (en) 2014-08-26
JP2011501725A (ja) 2011-01-13
RU2010114227A (ru) 2011-10-20
US20140360661A1 (en) 2014-12-11

Similar Documents

Publication Publication Date Title
TWI564980B (zh) 以奈米結構連接和結合相鄰層
KR101051351B1 (ko) 시트 형상 구조체와 그 제조 방법, 및 전자 기기와 그 제조방법
US8610290B2 (en) Fabricated adhesive microstructures for making an electrical connection
US7479702B2 (en) Composite conductive film and semiconductor package using such film
US8173260B1 (en) Nano-structure enhancements for anisotropic conductive adhesive and thermal interposers
JP5237242B2 (ja) 配線回路構造体およびそれを用いた半導体装置の製造方法
TWI255466B (en) Polymer-matrix conductive film and method for fabricating the same
JP5013116B2 (ja) シート状構造体及びその製造方法並びに電子機器
CN112053962A (zh) 一种系统级堆叠封装及其制备方法
JP7332956B2 (ja) フィラー含有フィルム
JP5003320B2 (ja) 導電性バンプとその製造方法およびそれらを用いた電子部品実装構造体とその製造方法
Lu et al. Conductive adhesives for flip-chip applications
JP2012129338A (ja) 半導体装置および半導体装置の製造方法
JP2010007076A (ja) 異方導電性接着フィルム