CN109791921A - 用于覆晶互连接上的固态扩散接合的具有精细间距的导线的制程与结构 - Google Patents

用于覆晶互连接上的固态扩散接合的具有精细间距的导线的制程与结构 Download PDF

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CN109791921A
CN109791921A CN201780061589.8A CN201780061589A CN109791921A CN 109791921 A CN109791921 A CN 109791921A CN 201780061589 A CN201780061589 A CN 201780061589A CN 109791921 A CN109791921 A CN 109791921A
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substrate
microns
nickel
diffusion bonding
copper conductor
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CN109791921B (zh
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潘宝梁
张志华
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Xiamen Jinbai Semiconductor Co ltd
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Jinbai Technology Co Ltd
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Abstract

本发明揭示一种半导体封装或可挠性基板上系统封装(system‑on‑flex package)，其包含接合结构，接合结构系利用固态扩散接合连接集成电路/晶片至精细间距(pitch)电路。复数导线形成在一基板上，每一导线包含五种不同导电材料，其具有不同熔点与不同塑性变形特性，导电材料针对被动元件的扩散接合与焊接而最佳化。

Description

用于覆晶互连接上的固态扩散接合的具有精细间距的导线的 制程与结构
技术领域
本发明涉及一种半导体封装，且特别关于一种具有固态扩散接合的半导体封装。
背景技术
随着输入输出埠在数量上的增加、元件尺寸的缩小、功能与速度上的增加，高密度互连(HDI)基板在市场需求上不断成长。相对刚性基材，胶带基材有许多常见的优点，包含1.具有较高电路密度的较精细的线宽与间隔；2.瘦轮廓与轻重量；3.较佳热性能。
随着输入输出埠在数量上的不断提升，覆晶是一个关键技术，其系能提供许多优点，例如高密度的输入输出埠、较细间距(pitch)的互连接技术、较佳电性能与热性能，其系能应用在特定的部份上。这对细间距的互连接技术而言，是个连续不断的需求，包含显示驱动器、互补式金氧半影像感测器、基频处理器与能量管理单元等等。
在下个世纪中，低成本与高可靠度的互连接制程在先进封装中扮演一个关键角色。扩散接合为金属或非金属的接合方法。此种接合方法是根据接合介面上元素的原子扩散原理而接合。在将集成电路/晶片连接到基板的扩散接合技术中，在接触界面上施加热和压力时，由于此接触界面具有作为可变形层的一部分，使得在压力下，此层的塑性变形使界面更快到达接合温度，以增强扩散能力，进而形成强健与稳定的接合。当接合间距减小到像接触点的10微米宽度与10微米或更小之间隔的程度，则有许多方面需要考虑。由于铜的优秀导电性与热导性，它可以是较佳导体。可变形层必须提供必要的电特性。可变形层必须在从接触时于均匀的压力下变形，并且在导线的接合表面上必须具有足够的顶部宽度，以便在可变形层上形成完全的接触界面和适当的表面。随着接合间距变得越来越紧密，根据目前的卷到卷(reel to reel)制造能力，传统的半加成和减成法具有将导线间距减小到20微米(μm)以下的限制。具体而言，难以将顶部和底部导线比例保持为1。一般来说，以扩散系数D表示的扩散率定义为D＝Do exp(-Q/RT)，其中Do取决于扩散原子的晶格类型与震荡频率的频率因素，Q为活化能，R为气体常数，T为克尔文(Kelvin)的温度。
原子扩散是一个热力学过程，其中材料的温度和扩散性是关键参数。蠕变(creep)机制允许材料流在扩散结合所需的接合界面处产生完全紧密接触。因此，导线的表面处理(surface finish)和接合温度与负载的选择是扩散接合过程中的重要因素。其他因素如塑性变形、导热性、热膨胀和接合环境也会影响接合过程，特别是在高接合温度下。
热压接合在使用金凸块的覆晶组装中有预期的应用。使用螺柱凸块法或电解镀金在基板上制作凸块。在接合过程中，拾取晶片并面向下对齐在加热的基板上的凸块。当接合元件往下压时，金凸块变形并与接合垫紧密接触，从而导致纯金属发生金属焊接。热压接合需要覆晶接合器，其能够产生摄氏300度的较高接合温度，具有大约100牛顿/凸块的力和基板与晶片之间较大范围的平行度。为了获得更好的接合，需要良好地控制温度和接合力。为了避免损坏半导体材料，接合力必须是渐变的。过大的接合力可能导致晶片钝化中产生裂缝，并且由于凸块的过度变形，有时会在细间距阵列中桥接凸块。导线的表面处理的选择方式对改善扩散接合制程是至关重要的。
美国专利证号8940581、8967452、8440506、9153551与7878385揭示热压缩制程。
发明内容
本发明的主要目的，在于提供一种半导体封装的热压缩接合方法。
本发明的另一目的，在于提供一种半导体封装的热压缩接合方法的改良式表面。
在本发明的一实施例中，半导体封装包含一可挠性基板；复数导线，设于可挠性基板上，每一导线包含至少五种不同导电材料，导电材料具有不同熔点与不同塑性变形特性，导电材料针对被动元件的扩散接合与焊接而最佳化；以及至少一晶粒，通过导线的至少其中之一的扩散接合设于基板上
在本发明的一实施例中，用于扩散接合的基板的制作方法，包含下列步骤：提供一可挠性基板；以及形成复数导线在可挠性基板上，且形成导线在可挠性基板的步骤更包含下列步骤：电解电镀复数铜导线在可挠性基板上，铜导线的间距(pitch)为15-30微米(μm)；无电极电镀一镍磷合金层在铜导线的顶表面与侧表面上；无电极电镀一钯层在镍磷合金层上；以及在钯层上浸镀一金层。完成的导线适合热压接合设有金凸块的一晶粒，也适合锡铅凸块的表面安装。
在本发明的一实施例中，半导体封装的制作方法，包含下列步骤：提供一基板；形成复数导线在基板上，形成导线在基板上的步骤更包含下列步骤：无电极电镀一镍磷种子层在基板上；电解电镀复数铜导线在镍磷种子层上，铜导线的间距(pitch)为15-30微米，每一铜导线的线宽为7.5微米，铜导线之间隔为7.5微米；无电极电镀一镍磷合金层在铜导线的顶表面与侧表面上；无电极电镀一钯层在镍磷合金层上；以及在钯层上浸镀一金层；形成一金凸块在一晶粒的表面上；以及利用金凸块的热压缩以扩散接合晶粒至导线的至少其一，以完成半导体封装。
兹为使贵审查委员对本发明的结构特征及所达成的功效更有进一步的了解与认识，谨佐以较佳的实施例图及配合详细的说明，说明如后：
附图说明
图1A与图1B为本发明的热压缩的接合方法的结构剖视图。
图2至图6为本发明的复数个实施例的结构剖视图。
图7A至图7E为本发明的第一实施例的各步骤结构剖视图。
图8A至图8F为本发明的第二实施例的各步骤结构剖视图。
图9至图11为本发明的第一实施例或第二实施例的接合步骤的结构剖视图。
图12为本发明的于固定时间及固定施力下的剪切强度的比较图。
图13为本发明的于固定接合压力与时间下的剪切强度的比较图。
图14为本发明的于固定接合压力与温度下的剪切强度的比较图。
图15为本发明的第一实施例的介面接合强度曲线图。
具体实施方式
本发明提供一种利用固态扩散或热压接合以形成半导体封装的方法。鉴于传统在覆晶技术上较佳的电特性、铜柱与焊接互连技术，利用超薄镍磷沉积法来形成无电极电镀镍/无电极电镀钯/浸镀金(Electroless Nickel/Electroless Palladium/ImmersionGold，ENEPIG)，以取代传统的电解表面处理(surface finish)技术。本发明提供一种ENEPIG制程的变化，其系能提供一种用于固态扩散接合的较佳接合结构。
本发明提供一种半导体封装或可挠性基板上系统封装(system-on-flex)的制作方法，其中半导体封装由接合结构组成，以连接集成电路/晶片至精细间距电路，并将此些接合结构加热与压制成固态扩散结合关系。基板利用覆晶方式设于晶粒上。接合结构由复数在基板上的导线所形成，每一导线包含五种不同导电材质，导电材质具有不同熔点与不同塑性变形特性，导电材料针对晶片的扩散接合与被动元件或封装的焊接而最佳化。被动元件利用表面安装技术与晶片/集成电路邻接。利用镍磷种子层的全加成或半加成制程对导线进行电镀。本发明能使用卷对卷(reel to reel)制造能力，降低接合间距(pitch)至小于16微米(μm)，使导线的长宽比(aspect ratio)大于1。此方法并未限制在具有信号金属层的基板，且有很广泛的应用，包含多层可挠性基板与折迭可挠式封装。
使用在导线上的扩散接合的方法尤其有助于制作许多装置，包含通讯装置、固定位置资料单元、可穿戴式电子装置、显示驱动器、互补式金氧半影像感测器、基频处理器、能量管理单元、记忆体、中央处理器、图形处理器与特殊应用集成电路，并应用在移动式/无线、消费、计算、医疗、工业与汽车技术中。
图1A为可挠性基板上系统封装或可挠性基板上晶片封装的示意图，其包含覆晶式集成电路/晶片，以热压缩接合方式在导线上进行接合。晶粒30在其下方有一金凸块32。图1B为晶粒30利用热压缩接合方式接合于导线24上的示意图，图中表示金凸块32的压缩。导线包含五种不同导电材质，导电材质具有不同熔点与不同塑性变形特性，导电材质针对高密度电路与热压缩接合而最佳化，以提供电性连接。导线经过热压缩接合，以接合至金电镀凸块，此导线的扫瞄电子显微镜(SEM)的图像可显示扩散接合变成固体的状况。
图2为可挠性基板上系统封装的示意图，其包含一晶粒/晶片30，晶粒/晶片30接合于基板10上。有许多电性连接24与介于晶片30与基板10之间的底部填充物36。在热压缩接合后，毛细状的底部填充物用来保护介于晶片与基板之间的电性连接，并补偿介于金凸块与可挠性基板之间的热膨胀率的差异，以增加最终产品的预期寿命。底部填充物36分配在覆晶式晶粒的一侧或更多侧，有时在多次分配过程中允许毛细作用发生。导线包含五种不同导电材质，导电材质具有不同熔点与不同塑性变形特性，导电材质针对高密度电路与热压缩接合而最佳化，以提供电性连接。
图3为可挠性基板上系统封装的示意图，其包含利用热压缩接合的至少一覆晶式晶粒30。在晶片与基板10之间，有金凸块32、电性连接24与毛细底部填充物36。被动元件40利用表面安装技术设于邻近晶片/集成电路。导线24上的表面处理系最佳化，以利用金凸块32而具有良好的扩散接合能力，并利用锡铅凸块38而具有良好的焊接能力。
图4为覆晶式封装的示意图，其中有两晶粒30a与30b利用金凸块32与热压缩接合技术，设于基板10上的导线24上。任何数量的晶粒都可利用此种方式设于基板上。如图4所示，最小晶粒间隙39可以控制在10微米(μm)以下，且在控制下的覆晶接合准确度为+/-2微米。
图5为晶片/晶粒利用热压缩接合制程，组合于折迭可挠式封装的示意图。至少一晶粒30利用热压缩接合制程设于基板10上。导线24a的表面处理进行最佳化，以利用金凸块32与基板10上其他地方的导线24b上的焊球，进行热压缩接合制程。基板10围绕加强件42折迭，且焊球44装设到加强件42的底表面上的基板的下侧的导线24b上。
图6为可挠性基板上系统封装的示意图，其包含利用热压缩接合的至少一覆晶式晶粒30。在晶片与基板10之间，有金凸块32、电性连接24与毛细底部填充物36。晶粒50系以覆晶方式接合于导线24上，并利用金线52接合于其他导线24。被动元件40利用表面安装技术设于邻近晶片/集成电路的位置。导线24上的表面处理系最佳化，以利用金凸块32而具有良好的扩散接合能力，并利用锡铅凸块38而具有良好的覆晶接合能力与焊接能力。
图1至图6的任何一实施例与未绘出的实施例都可以根据本发明的制程来制作。
针对覆晶式组装，全加成制程被预期来符合未来在细线与空间上的需求，此制程利用目前卷对卷制作能力来达成。内引脚接合的介于导线之间的间距系在10-30微米之间，较佳小于15微米，且线宽为7.5微米，线间隔为7.5微米。
请参阅图7A至图7E。以下介绍本发明的第一实施例的制程。基板10具有至少一金属层，且能够具有一或更多导电金属层。此外，可挠性基板10具有双面导电金属层或两个以上堆迭的导电金属层。可挠性基板的介电材料可为聚酰亚胺(PI)、液晶聚合物(LCP)、聚酯(PET)、聚萘二甲酸乙二醇酯(PEN)、聚四氟乙烯或一层压基板，此层压基板包含环氧树脂和双马来酰亚胺三嗪(BT)树脂，或聚四氟乙烯或改性聚四氟乙烯。
如图7A所示，使用无电极电镀制程将自催化镍磷(Ni-P)的种子层12形成到基板10，例如聚酰亚胺胶带上，种子层12的厚度在约0.09μm和0.11μm之间，较佳约0.1μm，以催化性活化聚酰亚胺胶带或任何其他介电表面。镍磷种子层的镍占96.5-97.5的重量百分比(wt％)，磷占2.5-3.5wt％。在某些应用中，取决于黏合需求，镍与磷的元素组成比例是不同的，镍磷种子层的厚度为0.1-1微米。铜对镍磷种子层的粘合强度超过8牛顿/公分。
镍磷种子层在摄氏180-200度下进行退火，并持续至少一小时，甚至高达五小时或更长，以增进介于聚酰亚胺与镍磷之间的介面粘合度。镍磷利用无电极电镀制程沉积，以催化性活化介电材质的表面。涂布光阻14，可为干性薄膜或液态光阻，较佳为正型光阻，其系形成于基板的种子层的表面。在光微影制程中，光阻经过曝光与显影，以形成细间距的导线或电路化的图案15，如图7B所示。
导电金属层16包含主动接合的导线与表面安装的接垫，并利用电解铜电镀的方式形成所需的厚度，约6微米，如图7C所示。铜是以高韧性且细粒状的方式沉积。沉积铜的延伸强度超过15％，抗拉强度则介于290-340牛顿/平方公厘。电解铜的硬度应为100HV(维克角锥数)，其纯度超过99.9％。在某些应用中，铜的厚度为2-12微米。电镀仅实施在未被光阻覆盖之间隔的区域上。在某些应用中，控制电镀以实现超过1的长宽比，利用此方法使导线的顶部与底部的比例超过1。在光阻遮罩14剥离后，便蚀刻镍磷种子层，其中光阻遮罩14并未被导电金属层覆盖，如图7D所示。
请参阅图7E，ENEPIG制程用来形成导线16的表面处理24。如图9所示，在传统的ENEPIG制程中，一开始镍磷层18无电极电镀于铜导线16的顶表面与侧表面。较佳地，镍磷层的厚度为0.5-5微米，较佳为1微米，以供细间距电路使用。镍磷种子层作为粘合促进剂，并保护铜导线免受ENEPIG制程影响。镍的硬度约为500HV，且在镍磷种子层中，镍有超过90％的纯度，其中有8-10％的磷，镍磷溶液的pH值维持在5.4与6.3之间。无电极电镀镍磷沉积物为无定形且非结晶的非磁性结构。
接着，自催化钯层20无电极电镀于镍磷层上，且自催化钯层20的厚度为0.05-0.4微米，较佳为0.05微米。钯的硬度为400-450HV，钯的纯度为98％，其中磷占1-2％。钯溶液的pH值为8-8.5。
最后，纯度99.9％的金层22以浸镀方式涂布于钯层上，其中金层22的厚度为0.03-0.1微米，较佳为0.05微米，此厚度适合覆晶式集成电路/晶片互连接的固态扩散接合。此外，金层22为细粒状的沉积物，其硬度约为100HV，金溶液的pH值为5.6-6.0。
最终的导线24包含五种不同导电材质，其具有不同熔点与不同塑性变形特性，如上面所述，导电材质针对被动元件的扩散接合与焊接而最佳化。虽然有两镍磷层，但此两层具有不同组成，因此有不同熔点与不同塑性变形特性，所以视为二不同材质。
图9为晶粒30的示意图，晶粒30具有位于下方的金凸块32。在ENEPIG制程后，凭借传统的网版印刷形成防焊漆(solder mask)34。或者，在ENEPIG制程前，防焊漆可以选择性形成。金凸块32是传统的镀金或金柱凸块。
如今，晶粒30对封装基板的导线24的覆晶式接合系利用热压缩接合来执行，如图10所示。此接合在介面上的接合温度为摄氏280-300度，且固定压力约为163百万帕(MPa)。在范围内的接合温度愈高，愈能提升金凸块对基板接垫的接合强度。
接着，请参阅图11。在热压接合后，提供毛细状的底部填充物36，以避免介于晶片30与基板10之间的电性连接受湿气、离子污染物、辐射与恶劣操作环境影响，并补偿介于金凸块32与可挠性基板10之间的热扩散率的差异，以增加最终产品的预期寿命。此底部填充物也可分配于覆晶式晶粒的一侧或多侧，有时在多次分配过程中允许毛细作用发生。
本发明的第二实施例的制程介绍如下，请参阅图8A至图8F。第二实施例为半加成制程，其系将铜制种子层形成于镍磷底层的顶部。半加成制程并不是针对较精细的接合间距，这是考虑到造成较弱的导线粘合的底切(under cut)现象。
可挠性基板10如第一实施例所述。如图8A所示，使用无电极电镀制程将镍磷种子层12形成到基板10，例如聚酰亚胺胶带上，种子层12的厚度在约0.09μm和0.11μm之间，较佳约0.1μm。镍磷种子层的镍占96.5-97.5的重量百分比(wt％)，磷占2.5-3.5wt％。在某些应用中，取决于粘合需求，镍与磷的元素组成比例是不同的，镍磷种子层的厚度为0.1-1微米。镍磷利用无电极电镀制程来催化性活化介电表面。
接着，铜层17以厚度约为2微米电镀于镍磷种子层，铜层与镍磷层以摄氏180-200度进行退火，且持续至少一小时，甚至五小时或更多，以提升介于聚酰亚胺与镍磷之间的介面粘合度。
涂布光阻14，可为干性薄膜或液态光阻，较佳为正型光阻，其系形成于基板的铜层17的表面。在光微影制程中，光阻经过曝光与显影，以形成细间距的导线或电路化的图案14，如图8B所示。
额外的铜16包含主动接合的导线与表面安装的接垫，并以电解铜镀方式电镀6微米于第一铜层17上，如图8C所示。在某些应用中，铜的厚度为2-12微米。
如今，剥离光阻遮罩14如图8D所示。铜层17与镍磷层12被蚀刻，如图8E所示。如图8F所示，修改过的ENEPIG制程用来形成导线16的表面处理24，如第一实施例所描述的。
在另一实施例中，镍层与金层电解电镀在铜导线上，以代替在导线上的修改后ENEPIG涂层。此种选择可以使用在全加成或半加成制程上。然而，镍/金涂布对精细间距导线并非较佳选择。
图12为在固定时间与固定施力下的剪切强度的比较图，其中剪切强度系以百万帕(MPa)为单位，百万帕即为牛顿/平方公厘，剪切强度系以介于晶粒与导线之间的金凸块的热压缩接合的摄氏温度为函数。图12中比较于铜导线上的镍/金涂层100及本发明(镍磷/钯/金)的利用下方有镍磷种子层的位于铜导线上的修改后ENEPIG涂层102的情况。在本发明的制程中，如曲线102所示，剪切强度随着接合温度增加而增加。
图13为本发明的于固定接合压力与时间下的剪切强度的比较图，其中剪切强度系以百万帕(MPa)为单位，剪切强度系以于晶粒与基板之间的介面的热压缩接合的实际接合温度为函数。图13比较于铜导线上的镍/金涂层110及本发明(镍磷/钯/金)的利用下方有镍磷种子层的位于铜导线上的修改后ENEPIG涂层112的情况。对此两样本而言，剪切强度随着接合温度增加而增加。具有本发明的修改后ENEPIG涂层的全加成导线的样本的剪切强度(112)，相较镍金涂层的样本，随着接合温度增加而增加。
图14为本发明的在163百万帕(MPa)的固定接合压力与摄氏300度的剪切强度的比较图。剪切强度系以百万帕为单位，剪切强度系以介于晶粒与导线之间的金凸块的热压缩接合的接合时间的秒数为函数。图14比较于铜导线上的镍/金涂层120及本发明(镍磷/钯/金)的利用下方有镍磷种子层的位于铜导线上的修改后ENEPIG涂层122的情况。对此两样本而言，剪切强度随着时间增加而有些微增加。
对一晶粒进行拉力测试，此晶粒利用全加成热接合制程与第一实施例的修改后ENEPIG接合于一基板上，其中接合温度为摄氏340度。将一棍棒利用底部填充材料贴附于晶粒的上侧，并对棍棒进行拉伸，直到晶粒与基板之间的接合断裂为止。如图15所示，接合强度的测量值超过21MPa。
本发明的扩散接合制程使用于手机、平板电脑、笔记本电脑、超高画质电视(UHDTV)、台式电脑、游戏系统、安装盒(setup box)、服务器、车辆、超音波处理机、医疗装置与电脑断层扫描器。此外，被揭示的制程可以使用在通讯装置、固定位置资料单元、可穿戴式电子装置、显示驱动器、互补式金氧半影像感测器、基频处理器、能量管理单元、记忆体、中央处理器、图形处理器、特殊应用集成电路、发光二极管与射频装置，并应用在移动式/无线、消费、计算、医疗、工业与汽车技术中。
本发明的扩散接合制程利用五层ENEPIG涂布铜导线，并提供晶粒的较佳的热压缩接合技术，尤其是使用在覆晶制程中。使用此制程，晶粒与晶粒之间的最小空隙可以小于10微米，且覆晶接合准确度为+/-2微米。因为镍磷种子层的缘故，此制程可以制作间距为16微米甚至更小的细间距电路。利用全加成制程，导线的顶部与底部的长宽比大于1。改良式固态的金对金扩散接合在未来个人电子装置中有很大的价值。被揭示的导线的选择标准，例如塑性变形、导热性、热膨胀性与接合环境，都很适合扩散接合制程，尤其是对于高密度互连接技术。
以上所述者，仅为本发明一较佳实施例而已，并非用来限定本发明实施的范围，故举凡依本发明申请专利范围所述的形状、构造、特征及精神所为的均等变化与修饰，均应包括于本发明的保护范围内。

Claims (20)

1.一种半导体封装，其特征在于，包含：
一可挠性基板；
复数导线，设于该可挠性基板上，每一该导线包含至少五种不同导电材料，该些导电材料具有不同熔点与不同塑性变形特性，该些导电材料针对被动元件的扩散接合与焊接而最佳化；以及
至少一晶粒，通过该复数导线的至少其中之一的该扩散接合设于该基板上。
2.如权利要求1所述的半导体封装，其特征在于，该扩散接合为经由位于该晶粒上的一镀金凸块或一金柱凸块来进行。
3.如权利要求1所述的半导体封装，其特征在于，最接近该扩散接合的每一该导线的一第一层包含金，该金的纯度为99.9％，硬度为100HV，厚度为0.03-0.1微米。
4.如权利要求3所述的半导体封装，其特征在于，最接近该扩散接合的每一该导线的一第二层包含钯，该钯的纯度超过98％，其中有1-2％的磷，该钯的硬度为400-450HV，厚度为0.05-0.4微米。
5.如权利要求4所述的半导体封装，其特征在于，每一该导线的一第三层包含镍，该镍的纯度超过90％，其中有8-10％的磷，该镍的硬度为500HV，厚度为0.5-5微米。
6.如权利要求5所述的半导体封装，其特征在于，每一该导线的一第四层包含铜，该铜的纯度超过99.9％，硬度为100HV，厚度为2-12微米。
7.如权利要求6所述的半导体封装，其特征在于，该基板上每一该导线的底层包含镍与磷，其厚度为0.09-0.11微米。
8.如权利要求1所述的半导体封装，其特征在于，该可挠性基板包含至少一金属层与一介电材料，该介电材料包含聚酰亚胺、液晶聚合物、聚酯、聚萘二甲酸乙二醇酯、聚四氟乙烯或一层压基板，该层压基板包含环氧树脂和双马来酰亚胺三嗪树脂，或聚四氟乙烯或改性聚四氟乙烯。
9.如权利要求1所述的半导体封装，其特征在于，该半导体封装整合于下列其中之一中：智能手机、平板电脑、笔记本电脑、超高画质电视、台式电脑、游戏系统、电子安装盒、服务器、摩托车、超音波处理机、医疗装置、电脑断层扫描器、通讯装置、固定位置资料单元、可穿戴式电子装置、显示驱动器、互补式金氧半影像感测器、基频处理器、能量管理单元、记忆体、中央处理器、图形处理器、特殊应用集成电路、发光二极管与射频装置。
10.一种用于扩散接合的基板的制作方法，其特征在于，包含下列步骤：
提供一可挠性基板；以及
形成复数导线在该可挠性基板上，且形成该复数导线在该可挠性基板的步骤更包含下列步骤：
电解电镀复数铜导线在该可挠性基板上，该复数铜导线的间距为15-30微米；
无电极电镀一镍磷合金层在该复数铜导线的顶表面与侧表面上；
无电极电镀一钯层在该镍磷合金层上；以及
在该钯层上浸镀一金层，以形成适用于扩散接合的该基板。
11.如权利要求10所述的用于扩散接合的基板的制作方法，其特征在于，该铜导线的纯度超过99.9％，硬度为100HV，厚度为2-12微米，较佳厚度为6微米。
12.如权利要求10所述的用于扩散接合的基板的制作方法，其特征在于，该镍磷合金层利用自催化镍磷溶液来进行无电极电镀，该自催化镍磷溶液的pH值为5.4-6.3，该镍磷合金层的镍具有超过90％的纯度，其中有8-10％的磷，该镍磷合金层的硬度为500HV，厚度为0.5-5微米，较佳厚度为1微米。
13.如权利要求10所述的用于扩散接合的基板的制作方法，其特征在于，该钯层利用钯溶液来进行无电极电镀，该钯溶液的pH值为8-8.5，该钯层的钯具有超过98％的纯度，其中有1-2％的磷，该钯层的硬度为400-450HV，厚度为0.05-0.4微米，较佳厚度为0.05微米。
14.如权利要求10所述的用于扩散接合的基板的制作方法，其特征在于，该金层利用金溶液来进行浸镀，该金溶液的pH值为5.6-6，该金层的金具有99.9％的纯度，该金层的硬度为100HV，厚度为0.03-0.1微米，较佳厚度为0.05微米。
15.如权利要求10所述的用于扩散接合的基板的制作方法，其特征在于，更包含形成一镍磷种子层于该复数铜导线的下方，该镍磷种子层系于一无电极电镀制程中形成，该镍磷种子层的镍占96.5-97.5的重量百分比(wt％)，磷占2.5-3.5wt％，该镍磷种子层的厚度为0.1-1微米，较佳厚度为0.1微米。
16.如权利要求15所述的用于扩散接合的基板的制作方法，其特征在于，更包含以摄氏180-200度与1-5小时对该镍磷种子层进行退火，以增进该复数导线的接合强度。
17.如权利要求15所述的用于扩散接合的基板的制作方法，其特征在于，更包含：
形成一抗蚀图案在该镍磷种子层上；
电镀该复数铜导线在未被该抗蚀图案覆盖的该镍磷种子层上；以及
剥离该抗蚀图案；以及蚀刻未在该复数铜导线的下方的该镍磷种子层。
18.如权利要求17所述的用于扩散接合的基板的制作方法，其特征在于，该抗蚀图形由一图案化干膜抗蚀剂或一液体光致抗蚀剂所形成。
19.如权利要求15所述的用于扩散接合的基板的制作方法，其特征在于，更包含：
电镀一第一铜层于该镍磷种子层上；
形成一抗蚀图案在该第一铜层上；
电镀该复数铜导线在未被该抗蚀图案覆盖的该第一铜层上；
剥离该抗蚀图案；
蚀刻未被该复数铜导线覆盖的该第一铜层；以及
蚀刻未在该复数铜导线的下方的该镍磷种子层。
20.一种半导体封装的制作方法，其特征在于，包含下列步骤：
提供一基板；
形成复数导线在该基板上，形成该复数导线在该基板上的步骤更包含下列步骤：
无电极电镀一镍磷种子层在该基板上；
电解电镀复数铜导线在该镍磷种子层上，该复数铜导线的间距(pitch)为15-30微米，每一该铜导线的线宽为7.5微米，该复数铜导线之间隔为7.5微米；
无电极电镀一镍磷合金层在该复数铜导线的顶表面与侧表面上；
无电极电镀一钯层在该镍磷合金层上；以及
在该钯层上浸镀一金层；
形成一金凸块在一晶粒的表面上；以及
利用该金凸块的热压缩以扩散接合该晶粒至该复数导线的至少其一，以完成该半导体封装。
CN201780061589.8A 2016-10-06 2017-10-09 用于覆晶互连接上的固态扩散接合的具有精细间距的导线的制程与结构 Active CN109791921B (zh)

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