CN106575620A - 具有集成高电压器件的硅管芯 - Google Patents
具有集成高电压器件的硅管芯 Download PDFInfo
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- CN106575620A CN106575620A CN201480078916.7A CN201480078916A CN106575620A CN 106575620 A CN106575620 A CN 106575620A CN 201480078916 A CN201480078916 A CN 201480078916A CN 106575620 A CN106575620 A CN 106575620A
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- 239000002344 surface layer Substances 0.000 description 1
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- 229910052727 yttrium Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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Abstract
一种方法包括:在衬底上形成多个第一器件和多个第一互连件;将包括多个第二器件的第二器件层耦合到多个第一互连件中的一些第一互连件;以及在第二器件层上形成多个第二互连件。一种装置包括:第一器件层,其包括设置在多个第一互连件和多个第二互连件之间的多个第一电路器件;以及第二器件层,其包括与多个第一互连件和多个第二互连件的其中之一并置并耦合的多个第二器件;其中,多个第一器件和多个第二器件中的一个包括具有比多个第一器件和多个第二器件中的另一个更高的电压范围的器件。
Description
技术领域
集成电路,并且更具体地,单片三维集成电路。
背景技术
单片集成电路(IC)通常包括多个晶体管,例如在平面衬底(例如硅晶圆)之上制造的金属氧化物半导体场效应晶体管(MOSFET)。现在低于20nm的MOSFET栅极尺寸变得越来越难实现IC尺寸的横向缩放。随着器件尺寸继续减小,将会出现一个继续进行标准平面缩放变得不实际的点。这个拐点可以是由于经济学或物理学的原因,例如高得过分的电容或基于量子的可变性。一般被称为垂直缩放的在第三维中的器件的堆叠、或三维(3D)集成是朝着较大的晶体管密度的有前途的途径。
附图说明
图1示出包括多个器件层和多个互连层的单片三维集成电路的一个实施例的横截面侧视图。
图2A示出单片三维集成电路结构的另一实施例的横截面侧视图。
图2B示出单片三维集成电路结构的另一实施例的横截面侧视图。
图3示出具有器件层的衬底的横截面侧视图,器件层具有在其上形成的多个相对高电压摆动器件。
图4示出在引入与衬底的器件层并置的多个第一互连层之后的图3的结构。
图5示出在将第二器件层引入到与多个互连层并置的结构上之后的图4的结构。
图6示出在将第二多个互连件引入与第二器件层并置的结构上之后的图5的结构。
图7示出在将结构连接到载体晶圆之后的图6的结构。
图8示出在从结构中去除衬底之后并且在形成位于结构的一侧上并连接到第一多个互连件的接触点之后的图7的结构。
图9示出包括包含集成电路器件的第一器件层的半导体衬底的一部分的横截面侧视图,并且在将第一多个互连件形成在衬底上之后,其中一些互连件连接到第一器件层中的集成电路器件。
图10示出在将第二器件层引入与第一多个互连件并置的结构上之后的图9的结构。
图11示出在形成第二器件层中的若干第二集成电路器件之后的图10的结构。
图12示出在形成与第二集成电路器件中的一些器件并置并连接的第二多个互连件之后、并且在形成位于结构的一侧上并连接到第二多个互连件中的一些互连件的接触点之后的图11的结构。
图13是实施一个或多个实施例的内插件。
图14示出计算设备的实施例。
具体实施方式
公开了集成电路(IC)和形成IC的方法。在一个实施例中,描述了单片三维(3D)IC及其制造和用途,在一个实施例中,其包括器件层,器件层包括在管芯的相应器件层中具有不同电压范围的器件。通过至少部分地分离不同器件层中的不同电压范围的器件,单片3DIC为特定器件提供增加的面积,以允许器件密度增加并且允许在器件层处针对要在其上形成的特定器件调整制造技术。
在下面的描述中,将使用通常由本领域中的技术人员使用来将他们的工作的实质传达给本领域中的其他技术人员的术语来描述说明性实施方式的各方面。然而,对本领域中的技术人员显而易见的是,可以在只具有所述方面中的一些方面的情况下实践实施例。为了解释的目的,阐述了特定的数量、材料和配置,以便提供对说明性实施方式的彻底理解。然而,对本领域中的技术人员显而易见的是,可在没有具体细节的情况下实践实施例。在其它实例中,公知的特征被省略或简化,以便不使说明性实施方式难以理解。
各种操作将以对理解本文所述的实施例最有帮助的方式被依次描述为多个分立的操作,然而,描述的顺序不应被解释为暗示这些操作必须是顺序相关的。具体而言,这些操作不需要以呈现的顺序被执行。
可以在诸如半导体衬底等衬底上形成或实行实施方式。在一种实施方式中,半导体衬底可以是使用体硅或绝缘体上硅子结构形成的晶体衬底。在其它实施方式中,可以使用替代的材料来形成半导体衬底,这些材料可以或可以不与硅组合,其包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、砷化铟镓、锑化镓、或者III-V族或IV族材料的其它组合。虽然在这里描述了可以形成衬底的材料的几个示例,但是可以充当在其上可以构建半导体器件的基础的任何材料落在精神和范围内。
可以在衬底上,例如在如将在本文提到的器件层中制造多个晶体管,例如金属氧化物半导体场效应晶体管(MOSFET或简单地MOS晶体管)。在各种实施方式中,MOS晶体管可以是平面晶体管、非平面晶体管或这两者的组合。非平面晶体管包括FinFET晶体管(例如双栅极晶体管和三栅极晶体管)以及环绕栅极或全包围栅极晶体管(例如纳米带和纳米线晶体管)。虽然本文所述的实施方式可以只示出平面晶体管,但是应注意,也可以使用非平面晶体管来实行实施例。
每个MOS晶体管包括由至少两层(栅极电介质层和栅极电极层形成的栅极叠置体。栅极电介质层可以包括一层或层的叠置体。一个或多个层可以包括氧化硅、二氧化硅(SiO2)和/或高k电介质材料。高k电介质材料可以包括诸如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌等元素。可以在栅极电介质层中使用的高k材料的示例包括但不限于氧化铪、硅氧化铪、氧化镧、氧化镧铝、氧化锆、硅氧化锆、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。在一些实施例中,当使用高k材料时,可以在栅极电介质层上实行退火工艺以提高它的质量。
栅极电极层形成在栅极电介质层上并且可以由至少一个P型功函数金属或N型功函数金属组成,取决于晶体管是PMOS还是NMOS晶体管。在一些实施方式中,栅极电极层可以由两个或更多金属层的叠置体组成,其中一个或多个金属层是功函数金属层,并且至少一个金属层是填充金属层。
对于PMOS晶体管,可以用于栅极电极的金属包括但不限于钌、钯、铂、钴、镍和导电金属氧化物,例如氧化钌。P型金属层将实现具有在大约4.9eV与大约5.2eV之间的功函数的PMOS栅极电极的形成。对于NMOS晶体管,可以用于栅极电极的金属包括但不限于铪、锆、钛、钽、铝、这些金属的合金以及这些金属的碳化物,例如碳化铪、碳化锆、碳化钛、碳化钽和碳化铝。N型金属层将实现具有在大约3.9eV与大约4.2eV之间的功函数的NMOS栅极电极的形成。
在一些实施方式中,栅极电极可以由包括大体上平行于衬底的表面的底部部分和大体上垂直于衬底的顶表面的两个侧壁部分的“U”形结构组成。在另一实施方式中,形成栅极电极的金属层中的至少一个可以简单地是大体上平行于衬底的顶表面并且不包括大体上垂直于衬底的顶表面的侧壁部分的平面层。在其它实施方式中,栅极电极可以由U形结构与平面非U形结构的组合组成。例如,栅极电极可以由形成在一个或多个平面非U形层顶上的一个或多个U形金属层组成。
在一些实施方式中,一对侧壁间隔体可以形成在栅极叠置体的托住栅极叠置体相对侧上。侧壁间隔体可以由诸如氮化硅、氧化硅、碳化硅、掺杂有碳的氮化硅和氮氧化硅等材料形成。用于形成侧壁间隔体的工艺在本领域中是公知的并且通常包括沉积和蚀刻工艺步骤。在替代的实施方式中,可以使用多个间隔体对,例如两对、三对或四对侧壁间隔体可以形成在栅极叠置体的相对侧上。
如在本领域中公知的,源极区和漏极区形成在衬底内、与每个MOS晶体管的栅极叠置体相邻。通常使用注入/扩散工艺或蚀刻/沉积工艺来形成源极区和漏极区。在前一工艺中,诸如硼、铝、锑、磷或砷等掺杂剂可以被离子注入到衬底中以形成源极区和漏极区。激活掺杂剂并使它们进一步扩散到衬底中的退火工艺一般在离子注入工艺之后。在后一工艺中,衬底可以首先被蚀刻以在源极区和漏极区的位置处形成凹部。然后可以实行外延沉积工艺以用用于制造源极区和漏极区的材料填充凹部。在一些实施方式中,可以使用诸如硅锗或碳化硅等硅合金来制造源极区和漏极区。在一些实施方式中,外延沉积的硅合金可以在原位被掺杂有诸如硼、砷或磷等掺杂剂。在其它实施例中,可以使用诸如锗或III-V族材料或合金等一种或多种替代的半导体材料来形成源极区和漏极区。并且在其它实施例中,一个或多个金属层和/或金属合金层可以用于形成源极区和漏极区。
一个或多个层间电介质(ILD)沉积在MOS晶体管之上。可以使用因其在集成电路结构中的可应用性而出名的电介质材料(例如低k电介质材料)来形成ILD层。可以使用的电介质材料的示例包括但不限于二氧化硅(SiO2)、掺碳氧化物(CDO)、氮化硅、有机聚合物(例如八氟环丁烷或聚四氟乙烯、氟硅酸盐玻璃(FSG))和有机硅酸盐(例如硅倍半氧烷、硅氧烷或有机硅酸盐玻璃)。ILD层可以包括孔或气隙以进一步减小它们的介电常数。
通常,单片3D IC需要采用与管芯(器件层加上体衬底)相反的器件层形式的器件(例如晶体管)的两个或更多级。器件层被互连在衬底上和之上。例如,以第一半导体衬底开始,根据常规技术来制造器件(例如晶体管)的第一器件层,并且多个第一互连件连接到器件。包括器件的第二器件层或没有器件的施主衬底然后接合到第一衬底,并且施主衬底的一部分被劈开以留下与多个第一互连件并置或在多个第一互连件上的半导体薄膜的第二器件层。该方法当然仅仅是得到用于器件的第二层的单晶衬底的很多方式之一。在第二器件层在接合之前没有器件的场合,器件(例如晶体管)的第二器件层然后被制造在半导体薄膜中,并且跨级互连件可以形成在晶体管级之间。多个第二互连件形成在第二器件层上,这些互连件中的一些互连件连接到第二器件层中的器件,并且可操作用于将单片3D IC连接到衬底(例如封装衬底)的接触点被形成到多个第二互连件。
在前述示例中,第一器件层和第二器件层中的任一个可以包括具有比被包括在器件层中的另一个器件层中的器件更高的电压范围的器件。代表性地,具有更高的电压范围的器件包括但不限于可操作用于高频(例如射频(RF))和功率切换应用的器件。这样的器件的示例是相对大的(例如较老代)p型和/或n型器件、诸如氮化镓(GaN)或砷化镓(GaAs)等高电子迁移率晶体管。代表性地,这样的器件可以包括可承受增加的电压并提供增加的驱动电流的器件。这样的器件倾向于大于现有技术的逻辑器件。较低电压范围、一般较快器件包括诸如FinFET等逻辑器件,或可以以比较高电压范围器件更高的间距布置在器件层上的其它形状因数减小的器件。代表性地,当前FinFET具有零到1.5伏的电压范围。在一个实施例中较高电压范围器件是具有大于1.5伏(例如范围高达5.5伏)的电压范围的器件。
图1示出包括多个器件层和多个互连层的单片3D IC的一个实施例。参考图1,结构100包括衬底110,其例如是单晶半导体衬底(例如单晶硅)或绝缘体结构上的半导体。衬底110包括器件层120,其在该实施例中包括若干器件125。在一个实施例中,器件125包括高电压范围器件,例如用于高频(例如RF)和功率切换应用的器件。示例包括但不限于氮化镓(GaN)或大的(例如较老代)p型和/或n型晶体管器件。
与器件层120并置或在器件层120上的是连接到器件层120的器件125的多个互连件130。在器件125和器件层120包括具有比当前逻辑器件相对更高的电压范围的器件的场合,这样的多个互连件130具有被选择来适应例如电气负载的阻抗(例如阻抗匹配)的尺寸。图1示出具有可操作用于适应具有较高电压范围的器件的尺寸的互连件1306(大或厚的互连件)。代表性地,在一个实施例中,互连件1305具有大约栅极间距的至少0.67倍的厚度,并且互连件1306具有大于互连件1305的厚度的100到1000倍的厚度。图1示出在设备125与互连件1306之间的导电接触部127。多个互连件130还包括可操作用于适应较高速器件的一个或多个互连件1305(例如小或薄的互连件)。多个互连件130由诸如铜等导电材料形成并且通过层间电介质材料(例如氧化物)与彼此绝缘。覆盖多个互连件130中的最后的互连件(如所观察到的)的也是电介质材料。
图1示出与多个互连件130并置或者在多个互连件130上的器件层150。在一个实施例中,器件层150是单晶半导体(例如硅)层,其借助于层转移工艺从另一衬底转移到它在结构100中的位置。在一个实施例中器件层150包括若干器件,例如逻辑和/或高速器件(例如逻辑器件)的一个或多个阵列。在一个实施例中,这样的器件可以包括多栅极场效应晶体管(FET),例如FinFET。在一个实施例中,以比器件层120中的较高电压范围器件的布置更细的间距来布置这样的器件。在一个实施例中,器件层150中的器件中的一些器件连接到多个互连件130中的一些互连件。如图1所示,上覆器件层150是多个互连件170。多个互连件170连接到器件层150中的器件并具有在一个方面被选择为与这样的器件兼容(例如阻抗匹配)的尺寸。图1还示出嵌入在多个互连件170中的存储器元件160。存储器元件160包括例如可缩放双晶体管存储器(STTM)或电阻随机存取存储器(ReRAM)器件,其在一个实施例中连接到器件层150中的器件。图1示出在存储器元件160之一与多个互连件130中的一个互连件之间的连接162(导电接触部)和在存储器元件与多个互连件170的其中之一之间的连接164。在一个实施例中,器件(例如器件层150中的晶体管)可操作用于在写和读操作期间启用单独的存储器位。
与多个互连件170并置或在多个互连件170上的是暴露的接触点180,其提供用于至结构100的功率、地、VCC和VSS连接的接触点。这样的接触点可以用于将结构100连接到衬底,例如封装衬底。接触部180根据常规技术连接到包括布线层的金属化层,其中这样的金属化层与最后的互连件和结构的暴露表面绝缘。
图2A示出单片3D IC结构的另一实施例。参考图2A,结构200包括例如单晶半导体(例如硅)或绝缘结构上的半导体的衬底210。在一个实施例中,衬底210包括器件层220,其包括高速逻辑器件的一个或多个阵列。与图2A中的衬底210并置或在衬底210上的是例如铜互连件的多个互连件230,铜互连件代表性地与衬底210上的任何器件的阻抗匹配。设置或嵌入在多个互连件230中的是例如STTM或ReRAM的存储器元件260。在图2A所示的实施例中,与多个互连件230并置或在多个互连件230上的结构200包括器件层250。在一个实施例中,器件层250包括以比较大器件相对更细的间距设置或布置的高速器件(例如高速逻辑器件)的一个或多个阵列。器件层250可以通过层转移工艺从另一衬底被引入。器件层250中的器件中的一些器件通过导电接触部(例如接触部235)连接到多个互连件230中的一些互连件。
与图2A中的结构200的器件层250并置或在器件层250上的是多个互连件270。多个互连件270包括具有与器件层250中的器件阻抗匹配的尺寸的互连件。多个互连件270还可以包括具有适应较高摆动电压器件或较大(例如较老代)PMOS和/或NMOS器件的尺寸的互连件。图2A示出具有被选择为与硅器件层250中的高速器件匹配的尺寸的互连件2705和在器件层250中的器件与互连件2705之间的导电接触部255。图2A还示出多个互连件270的具有与较高或较大电压摆动器件匹配的尺寸的互连件2706。
与多个互连件270并置或在多个互连件270上的是器件层275。在一个实施例中,器件层275包括较高电压摆动器件,例如氮化硅器件或较大(例如较老代)PMOS和/或NMOS器件。在一个实施例中这样的器件通过导电接触部272连接到多个互连件270中的一些互连件,尤其连接到具有被选择为与器件层275中的器件阻抗匹配的尺寸的互连件2706。在一个实施例中器件层275通过层转移工艺从例如另一衬底被引入到结构200。图2A还示出在器件层275的和与互连件270并置或在互连件270上的表面相对的表面上形成的接触点280。在一个实施例中接触点280用于将结构200连接到衬底,例如封装衬底。
参考图2A的存储器元件260和结构200,图2A示出嵌入多个互连件230中的存储器元件260。存储器元件的一侧可以连接到多个互连件230中的互连件(通过导电接触连接点262),并且存储器元件的另一侧可以连接到多个互连件270中的互连件(通过导电接触连接点264)。器件层250中的器件(例如晶体管)通过导电接触部连接到存储器元件中的一些存储器元件并且可操作用于在写和读操作期间启用存储器元件。
图2B示出单片3D IC结构的另一实施例。参考图2B,结构300包括例如单晶半导体材料(例如硅)或绝缘体结构上的半导体的衬底310。在该实施例中,衬底310可选地包括器件层320,其包括高性能、高速器件,例如高速逻辑器件。与衬底310并置或在衬底310上的是具有适应器件层320中的阻抗匹配器件的尺寸的多个互连件330。图2B示出在多个互连件330中的一些互连件与器件层320中的器件之间的导电接触部325。嵌入在多个互连件330内的可选地是例如STTM和/或RERAM存储器元件的存储器元件360。
与图2B中的结构300的多个互连件330并置的是器件层350。在一个实施例中,器件层350包括高速器件,例如高速逻辑器件。器件层350中的这样的器件通过导电接触部335连接到多个互连件330中的一些互连件。
与器件层350并置或在器件层350上的是多个互连件370,其包括具有可操作用于与器件层350中的器件阻抗匹配的尺寸的互连件3705。图2A示出在互连件3705中的一些互连件与器件层350之间的导电接触部355。多个互连件370还包括具有可操作用于与高电压摆动器件阻抗匹配的尺寸的互连件3706。图2B示出被形成到互连件3706并暴露在结构300的一侧上的接触点380。接触点380可以用于将结构300连接到另一结构,例如封装衬底。
图3-8描述形成单片额D IC的一种方法。参考图3,在一个实施例中,高电压摆动器件和/或较大(例如较老代)PMOS和/或NMOS器件形成在衬底上。图3示出例如单晶半导体衬底(例如硅衬底)的衬底410。设置在衬底410上的是包括器件420A、420B和420C的器件层。器件层420A例如是GaN器件;器件层420B例如是较老代n型器件;并且器件420C代表性地是较老代p型器件。可以在高功率应用中使用这样的器件。
图4示出在引入与衬底410并置的多个互连件之后的图3的结构,其中多个互连件中的一些互连件连接到器件。图4示出多个互连件430,其包括具有与相对高电压摆动器件(例如器件420A、420B和420C)兼容(例如阻抗匹配)的尺寸的互连件4305。在一个实施例中,多个互连件430还包括具有与互连件4305的尺寸不同的尺寸的互连件4306。在一个实施例中,多个互连件430是铜材料并如在本领域中已知的那样被图案化。在器件与第一级互连件之间的器件层接触部425A、425B和425C可以是钨或铜,并且在互连件之间的跨级接触部是例如铜。互连件通过电介质材料(例如氧化物)而彼此绝缘并且与器件绝缘。
图5示出在将器件层引入到结构上之后的图4的结构。图5示出与多个互连件430并置或在多个互连件430上的器件层450。在一个实施例中,器件层450是单晶半导体层(例如,硅层),其包括通过层转移工艺引入的层。器件层450在转移时可以或可以不包括器件。在这样的层在转移时不包括器件的实施例中,多个器件可以在转移后形成。这样的器件包括高速器件,例如高速逻辑器件(例如,finFET器件)。还可以以比高电压摆动器件和/或与结构400上的其它器件层(例如包括器件420A-420C的器件层)相关联的较大(较老代)器件更细的间距将这样的器件布局或布置在器件层450中。在一个实施例中,这样的器件通过例如器件层与互连件之间的接触部455连接到多个互连件430的互连件4306。
图6示出在将多个互连件引入结构上之后的图5的结构。图6示出与器件层450并置或在器件层450上的多个互连件470上,其中多个互连件470中的一些互连件连接到器件层450中的器件。如图6所示,器件层450中的器件可以通过接触部458连接到多个互连件470中的一些互连件和/或通过接触部455连接到多个互连件430中的一些互连件。图6还示出嵌入在多个互连件470中的存储器元件。在一个实施例中,存储器元件(例如,STTM和/或ReRAM元件)在一端连接到多个互连件470(通过接触部464)并连接到器件450,并且通过接触部462连接到多个互连件430。器件层450中的器件可操作用于在存储器读和写操作之间启用存储器元件。
图6示出通过如在本领域中已知的电介质材料与彼此隔离并且与器件层隔离的多个互连件470。在一个实施例中,多个互连件470选自诸如通过电镀工艺引入的铜等材料,其中器件层450中的器件的接触部458代表性地是铜或钨,并且在互连件之间的接触部是铜。
图7示出在将结构连接到载体晶圆之后的图6的结构。在一个实施例中,来自图7的结构400倒置并接合到载体晶圆。图7示出例如硅或陶瓷或其它适当衬底的载体晶圆480。在一个实施例中,覆盖在载体晶圆480的表面上的是电介质材料层485(例如,氧化物层)。图7示出与载体晶圆480并置的多个互连件470。
图8示出在从结构去除衬底410之后的图7的结构。在一个实施例中,通过机械(例如研磨)或其它机制(例如蚀刻)来去除衬底410。在该实施例中,衬底410被去除到包括器件420A、420B和420C的器件层至少保持在载体晶圆上的程度。图8还示出在将接触点490引入到多个互连件430(尤其到互连件4305)之后的结构。图8还示出在具有例如氧化物的钝化层495的器件层的表面钝化之后的结构。接触点490可以用于将结构400连接到衬底,例如封装衬底。一旦被形成,所述结构(如果形成在晶圆级)就可以被单一化成分立的单片3D IC。图8代表性地示出在单一化之后的结构400并以鬼线示出通过与接触点480的焊接连接将结构连接到封装衬底。
图9-12示出形成单片3D IC的方法的第二实施例。参考图9,在一个实施例中,诸如高速逻辑器件(例如FinFET)等高速器件形成在衬底上。图9示出例如单晶半导体材料(例如单晶硅)的衬底510。设置在衬底510上的是包括相对高速器件的一个或多个阵列的器件层520。在一个实施例中,与图9中的器件层520并置或在器件层520上的是被选择为具有与器件层520中的细间距高速器件兼容(例如,阻抗匹配)的尺寸的多个互连件530。可以通过本领域中已知的工艺来形成这样的多个互连件530。图9还示出在器件层520中的器件与多个互连件530中的一些互连件之间的器件级接触部525。这样的器件级接触部525可以代表性地是钨材料或铜材料。在互连件之间的接触部代表性地是铜材料。多个互连件530通过层间电介质材料(例如氧化物)与彼此分开。图9还示出覆盖多个互连件530中的最后的互连件(如所观察到的)的电介质材料的层535。
图10示出在将器件层转移到结构上之后的图9的结构。代表性地,包括被指定为器件层的区域的牺牲衬底可以接合到结构500,使得所指定的器件层与多个互连件530并置(在层535上)。一旦包括器件层的牺牲衬底接合到结构500,就可以例如通过机械手段(例如研磨)或其它机制(例如蚀刻)来去除牺牲衬底。图10示出与多个互连件530并置的器件层550。
图11示出在形成第二器件层550中的器件之后的图10的结构。在一个实施例中,形成在器件层550中的器件包括具有较高电压范围并具有比器件层520中的器件更大的间距的器件。图11代表性地示出器件560A以及器件560B和器件560C,器件560A是例如用于高功率应用的GaN器件,并且器件560B和器件560C分别是例如较老代p型和n型器件。可以如本领域中已知的那样形成这样的器件。
图12示出在引入与器件层550并置的多个互连件570之后的图11的结构。在一个实施例中,多个互连件570被选择为与器件560A、560B和560C(例如,高电压范围器件)兼容。于是,多个互连件570的尺寸是针对它的兼容性(例如,阻抗匹配)来选择的。图12示出通过可以是钨或铜的接触部575连接到器件层550中的器件的多个互连件575中的一些互连件。多个互连件570代表性地是例如通过电镀工艺形成的铜材料。多个互连件570通过层间电介质材料(例如氧化物)与彼此绝缘。电介质材料层还设置在多个互连件570的最后的互连件上(如所观察到的)。
图12还示出被形成到多个互连件570之一的接触部580。这样的接触部580可以用于将结构500连接到另一结构,例如封装衬底。这样的接触部被示为直接连接到多个互连件570中的一些互连件。应认识到,这样的接触部可以被形成到连接到多个互连件570中的一些互连件的金属化层。
在上面的实施例中,器件层转移到没有器件的结构。在另一实施例中,诸如器件560A、器件560B和器件560C等器件可以形成在牺牲衬底上并且在这样的形成之后被转移。在另一实施例中,器件560A、器件560B和器件560C中的一些可以在转移之前形成,而其它器件在转移之后形成。
图13示出包括本发明的一个或多个实施例的内插件600。内插件600是用于将第一衬底602桥接到第二衬底604的介于其间的衬底。第一衬底602可以是例如集成电路管芯。第二衬底604可以是例如存储器模块、计算机母板或另一集成电路管芯。通常,内插件600的目的是将连接扩展到较宽的间距或将连接重新布线到不同的连接。例如,内插件600可以将集成电路管芯耦合到球栅阵列(BGA)606,球栅阵列(BGA)606可以随后耦合到第二衬底604。在一些实施例中,第一和第二衬底602/604附接到内插件600的相对侧。在其它实施例中,第一和第二衬底602/604附接到内插件600的同一侧。并且在其它实施例中,三个或更多衬底通过内插件600的方式来互连。
内插件600可以由环氧树脂、纤维玻璃加强的环氧树脂、陶瓷材料或诸如聚酰亚胺等聚合物材料形成。在其它实施方式中,内插件可以由替代的刚性或柔性材料形成,这些材料可以包括与上面所述的在半导体衬底中使用的材料相同的材料,例如硅、锗、以及其它III-V族和IV族材料。
内插件可以包括金属互连件608和通孔610,包括但不限于穿硅通孔(TSV)612。内插件600还可以包括嵌入式器件614,包括无源和有源器件二者。这样的器件包括但不限于电容器、去耦电容器、电阻器、电感器、熔丝、二极管、变压器、传感器和静电放电(ESD)器件。还可以在内插件600上形成更复杂的器件,例如射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件。
根据本发明的实施例,可以在内插件600的制造中使用本文公开的装置或工艺。
图14示出根据本发明的一个实施例的计算设备700。计算设备700可包括若干部件。在一个实施例中,这些部件附接到一个或多个母板。在替代的实施例中,这些部件被制造到单个片上系统(SoC)管芯上而不是母板上。在计算设备700中的部件包括但不限于集成电路管芯702和至少一个通信芯片708。在一些实施方式中,通信芯片708被制造为集成电路管芯702的部分。集成电路管芯702可以包括CPU 704以及常常用作高速缓存存储器的管芯上存储器706,其可以由例如嵌入式DRAM(eDRAM)或自旋转移矩存储器(STTM或STTM-RAM)的技术来提供。
计算设备700可以包括可以或可以不物理和电耦合到母板或被制造在SoC管芯内的其它部件。这些其它部件包括但不限于易失性存储器710(例如DRAM)、非易失性存储器712(例如ROM或闪存)、图形处理单元714(GPU)、数字信号处理器716、加密处理器742(在硬件内执行加密算法的专用处理器)、芯片组720、天线722、显示器或触摸屏显示器724、触摸屏控制器726、电池728或其它电源、功率放大器(未示出)、全球定位系统(GPS)设备744、罗盘730、运动协处理器或传感器732(其可以包括加速度计、陀螺仪和罗盘)、扬声器734、照相机736、用户输入设备738(例如键盘、鼠标、手写笔和触控板)和大容量存储设备740(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等)。
通信芯片708实现用于往返于计算设备700传输数据的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经调制的电磁辐射经由非固体介质来传递数据的电路、设备、系统、方法、技术、通信通道等。该术语并不暗示相关联的设备不包含任何线,虽然在一些实施例中它们可以不包含线。通信芯片708可以实现多种无线标准或协议中的任一个,包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线协议。计算设备700可以包括多个通信芯片708。例如,第一通信芯片708可以专用于较短距离无线通信,例如Wi-Fi和蓝牙,并且第二通信芯片708可以专用于较长距离无线通信,例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
在一个实施例中,计算设备700的处理器704是根据上述实施例形成的包括多个器件层的单片3D IC。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
在一个实施例中,通信芯片708也可以包括根据上述实施例形成的包括多个器件层的单片3D IC。
在其它实施例中,容纳在计算设备700内的另一部件可以包含根据上述实施方式的包括多个器件层的单片3D IC。
在各种实施例中,计算设备700可以是膝上型计算机、上网本计算机、笔记本计算机、超级本计算机、智能电话、平板电脑、个人数字助理(PDA)、超级移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录仪。在其它实施方式中,计算设备700可以是处理数据的任何其它电子设备。
示例
示例1是一种方法,其包括:在衬底上形成多个第一器件;在衬底上形成多个第一互连件,其中,多个第一互连件中的一些第一互连件耦合到多个第一器件中的一些第一器件;将没有多个第二器件的器件层和包括多个第二器件的器件层的其中之一耦合到多个第一互连件中的一些第一互连件,在没有多个第二器件的器件层被耦合的条件下,该方法包括:此后在器件层上形成多个第二器件;在第二器件层上形成多个第二互连件,其中,多个第二互连件中的一些第二互连件耦合到多个第二器件中的一些第二器件;以及将接触点形成到第一多个互连件中的互连件和第二多个互连件中的互连件的其中之一,接触点可操作用于连接到外部源。
在示例2中,示例1的多个第一器件和多个第二器件的其中之一包括具有比多个第一器件和多个第二器件中的另一个更高的电压范围的器件。
在示例3中,示例1的衬底包括牺牲衬底,该方法还包括:将牺牲衬底耦合到载体衬底;以及去除牺牲衬底。
在示例4中,示例3的多个第二器件包括以比多个第一器件的间距更细的间距设置的器件,并且将牺牲衬底耦合到载体衬底包括将多个第二互连件设置在器件层与载体衬底之间。
在示例5中,示例4的接触点耦合到多个第二互连件中的一些第二互连件。
在示例6中,示例1的形成多个第二互连件包括:形成包括多个第二互连件和多个存储器器件的互连叠置体。
在示例7中,示例1的多个第一器件包括以比多个第一器件的间距更细的间距设置的器件,并且多个第二器件中的一些第二器件具有比多个第二器件更高的电压范围。
在示例8中,示例7的形成多个第二器件包括:将第二器件耦合到第一多个互连件中的至少一个。
在示例9中,示例7的将器件层耦合到衬底上的第一多个第一互连件包括:在第二衬底上的器件层中形成多个第二器件,以及在将器件层耦合到第一多个互连件之后,该方法包括使第二衬底变薄。
在示例10中,示例7的接触点耦合到第二多个互连件中的一些互连件。
示例11是通过示例1-10的方法中的任一个形成的三维集成电路。
示例12是一种装置,其包括:第一器件层,其包括设置在衬底上的多个第一互连件与多个第二互连件之间的多个第一电路器件,其中,多个第一互连件中的一些第一互连件和多个第二互连件中的一些第二互连件耦合到多个第一电路器件中的一些第一电路器件;第二器件层,其包括与多个第一互连件和多个第二互连件的其中之一并置并与其耦合的多个第二器件;以及接触点,其耦合到多个第一互连件中的一些第一互连件和多个第二互连件中的一些第二互连件的其中之一,接触点可操作用于连接到外部源,其中,多个第一器件和多个第二器件的其中之一包括具有比多个第一器件和多个第二器件中的另一个更高的电压范围的器件。
在示例13中,示例12的第一器件层的多个第一电路器件包括以比多个第二电路器件的间距更细的间距设置的器件,并且多个第一互连件设置在载体衬底与第一器件层之间。
在示例14中,示例13的接触点耦合到多个第二互连件中的一些第二互连件。
在示例15中,示例12的多个存储器器件设置在多个第一互连件和多个第二互连件的其中之一内。
在示例16中,示例12的接触点包括电路接触点,该装置还包括封装,封装包括耦合到电路接触点的封装接触点。
示例17是一种方法,其包括:形成包括多个第一电路器件的第一器件层;形成多个第一互连件,其中,多个第一互连件中的一些第一互连件耦合到多个第一器件中的一些第一器件;将没有多个第二器件的第二器件层和包括多个第二器件的器件层的其中之一与多个第一连接中的一些第一互连件并置,在没有多个第二器件的器件层被耦合的条件下,该方法包括:形成多个第二器件;在第二器件层上形成多个第二互连件,其中,多个第二互连件中的一些第二互连件耦合到多个第二器件中的一些第二器件;以及将接触点与第一多个互连件中的一些互连件和第二多个互连件中的一些互连件的其中之一并置,接触点可操作用于连接到外部源,其中,多个第一器件和多个第二器件中的一个包括具有比多个第一器件和多个第二器件中的另一个更高的电压范围的器件。
在示例18中,示例17的第一器件层形成在牺牲衬底上,该方法还包括:将牺牲衬底耦合载体衬底;以及去除牺牲衬底。
在示例19中,示例18的多个第二器件包括以比多个第一器件的间距更细的间距设置的器件,并且将牺牲衬底耦合到载体衬底包括将多个第二互连件设置在器件层与载体衬底之间。
在示例20中,示例19的接触点与多个第二互连件中的一些第二互连件并置。
在示例21中,示例17的形成多个第二互连件包括:形成包括多个第二互连件和多个存储器器件的互连叠置体。
在示例22中,示例17的将第二器件层与第一多个第一互连件并置包括:在衬底上的器件层中形成多个第二器件,以及在使第二器件层与第一多个互连件耦合并置之后,该方法包括使第二衬底变薄。
在示例23中,示例17的接触点耦合到第二多个互连件中的一些互连件。
示例24是通过示例17-23的方法中的任一个形成的三维集成电路。
本发明的所示实施方式的上面的描述(包括在摘要中描述的内容)并非旨在是详尽的或者将本发明限制为所公开的精确形式。尽管为了例示的目的在本文中描述了本发明的具体实施方式和示例,但是如相关领域技术人员将认识到的,各种等同的修改在本发明的范围内是可能的。
鉴于以上具体实施方式,可以对本发明做出这些修改。在所附权利要求中使用的术语不应当被解释为将本发明限制为在说明书和权利要求书中公开的具体实施方式。更确切地,本发明的范围应当全部由所附权利要求来确定,所附权利要求是根据权利要求解释的所建立的原则来解释的。
Claims (24)
1.一种方法,包括:
在衬底上形成多个第一器件;
在所述衬底上形成多个第一互连件,其中,所述多个第一互连件中的一些第一互连件耦合到所述多个第一器件中的一些第一器件;
将没有多个第二器件的第二器件层和包括多个第二器件的器件层的其中之一耦合到所述多个第一互连件中的一些第一互连件,在没有所述多个第二器件的器件层被耦合的条件下,所述方法包括:此后在所述器件层上形成多个第二器件;
在所述第二器件层上形成多个第二互连件,其中,所述多个第二互连件中的一些第二互连件耦合到所述多个第二器件中的一些第二器件;以及
将接触点形成到所述第一多个互连件中的一些互连件和所述第二多个互连件中的一些互连件的其中之一,所述接触点能够操作用于连接到外部源。
2.如权利要求1所述的方法,其中,所述多个第一器件和所述多个第二器件的其中之一包括比所述多个第一器件和所述多个第二器件的其中之另一具有更高的电压范围的器件。
3.如权利要求1-2中的任一项所述的方法,其中,所述衬底包括牺牲衬底,所述方法还包括:
将所述牺牲衬底耦合到载体衬底;以及
去除所述牺牲衬底。(FLW1)
4.如权利要求3所述的方法,其中,所述多个第二器件包括以比所述多个第一器件的间距更细的间距设置的器件,并且将所述牺牲衬底耦合到所述载体衬底包括将所述多个第二互连件设置在所述器件层与所述载体衬底之间。(FLW1)
5.如权利要求4所述的方法,其中,所述接触点耦合到所述多个第二互连件中的一些第二互连件。(FLW1)
6.如权利要求1-2中的任一项所述的方法,其中,形成多个第二互连件包括:形成包括所述多个第二互连件和多个存储器器件的互连叠置体。
7.如权利要求1-2中的任一项所述的方法,其中,所述多个第一器件包括以比所述多个第一器件的间距更细的间距设置的器件,并且所述多个第二器件中的一些第二器件比所述多个第二器件具有更高的电压范围。(FLW2)
8.如权利要求7所述的方法,其中,形成多个第二器件包括将所述第二器件耦合到所述第一多个互连件中的至少之一。(FLW2)
9.如权利要求7所述的方法,其中,将器件层耦合到所述衬底上的所述第一多个第一互连件包括:在第二衬底上的器件层中形成所述多个第二器件,以及在将所述器件层耦合到所述第一多个互连件之后,所述方法包括使所述第二衬底变薄。(FLW2)
10.如权利要求7所述的方法,其中,所述接触点耦合到所述第二多个互连件中的一些互连件。
11.一种三维集成电路,通过根据权利要求1-10中的任一项所述的方法形成。
12.一种装置,包括:
第一器件层,其包括设置在衬底上的多个第一互连件与多个第二互连件之间的多个第一电路器件,其中,所述多个第一互连件中的一些第一互连件和所述多个第二互连件中的一些第二互连件耦合到所述多个第一电路器件中的一些第一电路器件;
第二器件层,其包括与所述多个第一互连件和所述多个第二互连件的其中之一并置并耦合的多个第二器件;以及
接触点,其耦合到所述第一多个互连件中的一些互连件和所述第二多个互连件中的一些互连件的其中之一,所述接触点能够操作用于连接到外部源,
其中,所述多个第一器件和所述多个第二器件的其中之一包括比所述多个第一器件和所述多个第二器件的其中之另一具有更高的电压范围的器件。
13.如权利要求12所述的装置,其中,所述第一器件层的所述多个第一电路器件包括以比所述多个第二电路器件的间距更细的间距设置的器件,并且所述多个第一互连件设置在载体衬底与所述第一器件层之间。
14.如权利要求13所述的装置,其中,所述接触点耦合到所述多个第二互连件中的一些第二互连件。
15.如权利要求12-13中的任一项所述的装置,其中,多个存储器器件设置在所述多个第一互连件和所述多个第二互连件的其中之一内。
16.如权利要求12-13中的任一项所述的装置,其中,所述接触点包括电路接触点,所述装置还包括封装,所述封装包括耦合到所述电路接触点的封装接触点。
17.一种方法,包括:
形成包括多个第一电路器件的第一器件层;
形成多个第一互连件,其中,所述多个第一互连件中的一些第一互连件耦合到所述多个第一器件中的一些第一器件;
将没有多个第二器件的第二器件层和包括多个第二器件的器件层的其中之一与所述多个第一互连件中的一些第一互连件并置,在没有所述多个第二器件的器件层被耦合的条件下,所述方法包括:形成多个第二器件;
在所述第二器件层上形成多个第二互连件,其中,所述多个第二互连件中的一些第二互连件耦合到所述多个第二器件中的一些第二器件;以及
将接触点与所述第一多个互连件中的一些互连件和所述第二多个互连件中的一些互连件的其中之一并置,所述接触点能够操作用于连接到外部源,
其中,所述多个第一器件和所述多个第二器件的其中之一包括比所述多个第一器件和所述多个第二器件的其中之另一具有更高的电压范围的器件。
18.如权利要求17所述的方法,其中,所述第一器件层形成在牺牲衬底上,所述方法还包括:
将所述牺牲衬底耦合到载体衬底;以及
去除所述牺牲衬底。(FLW1)
19.如权利要求18所述的方法,其中,所述多个第二器件包括以比所述多个第一器件的间距更细的间距设置的器件,并且将所述牺牲衬底耦合到所述载体衬底包括将所述多个第二互连件设置在所述器件层与所述载体衬底之间。(FLW1)
20.如权利要求19所述的方法,其中,所述接触点与所述多个第二互连件中的一些第二互连件并置。(FLW1)
21.如权利要求17-18中的任一项所述的方法,其中,形成多个第二互连件包括:形成包括所述多个第二互连件和多个存储器器件的互连叠置体。
22.如权利要求17-18中的任一项所述的方法,其中,将第二器件层与所述第一多个第一互连件并置包括在衬底上的器件层中形成所述多个第二器件,以及在将所述第二器件层与所述第一多个互连件耦合并置之后,所述方法包括使所述第二衬底变薄。(FLW2)
23.如权利要求17-18中的任一项所述的方法,其中,所述接触点耦合到所述第二多个互连件中的一些互连件。
24.一种三维集成电路,通过根据权利要求17-23中的任一项所述的方法来形成。
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