CN107026094A - 线圈结构及其制造方法 - Google Patents

线圈结构及其制造方法 Download PDF

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Publication number
CN107026094A
CN107026094A CN201710057578.4A CN201710057578A CN107026094A CN 107026094 A CN107026094 A CN 107026094A CN 201710057578 A CN201710057578 A CN 201710057578A CN 107026094 A CN107026094 A CN 107026094A
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China
Prior art keywords
coil
encapsulation materials
encapsulation
nude film
dielectric layer
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CN201710057578.4A
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CN107026094B (zh
Inventor
余振华
江宗宪
蔡豪益
郭鸿毅
曾明鸿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及一种线圈结构及其制造方法。根据本发明的一些实施例，所述方法包含：在载体上方形成线圈，将所述线圈囊封于囊封材料中，将所述囊封材料的顶部表面平面化直到暴露所述线圈为止，在所述囊封材料及所述线圈上方形成至少一个电介质层，及形成延伸到所述至少一个电介质层中的多个重布线。所述多个重布线电耦合到所述线圈。

Description

线圈结构及其制造方法
技术领域
本发明实施例涉及线圈结构及其制造方法。
背景技术
随着半导体技术的演进，半导体芯片/裸片正变得越来越小。与此同时，需要将更多功能集成到半导体裸片中。因此，半导体裸片需要将越来越大数目个I/O垫包装到较小区域中，且I/O垫的密度随时间迅速升高。因此，半导体裸片的封装变得更加困难，此对封装的合格率产生负面影响。
可将常规封装技术划分为两个类别。在第一类别中，晶片上的裸片是在其被锯割之前封装。此封装技术具有一些有利特征，例如较大生产量及较低成本。此外，需要较少底胶或模塑料。然而，此封装技术还有缺点。由于裸片的大小正变得越来越小，且相应封装仅可为扇入型封装，因此在这种封装中，每一裸片的I/O垫被限制于相应裸片的表面正上方的区。在裸片的有限区域的情况下，由于I/O垫的间距的限制，I/O垫的数目受限制。如果减小垫的间距，那么焊区可彼此桥接，此会导致电路故障。另外，在固定球大小的要求下，焊球必须具有特定大小，此又限制可包装于裸片的表面上的焊球的数目。
在另一封装类别中，裸片是在其被封装之前从晶片锯割。此封装技术的有利特征是形成扇出封装的可能性，此意味着可将裸片上的I/O垫重布到比裸片大的区域，且因此可增加包装于裸片的表面上的I/O垫的数目。此封装技术的另一有利特征是仅封装“已知良好裸片”，且摒弃缺陷裸片，且因此不将成本及努力浪费在缺陷裸片上。
发明内容
根据本公开的一些实施例，一种方法包含：在载体上方形成线圈，将所述线圈囊封于囊封材料中，将所述囊封材料的顶部表面平面化直到暴露所述线圈为止，在所述囊封材料及所述线圈上方形成至少一个电介质层，及形成延伸到所述至少一个电介质层中的多个重布线。所述多个重布线电耦合到所述线圈。
根据本公开的一些实施例，一种方法包含：在载体上方形成线圈，其中在所述线圈的俯视图中，所述线圈包括环绕内环的外环；将所述线圈囊封于囊封材料中；研磨所述囊封材料，其中所述线圈的所述外环及所述内环的顶部表面由于所述研磨而暴露；在所述囊封材料及所述线圈上方形成电介质层；及将所述电介质层图案化以形成第一开口及第二开口。所述线圈的第一端部及第二端部分别通过所述第一开口及所述第二开口而暴露。所述方法进一步包含形成用以电耦合到所述线圈的电连接。
根据本公开的一些实施例，一种结构包含：线圈，其具有环绕内环的外环；及囊封材料，其将所述线圈囊封于其中。所述囊封材料具有与所述外环的顶部表面及所述内环的顶部表面共面的顶部表面。所述结构进一步包含：电介质层，其位于所述囊封材料及所述线圈上方且接触所述囊封材料及所述线圈；第一开口及第二开口，其位于所述电介质层中；及第一重布线及第二重布线，其分别延伸到所述第一开口及所述第二开口中以接触所述线圈的相对端部。
附图说明
当与附图一起阅读时，依据以下详细描述最佳地理解本公开实施例的方面。注意，根据行业中的标准实践，各种构件并不按比例绘制。事实上，为讨论的清晰起见，可任意地增大或减小各种构件的尺寸。
图1到13图解说明根据一些实施例的封装的形成中的中间阶段的横截面图。
图14图解说明根据一些实施例的包含线圈、装置裸片及无源装置的封装的俯视图。
图15图解说明根据一些实施例的包含线圈且不包含装置裸片的封装的横截面图。
图16图解说明根据一些实施例的包含线圈且不包含装置裸片的封装的俯视图。
图17图解说明根据一些实施例的包含线圈、装置裸片及嵌入式无源装置的封装的横截面图。
图18图解说明根据一些实施例的用于形成封装的工艺流程。
图19图解说明根据一些实施例的线圈的一部分。
图20图解说明根据一些实施例的双线线圈。
具体实施方式
为实施本发明实施例的不同构件，以下公开提供许多不同实施例或实例。下文描述组件及布置的特定实例以简化本公开实施例。当然，这些组件及布置仅是实例且并不打算是限制性的。举例来说，在以下描述中，第一构件形成于第二构件上方或所述第二构件上可包含其中第一构件与第二构件直接接触而形成的实施例，且还可包含其中额外构件可形成于第一构件与第二构件之间使得第一构件与第二构件可不直接接触的实施例。另外，本公开可在各种实例中重复参考编号及/或字母。此重复是出于简洁及清晰目的且本身并不指示所论述的各种实施例及/或配置之间的关系。
此外，为便于描述起见，本文中可使用空间相对术语(例如“下伏”、“下方”、“下部”、“上覆”、“上部”等)来描述一个元件或构件与另一(些)元件或构件的关系，如图中所图解说明。除图中所描绘的定向外，空间相对术语还打算涵盖在使用或操作中的装置的不同定向。设备还可以其它方式定向(旋转90度或处于其它定向)且可相应地以类似方式解释本文中所使用的空间相对描述符。
根据各种示范性实施例提供一种封装及形成所述封装的方法，所述封装包含穿透相应封装的囊封材料的线圈。图解说明形成封装的中间阶段。论述一些实施例的一些变化形式。贯穿各种视图及说明性实施例，相似参考编号用于指定相似元件。
图1到13图解说明根据本公开的一些实施例的一些封装的形成中的中间阶段的横截面图及俯视图。图18中所展示的工艺流程200中还示意性地图解说明图1到13中所展示的步骤。
图1图解说明载体20及形成于载体20上方的离型层(release layer)22。载体20可为玻璃载体、陶瓷载体等。载体20可具有圆形俯视形状，且可具有硅晶片的大小。举例来说，载体20可具有8英寸直径、12英寸直径等。离型层22可由基于聚合物的材料(例如光到热转换(light to heat conversion，LTHC)材料)形成，离型层22可与载体20一起从将在后续步骤中形成的上覆结构移除。根据本公开的一些实施例，离型层22是由基于环氧树脂的热离型材料形成。根据本公开的一些实施例，离型层22是由紫外线(ultra-violet，UV)胶形成。可将离型层22施配为液体并将其固化。根据本公开的替代实施例，离型层22是层压膜且经层压到载体20上。离型层22的顶部表面经拉平且具有高度平整度。
根据本公开的一些实施例，电介质层24形成于离型层22上方。相应步骤经展示为图18中所展示的工艺流程中的步骤202。在最终产品中，电介质层24可用作钝化层以隔离上覆金属构件以使其免受湿气及其它有害物质的负面效应。电介质层24可由聚合物形成，所述聚合物还可为感光材料，例如聚苯并唑(PBO)、聚酰亚胺、苯环丁烯(BCB)等。根据本公开的替代实施例，电介质层24是由无机材料形成，所述无机材料可为例如氮化硅的氮化物、例如氧化硅的氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)等。根据本公开的另外替代实施例，无电介质层24形成。因此，电介质层24是以虚线展示以指示其可或可不形成。
图2及3图解说明导电构件32的形成，导电构件32在后文中称为贯穿导体(或贯穿通路)，这是因为其穿透将在后续步骤中施涂的囊封材料52(图6)。参考图2，晶种层26(举例来说)通过物理气相沉积(physical vapor deposition，PVD)或金属箔层压而形成于电介质层24上方。晶种层26可由铜、铝、钛或以上各项的多个层形成。根据本公开的一些实施例，晶种层26包含钛层(未展示)及位于钛层上方的铜层(未展示)。根据替代实施例，晶种层26包含单个铜层。
将光致抗蚀剂28施涂于晶种层26上方且然后将其图案化。相应步骤还经展示为图18中所展示的工艺流程中的步骤202。因此，开口30形成于光致抗蚀剂28中，晶种层26的一些部分通过开口30暴露。
如图2中所展示，贯穿导体32通过镀覆形成于开口30中，镀覆可为电镀与无电式电镀的适合组合。相应步骤经展示为图18中所展示的工艺流程中的步骤204。将贯穿导体32镀覆于晶种层26的暴露部分上。贯穿导体32可包含铜、铝、钨、镍或以上各项的合金。取决于贯穿导体32的既定功能，贯穿导体32的俯视图案轮廓/形状包含但不限于螺旋形、环形、矩形、方形、圆形等。尽管贯穿导体32贯穿描述在横截面图中经图解说明为离散构件，但其可为整体导体的部分。根据各种实施例，贯穿导体32的高度是由随后安置的装置裸片38(图6)的厚度确定，其中贯穿导体32的最终高度大于或等于装置裸片38的厚度。即成示范性贯穿导体32经配置以充当电感器，且贯穿导体32的高度可根据借此形成的电感器的所要电感而确定。根据一些实施例，在中间高度处测量的中间宽度W2大于顶部宽度W1及底部宽度W3。根据替代实施例，顶部宽度W1大于中间宽度W2，且中间宽度W2大于底部宽度W3。
在镀覆贯穿导体32之后，移除光致抗蚀剂28，且所得结构在图3中予以展示。晶种层26(图2)的先前由光致抗蚀剂28覆盖的部分被暴露。然后执行蚀刻步骤以移除晶种层26的暴露部分，其中所述蚀刻可为非各向同性蚀刻或各向同性蚀刻。另一方面，晶种层26的与贯穿导体32重叠的部分保持未被蚀刻。贯穿描述，晶种层26的剩余下伏部分被视为贯穿导体32的底部部分。当晶种层26是由类似于相应上覆贯穿导体32的材料或与相应上覆贯穿导体32的材料相同的材料形成时，晶种层26可与贯穿导体32合并而无可辨别界面存在于晶种层26与贯穿导体32之间。因此，在后续图式中未展示晶种层26。根据本公开的替代实施例，在晶种层26与贯穿导体32的上覆经镀覆部分之间存在可辨别界面。
贯穿导体32的俯视形状是与其既定功能相关且由其既定功能确定。根据其中贯穿导体32用于形成电感器的一些示范性实施例，所图解说明的贯穿导体32可为线圈33的一部分。根据一些实施例，贯穿导体32形成多个同心环(未展示)，其中外环环绕内环。所述环具有断裂以允许外环通过随后形成的重布线而连接到内环。根据一些实施例，如图14及16中所展示，贯穿导体32是集成式螺旋成形线圈33的部分，集成式螺旋成形线圈33还包含环绕内环的外环。线圈33具有在线圈33的相对端部处的端口34。
图4图解说明根据本公开的一些实施例的载体20上方的装置裸片38的安置。相应步骤经展示为图18中所展示的工艺流程中的步骤206。装置裸片38可通过是粘合剂膜的裸片附接膜(die-attach film，DAF)40而粘合到电介质层24。根据本公开的一些实施例，装置裸片38是AC-DC转换器裸片，所述AC-DC转换器裸片经布置以执行从线圈33接收AC电流并将AC电流转换成DC电流的功能。DC电流用于给电池(未展示)充电，或驱动包含线圈33的封装位于其中的相应产品的电路。装置裸片38还可为通信裸片，所述通信裸片可为蓝牙低能量(bluetooth low-energy，BLE)裸片。BLE裸片38可具有(举例来说)通过蓝牙技术与发射器(未展示)通信的功能。举例来说，当发射器与线圈33之间的距离足够小时，及/或当电池中所存储电力低于预定阈值电平时，发射器与BLE裸片38可协商能量发射。然后发射器可开始发射能量，所述能量可呈处于高频率下(举例来说，处于约6.78MHz下)的磁场形式。线圈33接收所述能量，并将相应电流馈送到AC-DC转换器裸片38。根据本公开的一些实施例，装置裸片38表示AC-DC转换器裸片及BLE裸片两者。
尽管图解说明一个装置裸片38，但可将更多装置裸片安置于电介质层24上方。根据本公开的一些实施例，封装的形成是在晶片级处。因此，可将与装置裸片38相同的多个装置裸片安置于载体20上，且将所述多个装置裸片分配为具有多个行及列的阵列。同样地，当形成线圈33时，同时形成与线圈33相同的多个线圈。
装置裸片38可包含半导体衬底42，半导体衬底42可为硅衬底。集成电路装置44形成于半导体衬底42上。集成电路装置44可包含有源装置(例如晶体管及二极管)及/或无源装置(例如电阻器、电容器、电感器等)。装置裸片38可包含电耦合到集成电路装置44的金属柱46。金属柱46可嵌入可由(举例来说)PBO、聚酰亚胺或BCB形成的电介质层48中。还图解说明钝化层50，其中金属柱46可延伸到钝化层50中。钝化层50可包含氮化硅、氧化硅或多层氮化硅及氧化硅。
接下来，参考图5，将囊封材料52囊封/成型于装置裸片38上。相应步骤经展示为图18中所展示的工艺流程中的步骤208。囊封材料52填充相邻贯穿导体32之间的间隙及贯穿导体32与装置裸片38之间的间隙。囊封材料52可包含基于聚合物的材料，且可包含模塑料、模塑底胶、环氧树脂及/或树脂。根据本公开的一些实施例，囊封材料52包含基于环氧树脂的材料及所述基于环氧树脂的材料中的填料粒子。所述填料粒子可包含(举例来说)Al2O3粒子，Al2O3粒子可为球形粒子。囊封材料52的顶部表面高于金属柱46的顶部端部。
在后续步骤中，如图6中所展示，执行平面化过程(例如化学机械抛光(chemicalmechanical polish，CMP)过程或研磨过程)以减小囊封材料52的顶部表面，直到暴露贯穿导体32及金属柱46为止。相应步骤还经展示为图18中所展示的工艺流程中的步骤210。由于平面化，贯穿导体32的顶部端部与金属柱46的顶部表面基本上水平(共面)，且与囊封材料52的顶部表面基本上共面。
图7到11图解说明正面RDL及相应电介质层的形成。参考图7，形成电介质层54。相应步骤经展示为图18中所展示的工艺流程中的步骤212。根据本公开的一些实施例，电介质层54是由聚合物(例如PBO、聚酰亚胺等)形成。根据本公开的替代实施例，电介质层54是由无机材料(例如氮化硅、氧化硅等)形成。开口55形成于电介质层54中(举例来说，通过曝光及显影)以暴露贯穿导体32及金属柱46。开口55可通过光刻过程形成。
接下来，参考图8，形成重布线(RDL)58以连接到金属柱46及贯穿导体32。相应步骤经展示为图18中所展示的工艺流程中的步骤214。RDL 58还可将金属柱46与贯穿导体32互连。RDL 58包含在电介质层54上方的金属迹线(金属线)及延伸到电介质层54中的通路。RDL58中的所述通路连接到贯穿导体32及金属柱46。根据本公开的一些实施例，RDL 58的形成包含：形成毯覆铜晶种层，在所述毯覆铜晶种层上方形成掩模层并将所述掩模层图案化，执行镀覆以形成RDL 58，移除所述掩模层，及蚀刻毯覆铜晶种层的未被RDL 58覆盖的部分。RDL 58可由金属或金属合金(包含铝、铜、钨及/或以上各项的合金)形成。
参考图9，根据一些实施例，电介质层60形成于图8中所展示的结构上方，后续接着在电介质层60中形成开口62。因此暴露RDL 58的一些部分。相应步骤经展示为图18中所展示的工艺流程中的步骤216。电介质层60可使用选自用于形成电介质层54的相同候选材料的材料而形成。
接下来，如图10中所展示，RDL 64形成于电介质层60中。相应步骤还经展示为图18中所展示的工艺流程中的步骤216。根据本公开的一些实施例，RDL 64的形成包含：形成毯覆铜晶种层，在所述毯覆铜晶种层上方形成掩模层并将所述掩模层图案化，执行镀覆以形成RDL 64，移除所述掩模层，及蚀刻毯覆铜晶种层的未被RDL 64覆盖的部分。RDL 64还可由金属或金属合金(包含铝、铜、钨及/或以上各项的合金)形成。应了解，尽管在所图解说明的示范性实施例中形成两层RDL(58及64)，但RDL可具有任何数目层，例如一层或多于两层。
图11及12图解说明根据一些示范性实施例的电介质层66及电连接件68的形成。相应步骤经展示为图18中所展示的工艺流程中的步骤218。参考图11，(举例来说)使用PBO、聚酰亚胺或BCB来形成电介质层66。开口59形成于电介质层66中以暴露是RDL 64的部分的下伏金属垫。根据某一实施例，形成凸块下金属(under-bump metallurgy，UBM，未展示)以延伸到电介质层66中的开口59中。
然后形成电连接件68，如图12中所展示。电连接件68的形成可包含：将焊球安置于UBM的暴露部分上，及然后对所述焊球进行回焊。根据本公开的替代实施例，电连接件68的形成包含：执行镀覆步骤以在RDL 64中的暴露金属垫上方形成焊区，及然后对所述焊区进行回焊。电连接件68还可包含还可通过镀覆而形成的金属柱或金属柱与焊帽。贯穿描述，包含电介质层24及上覆结构的结构以组合形式而称为封装100，封装100是包含多个装置裸片38的复合晶片。
接下来，(举例来说)通过将UV光或激光束投射于离型层22上，使得离型层22在UV光或激光束的热量作用下分解而将封装100从载体20剥离。因此封装100从载体20剥离。相应步骤经展示为图18中所展示的工艺流程中的步骤220。根据本公开的一些实施例，在所得封装100中，电介质层24仍作为封装100的底部部分，且保护贯穿导体32。电介质层24可为其中无贯穿开口的毯覆层。根据替代实施例，未形成电介质层24，且在剥离之后囊封材料52的底部表面及贯穿导体32的底部表面被暴露。可(或可不)执行背面研磨以移除DAF 40，如果使用背面研磨，那么使得贯穿导体32的底部表面与装置裸片38的底部表面及囊封材料52的底部表面共面。装置裸片38的底部表面还可为半导体衬底42的底部表面。
然后将封装100单切(锯割)成彼此相同的多个封装100’。相应步骤经展示为图18中所展示的工艺流程中的步骤222。图13图解说明示范性封装100’。图13还图解说明封装100’到封装组件110的接合(举例来说，通过电连接件68)。封装组件110可为印刷电路板(printed circuit board，PCB)、中介层、封装衬底、装置封装等。根据替代实施例，封装100’电连接到挠曲PCB(未展示，类似于图17中的挠曲PCB 72)，所述挠曲PCB可与线圈33重叠，或可侧向连接。
图14图解说明图13中所展示的封装100’的俯视图，其中图13中所展示的横截面图是从含有图14中的线13-13的平面获得。根据本公开的一些实施例，线圈33的端口34连接到装置裸片38(标示为38A)，装置裸片38可为AC-DC转换器裸片。根据一些实施例，标示为38B的BLE裸片也安置于封装100’中。
无源装置56也包含于封装100’中。无源装置56可为集成式无源装置(integratedpassive device，IPD)，其形成于相应芯片中的半导体衬底上。贯穿描述，IPD可为单装置芯片，所述单装置芯片可包含单个无源装置(例如电感器、电容器、电阻器等)，其中在相应芯片中无其它无源装置及有源装置。此外，根据一些实施例，在IPD中无有源装置，例如晶体管及二极管。
根据本公开的一些实施例，无源装置56包含接合到RDL 64或焊区68上的表面安装装置(surface mount device，SMD，标示为56A)，如图17中所展示。根据替代实施例，无源装置56包含嵌入式无源装置56B，嵌入式无源装置56B可在如图5中所展示的囊封步骤之前安置于载体20上。相应无源装置56B还在图17中予以展示，其中记号38/56B指示相应组件可为装置裸片38、无源装置(例如IPD)56B，或可包含彼此分离的装置裸片及无源装置两者。类似地，囊封于囊封材料52中的无源装置56B可使其相应表面导电构件(类似于46)在如图6中所展示的平面化步骤中暴露。因此，无源装置56B通过RDL 58及/或64而电耦合到其它装置。根据替代实施例，无无源装置囊封于囊封材料52中。
返回参考图14，根据本公开的一些实施例，囊封材料52的由线圈33环绕的部分在其中不具有例如贯穿通路的任何导电材料。因此，囊封材料52的由线圈33环绕的部分还可在其中不具有任何无源装置或有源装置。
图14还图解说明接垫70，根据一些示范性实施例，接垫70用于将封装100’中的组件连接到挠曲PCB 72(图14中未展示，参考图17)。接垫70通过RDL 58及64(图13)而电耦合到装置裸片38A、装置裸片38B及/或无源装置56。
图15图解说明根据本公开的一些实施例的封装的横截面图。这些实施例类似于图13及14中的实施例，惟无装置裸片(具有有源装置)及无源装置定位于封装100’中除外。换句话说，根据本公开的一些实施例，囊封材料52内部的所有导电构件均是线圈33的部分。因此，封装100’包含线圈33及相应电连接结构，但不包含额外装置，且封装100’是离散线圈。
图16图解说明根据本公开的一些实施例的封装100’的俯视图，其中图15中所展示的横截面图是从含有图16中的线15-15的平面获得。如图16中所展示，线圈33延伸到封装100’的近端所有边缘，惟留出某一过程余裕以确保充分但不过量的囊封材料52在线圈33的外侧上除外。因此，封装100’的占用面积大小(俯视区)被最小化。囊封材料52的在线圈33外侧上的部分防止线圈33暴露于外界空气。如图16中所展示，线圈33的内部或外部及囊封材料52中不存在有源装置及无源装置。
图17图解说明根据一些实施例的封装100’的横截面图。如图17中所展示，无源装置56A位于电介质层54、60及66上方，且可通过焊区68而接合到金属垫64。装置裸片38及/或无源装置56B嵌入于囊封材料52中。挠曲PCB 72连接到金属垫70(举例来说，通过焊区68)。此外，无源装置56A可直接与无源装置56B重叠以更好地使用封装区域且减小所得封装的占用面积。
根据一些实施例，铁氧体材料74通过(举例来说)粘合剂膜76而附接到电介质层66。铁氧体材料74可包含锰锌、镍锌等。铁氧体材料74在高频率下具有相对低损耗，且用于增加电感器33的电感。铁氧体材料74与线圈33重叠，且铁氧体材料74的边缘可与线圈33的边缘基本上同终点。
图19图解说明图14及16中的封装100’的部分82的经放大视图，其中两个贯穿导体32经图解说明为实例。为减小应力，贯穿导体32可具有经修圆隅角。举例来说，贯穿导体的半径R1可在介于约W1/2与2W1/3之间的范围中。
根据一些实施例，为提高效率，线圈33的外环可具有大于或等于内环的宽度的宽度。举例来说，参考图14及16，可为最外侧环的宽度的宽度W1A可等于或大于最内侧环的宽度W1B。W1B/W1A的比率可为在介于约1/2与约2/3之间的范围中。此外，从外环到内环，贯穿导体32的宽度可逐渐减小或每数环周期性地减小。
图20图解说明根据一些实施例的包含双线线圈33的封装100’。为较清晰视图起见，图20中未图解说明将线圈33的端部连接到装置裸片38A的RDL 58及64(图14)。图20中的线圈33可与图14或图16中的对应线圈基本上相同，惟线圈33具有两个平行贯穿导体32A及32B盘绕而非具有单个贯穿导体32盘绕除外。贯穿导体32A与32B彼此平行，且组合起来像单个导体样用于形成线圈。为辨别贯穿导体32A与32B，使得可清晰地看见其布局，使用不同图案来展示贯穿导体32A及32B。
如图20中所展示，贯穿导体32A及32B中的每一者本身形成线圈。贯穿导体32A及32B的端部是通过连接件74A及74B互连。连接件74A及74B中的每一者可为当贯穿导体32A及32B形成时而同时形成的贯穿通路，或可为RDL 58及64的一部分。连接件74A及74B还可包含贯穿导体部分及RDL部分两者。根据一些实施例，贯穿导体32A及32B仅在其端部处而不在中间连接，如图20中所展示。根据替代实施例，类似于连接件74A及74B的额外连接件可周期性地形成以使贯穿导体32A的中间部分与贯穿导体32B的相应中间部分互连。举例来说，贯穿导体32A及32B的每一笔直部分可包含一或多个互连件。如图19及20中所展示的线圈33可与如所图解说明的所有实施例组合。
由于贯穿导体32A及32B的互连，因此贯穿导体32A及32B以组合形式形成线圈。当图20中的线圈33以高频率(举例来说，数兆赫或更高)操作时，其具有可与如图14及16中所展示的块体线圈33相当且有时优于块体线圈33的性能。此可由集肤效应所致。此外，在贯穿导体32A及32B与块体线圈相比更窄(由于其相当于移除如图14及16中所展示的贯穿导体32的中间部分)的情况下，镀覆贯穿导体32A及32B的图案负载效应减小。
本公开的实施例具有一些有利特征。线圈33形成于囊封材料中，且因此线圈33的高度可具有较大值。因此线圈33的电感是高的。线圈33还可使用与用于封装装置裸片相同的封装过程来形成，且可将其与装置裸片及无源装置集成于同一封装内，从而实现封装的占用面积及制造成本的减小。
根据本公开的一些实施例，一种方法包含：在载体上方形成线圈，将所述线圈囊封于囊封材料中，将所述囊封材料的顶部表面平面化直到暴露所述线圈为止，在所述囊封材料及所述线圈上方形成至少一个电介质层，及形成延伸到所述至少一个电介质层中的多个重布线。所述多个重布线电耦合到所述线圈。
根据本公开的一些实施例，一种方法包含：在载体上方形成线圈，其中在所述线圈的俯视图中，所述线圈包括环绕内环的外环；将所述线圈囊封于囊封材料中；研磨所述囊封材料，其中所述线圈的所述外环及所述内环的顶部表面由于所述研磨而暴露；在所述囊封材料及所述线圈上方形成电介质层；及将所述电介质层图案化以形成第一开口及第二开口。所述线圈的第一端部及第二端部分别通过所述第一开口及所述第二开口而暴露。所述方法进一步包含形成用以电耦合到所述线圈的电连接。
根据本公开的一些实施例，一种结构包含：线圈，其具有环绕内环的外环；及囊封材料，其将所述线圈囊封于其中。所述囊封材料具有与所述外环的顶部表面及所述内环的顶部表面共面的顶部表面。所述结构进一步包含：电介质层，其位于所述囊封材料及所述线圈上方且接触所述囊封材料及所述线圈；第一开口及第二开口，其位于所述电介质层中；及第一重布线及第二重布线，其分别延伸到所述第一开口及所述第二开口中以接触所述线圈的相对端部。
前述内容概述数个实施例的特征，使得所属领域的技术人员可较好地理解本公开实施例的方面。所属领域的技术人员应了解，其可容易地将本公开实施例用作用于设计或修改其它过程及结构以实现本文中所引入实施例的相同目的及/或实现相同优势的基础。所属领域的技术人员还应意识到，这些等效构造并不脱离本公开实施例的精神及范围，且应意识到其可在不脱离本公开实施例的精神及范围的情况下在本文中做出各种改变、替代及更改。
符号说明
13-13 线
13-13 线
15-15 线
20 载体
22 离型层
24 电介质层
26 晶种层
28 光致抗蚀剂
30 开口
32 导电构件/贯穿导体
32A 贯穿导体
32B 贯穿导体
33 线圈/集成式螺旋成形线圈/电感器/双线线圈/块体线圈
34 埠
38 装置裸片/蓝牙低能量裸片/AC-DC转换器裸片
38A 装置裸片/AC-DC转换器裸片
38B 装置裸片/蓝牙低能量裸片
40 裸片附接膜
42 半导体衬底
44 集成电路装置
46 金属柱
48 电介质层
50 钝化层
52 囊封材料
54 电介质层
55 开口
56 无源装置
56A 表面安装装置/无源装置
56B 嵌入式无源装置/无源装置
58 重新分布线
59 开口
60 电介质层
62 开口
64 重新分布线/金属垫
66 电介质层
68 电连接件/焊区
70 接垫/金属垫
72 挠曲印刷电路板
74 铁氧体材料
74A 连接件
74B 连接件
76 粘合剂膜
82 封装100’的部分
100 封装
100’ 封装
110 封装组件
R1 半径

Claims (10)

1.一种线圈结构制造方法，其包括：
在载体上方形成线圈；
将所述线圈囊封于囊封材料中；
将所述囊封材料的顶部表面平面化直到暴露所述线圈为止；
在所述囊封材料及所述线圈上方形成至少一个电介质层；及
形成延伸到所述至少一个电介质层中的多个重布线，其中所述多个重布线电耦合到所述线圈。
2.根据权利要求1所述的线圈结构制造方法，其中形成所述线圈进一步包括将所述线圈的底部表面形成为与所述囊封材料的底部表面基本上共面，且不将除所述线圈之外的额外导电构件囊封于所述囊封材料中。
3.根据权利要求1所述的线圈结构制造方法，其进一步包括将AC-DC转换器裸片安置在所述载体上方，其中将所述AC-DC转换器裸片囊封于所述囊封材料中，且其中所述方法进一步包括：通过所述多个重布线的部分将所述线圈电耦合到所述AC-DC转换器裸片；将集成式被动装置接合于所述至少一个介电层上方，其中将所述集成式被动装置电耦合到所述多个重布线；或者，将额外集成式被动装置安置于所述载体上方，其中将所述额外集成式被动装置囊封于所述囊封材料中。
4.根据权利要求1所述的线圈结构制造方法，其进一步包括：将铁氧体材料附接到所述至少一个电介质层，其中所述铁氧体材料与所述线圈重叠；或者，执行单粒化以将所述线圈分离到封装中，其中在所述封装中无装置裸片及被动装置。
5.一种线圈结构制造方法，其包括：
在载体上方形成线圈，其中在所述线圈的俯视图中，所述线圈包括环绕内环的外环；
将所述线圈囊封于囊封材料中；
研磨所述囊封材料，其中所述线圈的所述外环及所述内环的顶部表面由于所述研磨而暴露；
在所述囊封材料及所述线圈上方形成电介质层；
将所述电介质层图案化以形成第一开口及第二开口，其中所述线圈的第一端部及第二端部分别通过所述第一开口及所述第二开口而暴露；及
形成用以电耦合到所述线圈的电连接。
6.根据权利要求5所述的线圈结构制造方法，其进一步包括：将所述载体与所述线圈及所述囊封材料拆分开；执行单粒化以将所述线圏分离到封装中，其中在所述封装中无装置裸片及被动装置；所述线圈的所述外环及所述内环的底部表面与介电材料接触；附接与所述线圈重叠的铁氧体材料；将集成式被动装置接合于所述介电层上方；或者将额外集成式被动装置安置于所述载体上方，其中所述额外集成式被动装置由所述囊封材料囊封。
7.根据权利要求5所述的线圈结构制造方法，其中所述形成所述线圈包括：
在所述载体上方沉积晶种层；
在所述晶种层上方施涂光致抗蚀剂；
将所述光致抗蚀剂图案化以在所述光致抗蚀剂中形成至少一个开口；
在所述至少一个开口中镀覆金属材料；及
蚀刻所述晶种层的未被所述线圈覆盖的部分。
8.一种线圈结构，其包括：
线圈，其包括环绕内环的外环，其中所述线圈的隅角是经修圆的；
囊封材料，其将所述线圈囊封于其中，其中所述囊封材料具有与所述外环的顶部表面及所述内环的顶部表面共面的顶部表面；
电介质层，其位于所述囊封材料上方且接触所述囊封材料；
第一开口及第二开口，其位于所述电介质层中；及
第一重布线及第二重布线，其分别延伸到所述第一开口及所述第二开口中以接触所述线圈的相对端部。
9.根据权利要求8所述的线圈结构，其中所述囊封材料环绕由所述线圈环绕的区的整体；或者所述线圈是包含两个平行导体的双线线圈，且所述线圈的相对端部是互连的。
10.根据权利要求8所述的线圈结构，其进一步包括囊封于所述囊封材料中的装置裸片，其中所述装置裸片的导电构件具有与所述囊封材料的顶部表面共面的顶部表面，其中所述装置裸片是集成式被动装置裸片，且所述集成式被动装置裸片的导电构件具有与所述囊封材料的顶部表面共面的顶部表面。
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