TWI692817B - Info線圈結構及其製造方法 - Google Patents

Info線圈結構及其製造方法 Download PDF

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TWI692817B
TWI692817B TW106101449A TW106101449A TWI692817B TW I692817 B TWI692817 B TW I692817B TW 106101449 A TW106101449 A TW 106101449A TW 106101449 A TW106101449 A TW 106101449A TW I692817 B TWI692817 B TW I692817B
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Taiwan
Prior art keywords
coil
encapsulating material
dielectric layer
die
opening
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TW106101449A
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TW201737364A (zh
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余振華
江宗憲
蔡豪益
郭鴻毅
曾明鴻
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台灣積體電路製造股份有限公司
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Abstract

一種方法包含：在一載體上方形成一線圈，將該線圈囊封於一囊封材料中，將該囊封材料之一頂部表面平坦化直至暴露該線圈為止，在囊封材料及該線圈上方形成至少一個介電層，及形成延伸至該至少一個介電層中之複數個重新分佈線。該複數個重新分佈線電耦合至該線圈。

Description

INFO線圈結構及其製造方法
本揭露實施例係關於INFO線圈結構及其製造方法。
隨著半導體技術之演進，半導體晶片/晶粒正變得愈來愈小。與此同時，需要將更多功能整合至半導體晶粒中。因此，半導體晶粒需要將愈來愈大數目個I/O墊包裝至較小區域中，且I/O墊之密度隨時間迅速上升。因此，半導體晶粒之封裝變得愈加困難，此對封裝之良率產生負面影響。 可將習用封裝技術劃分為兩個類別。在第一類別中，一晶圓上之晶粒係在其被鋸割之前封裝。此封裝技術具有某些有利特徵，諸如一較大生產量及一較低成本。此外，需要較少底膠或模塑料。然而，此封裝技術亦有缺點。由於晶粒之大小正變得愈來愈小，且各別封裝僅可係扇入類型封裝，因此在這種封裝中，每一晶粒之I/O墊被限制於各別晶粒之表面正上方之區。在晶粒之有限區域之情況下，由於I/O墊之間距之限制，I/O墊之數目受限制。若減小墊之間距，則銲區可彼此橋接，此會導致電路故障。另外，在固定球大小之要求下，銲球必須具有一特定大小，此又限制可包裝於一晶粒之表面上之銲球之數目。 在另一封裝類別中，晶粒係在其被封裝之前自晶圓鋸割。此封裝技術之一有利特徵係形成扇出封裝之可能性，此意味著可將一晶粒上之I/O墊重新分佈至比晶粒大之一區域，且因此可增加包裝於晶粒之表面上之I/O墊之數目。此封裝技術之另一有利特徵係僅封裝「已知良好晶粒」，且摒棄缺陷晶粒，且因此不將成本及努力浪費在缺陷晶粒上。
根據本揭露之某些實施例，一種方法包含：在一載體上方形成一線圈，將該線圈囊封於一囊封材料中，將該囊封材料之一頂部表面平坦化直至暴露該線圈為止，在該囊封材料及該線圈上方形成至少一個介電層，及形成延伸至該至少一個介電層中之複數個重新分佈線。該複數個重新分佈線電耦合至該線圈。 根據本揭露之某些實施例，一種方法包含：在一載體上方形成一線圈，其中在該線圈之一俯視圖中，該線圈包括環繞內環之外環；將該線圈囊封於一囊封材料中；研磨該囊封材料，其中該線圈之該等外環及該等內環之頂部表面由於該研磨而暴露；在該囊封材料及該線圈上方形成一介電層；及將該介電層圖案化以形成一第一開口及一第二開口。該線圈之一第一端部及一第二端部分別透過該第一開口及該第二開口而暴露。該方法進一步包含形成用以電耦合至該線圈之電連接。 根據本揭露之某些實施例，一結構包含：一線圈，其具有環繞內環之外環；及一囊封材料，其將該線圈囊封於其中。該囊封材料具有與該等外環之頂部表面及該等內環之頂部表面共面之一頂部表面。該結構進一步包含：一介電層，其在該囊封材料及該線圈上方且接觸該囊封材料及該線圈；一第一開口及一第二開口，其在該介電層中；及一第一重新分佈線及一第二重新分佈線，其分別延伸至該第一開口及該第二開口中以接觸該線圈之相對端部。
為實施本揭露之不同構件，以下揭露提供諸多不同實施例或實例。下文闡述組件及配置之特定實例以簡化本揭露。當然，此等組件及配置僅係實例且並不意欲係限制性的。舉例而言，在以下說明中，一第一構件形成於一第二構件上方或該第二構件上可包含其中第一構件與第二構件直接接觸而形成之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸之實施例。另外，本揭露可在各種實例中重複元件符號及/或字母。此重複係出於簡潔及清晰目的且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於說明起見，本文中可使用空間相對術語(諸如「下伏」、「下方」、「下部」、「上覆」、「上部」及諸如此類)來闡述一個元件或構件與另一(些)元件或構件之關係，如圖中所圖解說明。除圖中所繪示之定向外，空間相對術語亦意欲涵蓋在使用或操作中之裝置之不同定向。設備亦可以其他方式定向(旋轉90度或處於其他定向)且可相應地以類似方式解釋本文中所使用之空間相對描述符。 根據各種例示性實施例提供一封裝及形成該封裝之方法，該封裝包含穿透各別封裝之一囊封材料之一線圈。圖解說明形成封裝之中間階段。論述某些實施例之某些變化形式。貫穿各種視圖及說明性實施例，相似元件符號用於指定相似元件。 圖1至圖13圖解說明根據本揭露之某些實施例之某些封裝之形成中之中間階段之剖面圖及俯視圖。圖18中所展示之製程流程200中亦示意性地圖解說明圖1至圖13中所展示之步驟。 圖1圖解說明載體20及形成於載體20上方之離型層(release layer) 22。載體20可係一玻璃載體、一陶瓷載體或諸如此類。載體20可具有一圓形俯視形狀，且可具有一矽晶圓之一大小。舉例而言，載體20可具有一8英吋直徑、一12英吋直徑或諸如此類。離型層22可由一基於聚合物之材料(諸如一光至熱轉換(light to heat conversion，LTHC)材料)形成，離型層22可與載體20一起自將在後續步驟中形成之上覆結構移除。根據本揭露之某些實施例，離型層22係由一基於環氧樹脂之熱離型材料形成。根據本揭露之某些實施例，離型層22係由一紫外線(ultra-violet，UV)膠形成。可將離型層22施配為一液體並將其固化。根據本揭露之替代實施例，離型層22係一層壓膜且經層壓至載體20上。離型層22之頂部表面經拉平且具有一高度平整度。 根據本揭露之某些實施例，介電層24形成於離型層22上方。各別步驟經展示為圖18中所展示之製程流程中之步驟202。在最終產品中，介電層24可用作一鈍化層以隔離上覆金屬構件以使其免受濕氣及其他有害物質之負面效應。介電層24可由一聚合物形成，該聚合物亦可係一感光材料，諸如聚苯并㗁唑(PBO)、聚醯亞胺、苯環丁烯(BCB)或諸如此類。根據本揭露之替代實施例，介電層24係由一(或多種)無機材料形成，該(等)無機材料可係諸如氮化矽之一種氮化物、諸如氧化矽之一種氧化物、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼之磷矽酸鹽玻璃(BPSG)或諸如此類。根據本揭露之另外替代實施例，無介電層24形成。因此，介電層24係以虛線展示以指示其可或可不形成。 圖2及圖3圖解說明導電構件32之形成，導電構件32在後文中稱為貫穿導體(或貫穿通路)，此乃因其穿透將在後續步驟中施塗之囊封材料52 (圖6)。參考圖2，晶種層26(舉例而言)透過物理氣相沈積(physical vapor deposition，PVD)或金屬箔層壓而形成於介電層24上方。晶種層26可由銅、鋁、鈦或以上各項之多個層形成。根據本揭露之某些實施例，晶種層26包含一鈦層(未展示)及在鈦層上方之一銅層(未展示)。根據替代實施例，晶種層26包含一單個銅層。 將光阻劑28施塗於晶種層26上方且然後將其圖案化。各別步驟亦經展示為圖18中所展示之製程流程中之步驟202。因此，開口30形成於光阻劑28中，晶種層26之某些部分透過開口30暴露。 如圖2中所展示，貫穿導體32透過鍍覆形成於開口30中，鍍覆可係電鍍與無電式電鍍之一適合組合。各別步驟經展示為圖18中所展示之製程流程中之步驟204。將貫穿導體32鍍覆於晶種層26之暴露部分上。貫穿導體32可包含銅、鋁、鎢、鎳或以上各項之合金。取決於貫穿導體32之既定功能，貫穿導體32之俯視圖案輪廓/形狀包含但不限於螺旋形、環形、矩形、方形、圓形及諸如此類。儘管貫穿導體32在貫穿說明之剖面圖中經圖解說明為離散構件，但其可係一整體導體之部分。根據各種實施例，貫穿導體32之高度係由隨後安置之裝置晶粒38 (圖6)之厚度判定，其中貫穿導體32之最終高度大於或等於裝置晶粒38之厚度。即成例示性貫穿導體32經組態以充當一電感器，且貫穿導體32之高度可根據藉此形成之電感器之所要電感而判定。根據某些實施例，在中間高度處量測之中間寬度W2大於頂部寬度W1及底部寬度W3。根據替代實施例，頂部寬度W1大於中間寬度W2，且中間寬度W2大於底部寬度W3。 在鍍覆貫穿導體32之後，移除光阻劑28，且所得結構在圖3中予以展示。先前由光阻劑28覆蓋的晶種層26(圖2)之部分被暴露。然後執行一蝕刻步驟以移除晶種層26之暴露部分，其中該蝕刻可係一非等向性蝕刻或等向性蝕刻。另一方面，與貫穿導體32重疊的晶種層26之部分保持未被蝕刻。貫穿說明，晶種層26之剩餘下伏部分被視為貫穿導體32之底部部分。當晶種層26係由類似於各別上覆貫穿導體32之材料或與各別上覆貫穿導體32之材料相同之一材料形成時，晶種層26可與貫穿導體32合併而無可辨別界面存在於晶種層26與貫穿導體32之間。因此，在後續圖式中未展示晶種層26。根據本揭露之替代實施例，在晶種層26與貫穿導體32之上覆經鍍覆部分之間存在可辨別界面。 貫穿導體32之俯視形狀係與其既定功能相關且由其既定功能判定。根據其中貫穿導體32用於形成一電感器之某些例示性實施例，所圖解說明之貫穿導體32可係線圈33之一部分。根據某些實施例，貫穿導體32形成複數個同心環(未展示)，其中外環環繞內環。該等環具有斷裂以允許外環透過隨後形成之重新分佈線而連接至內環。根據某些實施例，如圖14及圖16中所展示，貫穿導體32係一整合式螺旋成形線圈33之部分，整合式螺旋成形線圈33亦包含環繞內環之外環。線圈33具有在線圈33之相對端部處之埠34。 圖4圖解說明根據本揭露之某些實施例之載體20上方之裝置晶粒38之安置。各別步驟經展示為圖18中所展示之製程流程中之步驟206。裝置晶粒38可透過係一黏合劑膜之晶粒附接膜(die-attach film，DAF)40而黏合至介電層24。根據本揭露之某些實施例，裝置晶粒38係一AC-DC轉換器晶粒，該AC-DC轉換器晶粒經配置以執行自線圈33接收AC電流並將AC電流轉換成一DC電流之功能。DC電流用於給一電池(未展示)充電，或驅動包含線圈33之封裝位於其中之各別產品之電路。裝置晶粒38亦可係一通信晶粒，該通信晶粒可係藍芽低能量(bluetooth low-energy，BLE)晶粒。BLE晶粒38可具有(舉例而言)透過藍芽技術與一傳輸器(未展示)通信之功能。舉例而言，當傳輸器與線圈33之間的距離足夠小時，及/或當電池中所儲存電力低於一預定臨限位準時，傳輸器與BLE晶粒38可協商能量傳輸。然後傳輸器可開始傳輸能量，該能量可呈處於一高頻率下(舉例而言，處於約6.78 MHz下)之磁場形式。線圈33接收該能量，並將各別電流饋送至AC-DC轉換器晶粒38。根據本揭露之某些實施例，裝置晶粒38表示AC-DC轉換器晶粒及一BLE晶粒兩者。 儘管圖解說明一個裝置晶粒38，但可將更多裝置晶粒安置於介電層24上方。根據本揭露之某些實施例，封裝之形成係在晶圓級處。因此，可將與裝置晶粒38相同之複數個裝置晶粒安置於載體20上，且將該複數個裝置晶粒分配為具有複數個列及行之一陣列。同樣地，當形成線圈33時，同時形成與線圈33相同之複數個線圈。 裝置晶粒38可包含半導體基板42，半導體基板42可係一矽基板。積體電路裝置44形成於半導體基板42上。積體電路裝置44可包含主動裝置(諸如電晶體及二極體)及/或被動裝置(諸如電阻器、電容器、電感器或諸如此類)。裝置晶粒38可包含電耦合至積體電路裝置44之金屬柱46。金屬柱46可嵌入可由(舉例而言) PBO、聚醯亞胺或BCB形成之介電層48中。亦圖解說明鈍化層50，其中金屬柱46可延伸至鈍化層50中。鈍化層50可包含氮化矽、氧化矽或多層氮化矽及氧化矽。 接下來，參考圖5，將囊封材料52囊封/成型於裝置晶粒38上。各別步驟經展示為圖18中所展示之製程流程中之步驟208。囊封材料52填充鄰近貫穿導體32之間的間隙及貫穿導體32與裝置晶粒38之間的間隙。囊封材料52可包含一基於聚合物之材料，且可包含一模塑料、一模塑底膠、一環氧樹脂及/或一樹脂。根據本揭露之某些實施例，囊封材料52包含一基於環氧樹脂之材料及該基於環氧樹脂之材料中之填料粒子。該等填料粒子可包含(舉例而言) Al2 O3 粒子，Al2 O3 粒子可係球形粒子。囊封材料52之頂部表面高於金屬柱46之頂部端部。 在一後續步驟中，如圖6中所展示，執行一平坦化製程(諸如一化學機械拋光(chemical mechanical polish，CMP)製程或一研磨製程)以減小囊封材料52之頂部表面，直至暴露貫穿導體32及金屬柱46為止。各別步驟亦經展示為圖18中所展示之製程流程中之步驟210。由於平坦化，貫穿導體32之頂部端部與金屬柱46之頂部表面實質上水平(共面)，且與囊封材料52之頂部表面實質上共面。 圖7至圖11圖解說明正面RDL及各別介電層之形成。參考圖7，形成介電層54。各別步驟經展示為圖18中所展示之製程流程中之步驟212。根據本揭露之某些實施例，介電層54係由一聚合物(諸如PBO、聚醯亞胺或諸如此類)形成。根據本揭露之替代實施例，介電層54係由一無機材料(諸如氮化矽、氧化矽或諸如此類)形成。開口55形成於介電層54中(舉例而言，透過曝光及顯影)以暴露貫穿導體32及金屬柱46。開口55可透過一光微影製程形成。 接下來，參考圖8，形成重新分佈線(RDL) 58以連接至金屬柱46及貫穿導體32。各別步驟經展示為圖18中所展示之製程流程中之步驟214。RDL 58亦可將金屬柱46與貫穿導體32互連。RDL 58包含在介電層54上方之金屬跡線(金屬線)及延伸至介電層54中之通路。RDL 58中之該等通路連接至貫穿導體32及金屬柱46。根據本揭露之某些實施例，RDL 58之形成包含：形成一毯覆銅晶種層，在該毯覆銅晶種層上方形成一遮罩層並將該遮罩層圖案化，執行一鍍覆以形成RDL 58，移除該遮罩層，及蝕刻未被RDL 58覆蓋的毯覆銅晶種層之部分。RDL 58可由一金屬或一金屬合金(包含鋁、銅、鎢及/或以上各項之合金)形成。 參考圖9，根據某些實施例，介電層60形成於圖8中所展示之結構上方，後續接著在介電層60中形成開口62。因此暴露RDL 58之某些部分。各別步驟經展示為圖18中所展示之製程流程中之步驟216。介電層60可使用選自用於形成介電層54之相同候選材料之一材料而形成。 接下來，如圖10中所展示，RDL 64形成於介電層60中。各別步驟亦經展示為圖18中所展示之製程流程中之步驟216。根據本揭露之某些實施例，RDL 64之形成包含：形成一毯覆銅晶種層，在該毯覆銅晶種層上方形成一遮罩層並將該遮罩層圖案化，執行一鍍覆以形成RDL 64，移除該遮罩層，及蝕刻未被RDL 64覆蓋的毯覆銅晶種層之部分。RDL 64亦可由一金屬或一金屬合金(包含鋁、銅、鎢及/或以上各項之合金)形成。應瞭解，儘管在所圖解說明之例示性實施例中形成兩層RDL (58及64)，但RDL可具有任何數目層，諸如一層或兩層以上。 圖11及圖12圖解說明根據某些例示性實施例之介電層66及電連接器68之形成。各別步驟經展示為圖18中所展示之製程流程中之步驟218。參考圖11，(舉例而言)使用PBO、聚醯亞胺或BCB來形成介電層66。開口59形成於介電層66中以暴露係RDL 64之部分之下伏金屬墊。根據某一實施例，形成凸塊下金屬(under-bump metallurgies，UBM，未展示)以延伸至介電層66中之開口59中。 然後形成電連接器68，如圖12中所展示。電連接器68之形成可包含：將銲球安置於UBM之暴露部分上，及然後對該等銲球進行回銲。根據本揭露之替代實施例，電連接器68之形成包含：執行一鍍覆步驟以在RDL 64中之暴露金屬墊上方形成銲區，及然後對該等銲區進行回銲。電連接器68亦可包含亦可透過鍍覆而形成之金屬柱或金屬柱與銲帽。貫穿說明，包含介電層24及上覆結構之結構以組合形式而稱為封裝100，封裝100係包含複數個裝置晶粒38之一複合晶圓。 接下來，(舉例而言)藉由將一UV光或一雷射束投射於離型層22上，使得離型層22在UV光或雷射束之熱量作用下分解而將封裝100與載體20剝離。因此封裝100與載體20剝離。各別步驟經展示為圖18中所展示之製程流程中之步驟220。根據本揭露之某些實施例，在所得封裝100中，介電層24仍作為封裝100之一底部部分，且保護貫穿導體32。介電層24可係其中無貫穿開口之一毯覆層。根據替代實施例，未形成介電層24，且在剝離之後囊封材料52之底部表面及貫穿導體32之底部表面被暴露。可(或可不)執行一背面研磨以移除DAF 40，若使用背面研磨，則使得貫穿導體32之底部表面與裝置晶粒38之底部表面及囊封材料52之底部表面共面。裝置晶粒38之底部表面亦可係半導體基板42之底部表面。 然後將封裝100單粒化(鋸割)成彼此相同之複數個封裝100’。各別步驟經展示為圖18中所展示之製程流程中之步驟222。圖13圖解說明一例示性封裝100’。圖13亦圖解說明封裝100’至封裝組件110之接合(舉例而言，透過電連接器68)。封裝組件110可係一印刷電路板(printed circuit board，PCB)、一中介層、一封裝基板、一裝置封裝或諸如此類。根據替代實施例，封裝100’電連接至一撓曲PCB (未展示，類似於圖17中之撓曲PCB 72)，該撓曲PCB可與線圈33重疊，或可側向連接。 圖14圖解說明圖13中所展示之封裝100’之一俯視圖，其中圖13中所展示之剖面圖係自含有圖14中之線13-13之平面獲得。根據本揭露之某些實施例，線圈33之埠34連接至裝置晶粒38(標示為38A)，裝置晶粒38可係一AC-DC轉換器晶粒。根據某些實施例，標示為38B之一BLE晶粒亦安置於封裝100’中。 被動裝置56亦包含於封裝100’中。被動裝置56可係整合式被動裝置(integrated passive devices，IPD)，其形成於各別晶片中之半導體基板上。貫穿說明，一IPD可係一單裝置晶片，該單裝置晶片可包含一單個被動裝置(諸如一電感器、一電容器、一電阻器或諸如此類)，其中在各別晶片中無其他被動裝置及主動裝置。此外，根據某些實施例，在IPD中無主動裝置，諸如電晶體及二極體。 根據本揭露之某些實施例，被動裝置56包含接合至RDL 64或銲區68上之表面安裝裝置(surface mount devices，SMD，標示為56A)，如圖17中所展示。根據替代實施例，被動裝置56包含嵌入式被動裝置56B，嵌入式被動裝置56B可在如圖5中所展示之囊封步驟之前安置於載體20上。各別被動裝置56B亦在圖17中予以展示，其中記號38/56B指示各別組件可係裝置晶粒38、被動裝置(諸如一IPD) 56B，或可包含彼此分離之一裝置晶粒及一被動裝置兩者。類似地，囊封於囊封材料52中之被動裝置56B可使其各別表面導電構件(類似於46)在如圖6中所展示之平坦化步驟中暴露。因此，被動裝置56B透過RDL 58及/或64而電耦合至其他裝置。根據替代實施例，無被動裝置囊封於囊封材料52中。 返回參考圖14，根據本揭露之某些實施例，由線圈33環繞的囊封材料52之部分在其中不具有諸如貫穿通路之任何導電材料。因此，由線圈33環繞的囊封材料52之部分亦可在其中不具有任何被動裝置或主動裝置。 圖14亦圖解說明接墊70，根據某些例示性實施例，接墊70用於將封裝100’中之組件連接至一撓曲PCB 72 (圖14中未展示，參考圖17)。接墊70透過RDL 58及64 (圖13)而電耦合至裝置晶粒38A、裝置晶粒38B及/或被動裝置56。 圖15圖解說明根據本揭露之某些實施例之一封裝之一剖面圖。此等實施例類似於圖13及圖14中之實施例，惟無裝置晶粒(具有主動裝置)及被動裝置定位於封裝100’中除外。換言之，根據本揭露之某些實施例，囊封材料52內部之所有導電構件皆係線圈33之部分。因此，封裝100’包含線圈33及各別電連接結構，但不包含額外裝置，且封裝100’係一離散線圈。 圖16圖解說明根據本揭露之某些實施例之封裝100’之一俯視圖，其中圖15中所展示之剖面圖係自含有圖16中之線15-15之平面獲得。如圖16中所展示，線圈33延伸至封裝100’之近端所有邊緣，惟留出某一製程餘裕以確保一充分但不過量之囊封材料52在線圈33之外側上除外。因此，封裝100’之佔用面積大小(俯視區)被最小化。線圈33外側上的囊封材料52之部分防止線圈33暴露於外界空氣。如圖16中所展示，線圈33之內部或外部及囊封材料52中不存在主動裝置及被動裝置。 圖17圖解說明根據某些實施例之封裝100’之一剖面圖。如圖17中所展示，被動裝置56A在介電層54、60及66上方，且可透過銲區68而接合至金屬墊64。裝置晶粒38及/或被動裝置56B嵌入於囊封材料52中。撓曲PCB 72連接至金屬墊70 (舉例而言，透過銲區68)。此外，被動裝置56A可直接與被動裝置56B重疊以更好地使用封裝區域且減小所得封裝之佔用面積。 根據某些實施例，鐵氧體材料74透過(舉例而言)黏合劑膜76而附接至介電層66。鐵氧體材料74可包含錳鋅、鎳鋅或諸如此類。鐵氧體材料74在高頻率下具有相對低損耗，且用於增加電感器33之電感。鐵氧體材料74與線圈33重疊，且鐵氧體材料74之邊緣可與線圈33之邊緣實質上同終點。 圖19圖解說明圖14及圖16中之封裝100’之部分82之一經放大視圖，其中兩個貫穿導體32經圖解說明為一實例。為減小應力，貫穿導體32可具有經修圓隅角。舉例而言，貫穿導體之半徑R1可在介於約W1/2與2W1/3之間的範圍中。 根據某些實施例，為提高效率，線圈33之外環可具有大於或等於內環之寬度的寬度。舉例而言，參考圖14及圖16，可係最外側環之寬度之寬度W1A可等於或大於最內側環之寬度W1B。W1B/W1A之比率可係在介於約1/2與約2/3之間的範圍中。此外，自外環至內環，貫穿導體32之寬度可逐漸減小或每數環週期性地減小。 圖20圖解說明根據某些實施例之包含一雙線線圈33之封裝100’。為一較清晰視圖起見，圖20中未圖解說明將線圈33之端部連接至裝置晶粒38A之RDL 58及64 (圖14)。圖20中之線圈33可與圖14或圖16中之對應線圈基本上相同，惟線圈33具有兩個平行貫穿導體32A及32B盤繞而非具有一單個貫穿導體32盤繞除外。貫穿導體32A與32B彼此平行，且組合起來像一單個導體一樣用於形成線圈。為辨別貫穿導體32A與32B，使得可清晰地看見其佈局，使用不同圖案來展示貫穿導體32A及32B。 如圖20中所展示，貫穿導體32A及32B中之每一者本身形成一線圈。貫穿導體32A及32B之端部係透過連接器74A及74B互連。連接器74A及74B中之每一者可係當貫穿導體32A及32B形成時而同時形成之一貫穿通路，或可係RDL 58及64之一部分。連接器74A及74B亦可包含貫穿導體部分及RDL部分兩者。根據某些實施例，貫穿導體32A及32B僅在其端部處而不在中間連接，如圖20中所展示。根據替代實施例，類似於連接器74A及74B之額外連接器可週期性地形成以使貫穿導體32A之中間部分與貫穿導體32B之各別中間部分互連。舉例而言，貫穿導體32A及32B之每一筆直部分可包含一或多個互連器。如圖19及圖20中所展示之線圈33可與如所圖解說明之所有實施例組合。 由於貫穿導體32A及32B之互連，因此貫穿導體32A及32B以組合形式形成線圈。當圖20中之線圈33以一高頻率(舉例而言，數兆赫或更高)操作時，其具有可與如圖14及圖16中所展示之塊體線圈33相當且有時優於塊體線圈33之效能。此可由集膚效應所致。此外，在貫穿導體32A及32B與一塊體線圈相比更窄(由於其相當於移除如圖14及圖16中所展示之貫穿導體32之一中間部分)之情況下，鍍覆貫穿導體32A及32B之圖案負載效應減小。 本揭露之實施例具有某些有利特徵。線圈33形成於一囊封材料中，且因此線圈33之高度可具有一較大值。因此線圈33之電感係高的。線圈33亦可使用與用於封裝裝置晶粒相同之封裝製程來形成，且可將其與裝置晶粒及被動裝置整合於同一封裝內，從而達成封裝之佔用面積及製造成本之減小。 根據本揭露之某些實施例，一種方法包含：在一載體上方形成一線圈，將該線圈囊封於一囊封材料中，將該囊封材料之一頂部表面平坦化直至暴露該線圈為止，在該囊封材料及該線圈上方形成至少一個介電層，及形成延伸至該至少一個介電層中之複數個重新分佈線。該複數個重新分佈線電耦合至該線圈。 根據本揭露之某些實施例，一種方法包含：在一載體上方形成一線圈，其中在該線圈之一俯視圖中，該線圈包括環繞內環之外環；將該線圈囊封於一囊封材料中；研磨該囊封材料，其中該線圈之該等外環及該等內環之頂部表面由於該研磨而暴露；在該囊封材料及該線圈上方形成一介電層；及將該介電層圖案化以形成一第一開口及一第二開口。該線圈之一第一端部及一第二端部分別透過該第一開口及該第二開口而暴露。該方法進一步包含形成用以電耦合至該線圈之電連接。 根據本揭露之某些實施例，一結構包含：一線圈，其具有環繞內環之外環；及一囊封材料，其將該線圈囊封於其中。該囊封材料具有與該等外環之頂部表面及該等內環之頂部表面共面之一頂部表面。該結構進一步包含：一介電層，其在該囊封材料及該線圈上方且接觸該囊封材料及該線圈；一第一開口及一第二開口，其在該介電層中；及一第一重新分佈線及一第二重新分佈線，其分別延伸至該第一開口及該第二開口中以接觸該線圈之相對端部。 前述內容概述數項實施例之特徵，使得熟習此項技術者可較好地理解本揭露之態樣。熟習此項技術者應瞭解，其可容易地將本揭露用作用於設計或修改其他製程及結構以實現本文中所引入實施例之相同目的及/或達成相同優勢之一基礎。熟習此項技術者亦應意識到，此等等效構造並不脫離本揭露之精神及範疇，且應意識到其可在不脫離本揭露之精神及範疇之情況下在本文中作出各種改變、替代及更改。
13-13‧‧‧線15-15‧‧‧線20‧‧‧載體22‧‧‧離型層24‧‧‧介電層26‧‧‧晶種層28‧‧‧光阻劑30‧‧‧開口32‧‧‧導電構件/貫穿導體32A‧‧‧貫穿導體32B‧‧‧貫穿導體33‧‧‧線圈/整合式螺旋成形線圈/電感器/雙線線圈/塊體線圈34‧‧‧埠38‧‧‧裝置晶粒/藍芽低能量晶粒/AC-DC轉換器晶粒38A‧‧‧裝置晶粒/AC-DC轉換器晶粒38B‧‧‧裝置晶粒/藍芽低能量晶粒40‧‧‧晶粒附接膜42‧‧‧半導體基板44‧‧‧積體電路裝置46‧‧‧金屬柱48‧‧‧介電層50‧‧‧鈍化層52‧‧‧囊封材料54‧‧‧介電層55‧‧‧開口56‧‧‧被動裝置56A‧‧‧表面安裝裝置/被動裝置56B‧‧‧嵌入式被動裝置/被動裝置58‧‧‧重新分佈線59‧‧‧開口60‧‧‧介電層62‧‧‧開口64‧‧‧重新分佈線/金屬墊66‧‧‧介電層68‧‧‧電連接器/銲區70‧‧‧接墊/金屬墊72‧‧‧撓曲印刷電路板74‧‧‧鐵氧體材料74A‧‧‧連接器74B‧‧‧連接器76‧‧‧黏合劑膜82‧‧‧封裝100’之部分100‧‧‧封裝100’‧‧‧封裝110‧‧‧封裝組件R1‧‧‧半徑
當與附圖一起閱讀時，依據以下詳細說明最佳地理解本揭露之態樣。注意，根據行業中之標準實踐，各種構件並不按比例繪製。事實上，為討論之清晰起見，可任意地增大或減小各種構件之尺寸。 圖1至圖13圖解說明根據某些實施例之一封裝之形成中之中間階段之剖面圖。 圖14圖解說明根據某些實施例之包含一線圈、裝置晶粒及被動裝置之一封裝之一俯視圖。 圖15圖解說明根據某些實施例之包含一線圈且不包含裝置晶粒之一封裝之一剖面圖。 圖16圖解說明根據某些實施例之包含一線圈且不包含裝置晶粒之一封裝之一俯視圖。 圖17圖解說明根據某些實施例之包含一線圈、一裝置晶粒及一嵌入式被動裝置之一封裝之一剖面圖。 圖18圖解說明根據某些實施例之用於形成一封裝之一製程流程。 圖19圖解說明根據某些實施例之線圈之一部分。 圖20圖解說明根據某些實施例之一雙線線圈。

Claims (10)

  1. 一種線圈結構的製造方法，其包括：在一載體上方形成一線圈；透過一黏合劑膜安置一裝置晶粒於該載體上方；將該線圈囊封於一囊封材料中；將該囊封材料之一頂部表面平坦化直至暴露該線圈為止，其中當該平坦化完成時，該裝置晶粒、該線圈、及該囊封材料之頂部表面實質上共面，且該黏合劑膜、該線圈、及該囊封材料之底部表面實質上共面；在該囊封材料及該線圈上方形成至少一個介電層；及形成延伸至該至少一個介電層中之複數個重新分佈線，其中該複數個重新分佈線電耦合至該線圈。
  2. 如請求項1之線圈結構的製造方法，其中形成該線圈進一步包括將該線圈之一底部表面形成為與該囊封材料之一底部表面實質上共面，且不將除該線圈之外的額外導電構件囊封於該囊封材料中；執行一單粒化以將該線圈分離至一封裝中，其中在該封裝中無裝置晶粒及被動裝置；或者將一鐵氧體材料附接至該至少一個介電層，其中該鐵氧體材料與該線圈重疊。
  3. 如請求項1之線圈結構的製造方法，其中安置該裝置晶粒包括將一AC-DC轉換器晶粒安置在該載體上方，其中將該AC-DC轉換器晶粒囊封於該囊封材料中，且其中該方法進一步包括透過該複數個重新分佈線之部 分將該線圈電耦合至該AC-DC轉換器晶粒；將一整合式被動裝置接合於該至少一個介電層上方，其中將該整合式被動裝置電耦合至該複數個重新分佈線；或者，將一額外整合式被動裝置安置於該載體上方，其中將該額外整合式被動裝置囊封於該囊封材料中。
  4. 一種線圈結構的製造方法，其包括：在一載體上方形成一線圈，其中在該線圈之一俯視圖中，該線圈包括環繞內環之外環；將該線圈囊封於一囊封材料中；研磨該囊封材料，其中該線圈之該等外環及該等內環之頂部表面由於該研磨而暴露；在該囊封材料及該線圈上方形成一介電層；將該介電層圖案化以形成一第一開口及一第二開口，其中該線圈之一第一端部及一第二端部分別透過該第一開口及該第二開口而暴露；及形成用以電耦合至該線圈之電連接。
  5. 如請求項4之線圈結構的製造方法，其進一步包括將該載體與該線圈及該囊封材料拆分開；執行一單粒化以將該線圈分離至一封裝中，其中在該封裝中無裝置晶粒及被動裝置；該線圈之該等外環及該等內環之底部表面與一介電材料接觸；或者，附接與該線圈重疊之一鐵氧體材料。
  6. 如請求項4之線圈結構的製造方法，其進一步包括將一整合式被動裝 置接合於該介電層上方；或者將一額外整合式被動裝置安置於該載體上方，其中該額外整合式被動裝置由該囊封材料囊封。
  7. 如請求項4之線圈結構的製造方法，其中該形成該線圈包括：在該載體上方沈積一晶種層；在該晶種層上方施塗一光阻劑；將該光阻劑圖案化以在該光阻劑中形成至少一個開口；在該至少一個開口中鍍覆一金屬材料；及蝕刻未被該線圈覆蓋的該晶種層之部分。
  8. 一種線圈結構，其包括：一線圈，其包括環繞內環之外環，其中該線圈之隅角經修圓；一囊封材料，其將該線圈囊封於其中，其中該囊封材料具有與該等外環之頂部表面及該等內環之頂部表面共面之一頂部表面；一介電層，其在該囊封材料上方且接觸該囊封材料；一第一開口及一第二開口，其在該介電層中；及一第一重新分佈線及一第二重新分佈線，其分別延伸至該第一開口及該第二開口中以接觸該線圈之相對端部。
  9. 如請求項8之線圈結構，其中該囊封材料環繞由該線圈環繞之一區之一整體；或者該線圈係包含兩個平行導體之一雙線線圈，且該線圈之相對端部係互連的。
  10. 如請求項8之線圈結構，其進一步包括囊封於該囊封材料中之一裝置晶粒，其中該裝置晶粒之導電構件具有與該囊封材料之一頂部表面共面之頂部表面，其中該裝置晶粒係一整合式被動裝置晶粒，且該整合式被動裝置晶粒之導電構件具有與該囊封材料之一頂部表面共面之頂部表面。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10530175B2 (en) 2016-08-09 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Hexagonal semiconductor package structure
TWI651919B (zh) * 2017-07-10 2019-02-21 建準電機工業股份有限公司 用於馬達之驅動組件及用於馬達激磁之半導體封裝結構
US10522526B2 (en) * 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
CN107705971A (zh) * 2017-08-30 2018-02-16 歌尔股份有限公司 一种线圈的制造方法、线圈、电子设备
CN107705976B (zh) * 2017-08-30 2020-08-25 潍坊歌尔微电子有限公司 一种线圈的制造方法、线圈、电子设备
US11315891B2 (en) 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant
US11043420B2 (en) * 2018-09-28 2021-06-22 Semiconductor Components Industries, Llc Fan-out wafer level packaging of semiconductor devices
US11189521B2 (en) * 2018-10-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing redistribution circuit structures using phase shift mask
TWI747288B (zh) * 2019-12-12 2021-11-21 友達光電股份有限公司 晶片
US11610921B2 (en) * 2019-12-12 2023-03-21 Au Optronics Corporation Chip having a flexible substrate
US11133273B2 (en) * 2019-12-17 2021-09-28 Nxp Usa, Inc. Semiconductor device with waveguide and method therefor
US11227837B2 (en) * 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
CN111863422A (zh) * 2020-08-18 2020-10-30 翔声科技（厦门）有限公司 一种薄膜电感器的制作工艺

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110241793A1 (en) * 2010-03-30 2011-10-06 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RF Balun Having Reduced Capacitive Coupling and High CMRR
US20120168963A1 (en) * 2009-03-13 2012-07-05 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors
US20140076617A1 (en) * 2012-09-20 2014-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Passive Devices in Package-on-Package Structures and Methods for Forming the Same
US20150228416A1 (en) * 2013-08-08 2015-08-13 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Polymer Frame for a Chip, Such That the Frame Comprises at Least One Via in Series with a Capacitor
US20150296617A1 (en) * 2014-04-09 2015-10-15 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Interposer frame with polymer matrix and methods of fabrication

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652173A (en) 1996-05-09 1997-07-29 Philips Electronics North America Corporation Monolithic microwave circuit with thick conductors
US7167072B2 (en) * 2004-03-25 2007-01-23 United Microelectronics Corp. Method of fabricating inductor and structure formed therefrom
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
TWI438696B (zh) * 2009-08-21 2014-05-21 Univ Nat Chiao Tung Chip inductor structure and manufacturing method thereof
US9324672B2 (en) * 2009-08-21 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming dual-active sided semiconductor die in fan-out wafer level chip scale package
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8624353B2 (en) 2010-12-22 2014-01-07 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device over semiconductor die with conductive bridge and fan-out redistribution layer
US8569861B2 (en) 2010-12-22 2013-10-29 Analog Devices, Inc. Vertically integrated systems
JP5842393B2 (ja) * 2011-06-10 2016-01-13 富士通株式会社 受光デバイス、これを用いた光受信機、及び受光デバイスの製造方法
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US8618631B2 (en) 2012-02-14 2013-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. On-chip ferrite bead inductor
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
JP6008237B2 (ja) * 2012-06-28 2016-10-19 パナソニックＩｐマネジメント株式会社 携帯端末
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US9726518B2 (en) 2012-07-13 2017-08-08 Qualcomm Incorporated Systems, methods, and apparatus for detection of metal objects in a predetermined space
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8896094B2 (en) * 2013-01-23 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for inductors and transformers in packages
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9378982B2 (en) * 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9515060B2 (en) * 2013-03-20 2016-12-06 Infineon Technologies Austria Ag Multi-chip semiconductor power device
US9673134B2 (en) * 2013-12-11 2017-06-06 Semiconductor Components Industries, Llc Semiconductor component and method of manufacture
CN103838025B (zh) 2014-02-20 2016-08-31 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
US9888577B2 (en) * 2014-03-28 2018-02-06 Intel Corporation Passive electrical devices with a polymer carrier
US9704739B2 (en) * 2014-07-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9735102B2 (en) * 2015-03-18 2017-08-15 Globalfoundries Singapore Pte. Ltd. High voltage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120168963A1 (en) * 2009-03-13 2012-07-05 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors
US20110241793A1 (en) * 2010-03-30 2011-10-06 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RF Balun Having Reduced Capacitive Coupling and High CMRR
US20140076617A1 (en) * 2012-09-20 2014-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Passive Devices in Package-on-Package Structures and Methods for Forming the Same
US20150228416A1 (en) * 2013-08-08 2015-08-13 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Polymer Frame for a Chip, Such That the Frame Comprises at Least One Via in Series with a Capacitor
US20150296617A1 (en) * 2014-04-09 2015-10-15 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Interposer frame with polymer matrix and methods of fabrication

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