KR100817030B1 - 반도체 패키지 및 이의 제조방법 - Google Patents
반도체 패키지 및 이의 제조방법 Download PDFInfo
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- KR100817030B1 KR100817030B1 KR1020060120707A KR20060120707A KR100817030B1 KR 100817030 B1 KR100817030 B1 KR 100817030B1 KR 1020060120707 A KR1020060120707 A KR 1020060120707A KR 20060120707 A KR20060120707 A KR 20060120707A KR 100817030 B1 KR100817030 B1 KR 100817030B1
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Abstract
Description
Claims (16)
- 제 1 면과 이의 반대면인 제 2 면을 갖는 반도체다이;상기 반도체다이의 상기 제 1 면과 전기적으로 연결되는 제 1 도전패드;상기 제 1 도전패드와 이격되는 적어도 하나의 제 2 도전패드;상기 반도체 다이의 상기 제 2 면과 상기 제 2 도전패드 각각을 전기적으로 연결하는 적어도 하나의 도전와이어; 및상기 반도체다이, 상기 제1도전패드, 상기 제 2 도전패드 및 상기 도전와이어를 봉지하는 인캡슐란트를 포함하고,상기 제 1 및 제 2 도전패드는 각각 제 1 금속층을 중심으로 상, 하면에 제 2 금속층 및 제 3 금속층이 형성되며, 상기 각각의 제 1 금속층은 측면이 오목 및 볼록한 형상 중 선택된 어느 하나의 형상으로 형성되고,상기 제 1 금속층은,상기 제 2 금속층 및 상기 제 3 금속층에 비해 동일한 식각액에 대한 반응도가 높은 금속인 것을 특징으로 하는 반도체패키지.
- 제 1 항에 있어서,상기 반도체 다이의 상기 제 1 면은, 상기 제 1 도전패드의 상기 제 2 금속층에 솔더에 의해 전기적으로 연결된 것을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 제 1 및 제 2 도전패드는 제 3 금속층이 상기 인캡슐란트의 외측으로 노출된 것을 특징으로 하는 반도체 패키지.
- 삭제
- 제 1 항에 있어서,상기 제 1 금속층은,상기 제 2 금속층 및 상기 제 3 금속층에 비해 동일한 식각액에 대한 반응도가 낮은 금속인 것을 특징으로 하는 반도체패키지.
- 제 1 항에 있어서,상기 제 1 금속층과 상기 제 3 금속층은 동일한 금속인 것을 특징으로 하는 반도체패키지.
- 제 3 항에 있어서,상기 제 3 금속층은,상기 인캡슐란트의 외부로 노출된 면에 솔더볼 및 랜드 중 선택된 어느 하나가 부착되는 것을 특징으로 하는 반도체패키지.
- 서브스트레이트를 준비하는 단계;상기 서브스트레이트 상에 접착층을 형성하는 단계;제 1 및 제 2 금속층을 포함하여 적어도 2층의 금속층으로 구성되는 도전패드모재를 상기 접착층 상에 부착하는 단계;상기 도전패드모재를 패터닝하여 도전패드를 형성하는 단계;상기 도전패드와 전기적으로 연결되도록 반도체다이를 실장하는 단계;상기 도전패드 및 상기 반도체다이를 인캡슐레이션하는 단계; 및상기 접착층 및 상기 서브스트레이트를 제거하는 단계;를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 8 항에 있어서,상기 서브스트레이트는,금속 박판 및 합성수지 필름 중 선택된 어느 하나인 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 8 항에 있어서,상기 도전패드모재는,상기 제 1 금속층을 사이에 두고 상기 제 2 금속층과 대면하도록 상기 제 2 금속층에 접합되는 제 3 금속층을 더 포함하여 구성되는 것을 특징으로 하는 반도 체 패키지의 제조방법.
- 제 10 항에 있어서,상기 도전패드 형성단계는,상기 도전패드모재 상에 패턴을 형성하는 단계, 및상기 패턴이 형성된 상기 도전패드모재를 식각액에 의해 식각하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 11 항에 있어서,상기 제 1 금속층은,상기 식각액에 의해 상기 제 2 금속층보다 더 식각되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 11 항에 있어서,상기 제 1 금속층은,상기 식각액에 의해 상기 제 2 금속층보다 덜 식각되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 11 항에 있어서,상기 제 3 금속층은 상기 제 2 금속층과 동일한 금속인 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 8 항에 있어서,상기 반도체다이 실장단계는,상기 반도체다이와 상기 제 2 금속층을 도전와이어에 의해 연결하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 패키지의 제조방법.
- 제 10 항에 있어서,상기 서브스트레이트 및 상기 접착층이 제거된 상기 제 3 금속층에 솔더볼 및 랜드 중 선택된 어느 하나를 부착하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조방법.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103311216A (zh) * | 2013-05-20 | 2013-09-18 | 江苏长电科技股份有限公司 | 新型高密度多层线路芯片倒装封装结构及制作方法 |
WO2016207220A1 (de) * | 2015-06-22 | 2016-12-29 | Osram Opto Semiconductors Gmbh | Herstellung elektronischer bauelemente |
CN112652544A (zh) * | 2020-12-22 | 2021-04-13 | 长电科技(滁州)有限公司 | 一种封装结构及其成型方法 |
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JP2001250884A (ja) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004119726A (ja) | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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JP2001250884A (ja) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP2004119726A (ja) | 2002-09-26 | 2004-04-15 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
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CN103311216A (zh) * | 2013-05-20 | 2013-09-18 | 江苏长电科技股份有限公司 | 新型高密度多层线路芯片倒装封装结构及制作方法 |
CN103311216B (zh) * | 2013-05-20 | 2016-02-24 | 江苏长电科技股份有限公司 | 高密度多层线路芯片倒装封装结构及制作方法 |
WO2016207220A1 (de) * | 2015-06-22 | 2016-12-29 | Osram Opto Semiconductors Gmbh | Herstellung elektronischer bauelemente |
CN112652544A (zh) * | 2020-12-22 | 2021-04-13 | 长电科技(滁州)有限公司 | 一种封装结构及其成型方法 |
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