TWI642152B - 半導體封裝組件 - Google Patents

半導體封裝組件 Download PDF

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Publication number
TWI642152B
TWI642152B TW105109810A TW105109810A TWI642152B TW I642152 B TWI642152 B TW I642152B TW 105109810 A TW105109810 A TW 105109810A TW 105109810 A TW105109810 A TW 105109810A TW I642152 B TWI642152 B TW I642152B
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Taiwan
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semiconductor package
semiconductor
bare
wafer
item
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TW105109810A
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TW201707164A (zh
Inventor
林子閎
彭逸軒
蕭景文
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聯發科技股份有限公司
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Publication of TW201707164A publication Critical patent/TW201707164A/zh
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Publication of TWI642152B publication Critical patent/TWI642152B/zh

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Abstract

本揭露提供一種半導體封裝組件。半導體封裝組件包括一第一半導體封裝體，其包括一第一半導體裸晶片。一第一重佈線結構耦接至第一半導體裸晶片。第一重佈線結構包括設置於第一層位的一第一導線。一第二導線設置於第二層位。一第一金屬層間介電層及位於第一金屬層間介電層附近的一第二金屬層間介電層設置於第一導線與第二導線之間。

Description

半導體封裝組件
本揭露係關於一種半導體封裝組件，且特別是關於一種具有被動裝置之半導體封裝組件。
為了確保電子產品及通訊裝置的微型化及多功能性，所需的半導體封裝體需具備小尺寸、支援多引腳(pin)連接、高速操作以及高功能性。另外，在高頻應用(例如，射頻(radio frequency,RF)系統封裝(system in package,SiP)組件)中，通常使用一或多個整合的被動裝置(integrated passive device,IPD)來進行上述功能。
在傳統的SiP組件中，被動裝置時常放置於一印刷電路板(printed circuit board,PCB)或一封裝體上。然而，印刷電路板須提供額外的區域以將被動裝置組裝於其上。另外，當被動裝置組裝於封裝體上時，SiP組件的總體高度將會增加。如此一來，勢必難以縮小封裝組件的尺寸。
因此，需要尋求一種新的半導體封裝組件。
本發明提供了一種半導體封裝組件，具有整合了的電子部件(如被動設備)。
根據一實施例，本揭露提供一種半導體封裝組件，包括一第一半導體封裝體。第一半導體封裝體包括一第一 重佈線結構，具有一第一表面及與其相對的一第二表面。第一半導體封裝體更包括一第一半導體裸晶片，設置於第一重佈線結構的第一表面上。第一半導體封裝體更包括一第一模塑化合物(molding compound)，設置於第一重佈線結構的第一表面上，且圍繞第一半導體裸晶片。第一半導體封裝體更包括一電子部件(如被動設備)，嵌入於第一重佈線結構內，且經由第一重佈線結構電性耦接至第一半導體裸晶片。
以上揭露之半導體封裝組件，電子部件(如被動設備)嵌入於重佈線結構內，且經由重佈線結構電性耦接至半導體裸晶片，從而將電子部件(如被動設備)整合進了半導體封裝組件中的重佈線結構內。
10a、10b、10c、10d、10e、10f‧‧‧半導體封裝組件
100、160、400a、400b‧‧‧半導體裸晶片
100a、100b、100c、100d、100e、100f、200a‧‧‧半導體封裝體
101、201‧‧‧第一表面
103、203‧‧‧第二表面
104、304‧‧‧模塑化合物
106‧‧‧通孔電極
109、164、308、310、325‧‧‧接墊
111、130、328‧‧‧導電結構
120、220、320‧‧‧金屬層間介電(IMD)層
120a、220a、320a‧‧‧第一次介電層
120b、220b、320b‧‧‧第二次介電層
120c、220c、320c‧‧‧第三次介電層
121、323‧‧‧第二導線
123、321‧‧‧第一導線
126、226、326‧‧‧重佈線(RDL)結構
150‧‧‧多層陶瓷電容(MLCC)
150’‧‧‧晶片電容
152、152’‧‧‧本體
154、154’‧‧‧第一電極層
156、156’‧‧‧第二電極層
221‧‧‧導線
223‧‧‧介層連接窗
300、302‧‧‧動態隨機存取記憶體(DRAM)裸晶片
301、303、602‧‧‧表面
314、316‧‧‧接線
600‧‧‧基體
A1、A2‧‧‧區域
第1A圖係繪示出根據本發明揭露一些實施例之半導體封裝組件剖面示意圖。
第1B圖係第1A圖中區域A1的放大圖，其繪示出多層陶瓷電容(multi-layer ceramic capacitor,MLCC)嵌入於重佈線結構內。
第1C圖係繪示出根據本揭露一些實施例之半導體封裝組件剖面示意圖。
第2A圖係繪示出根據本揭露一些實施例之半導體封裝組件剖面示意圖。
第2B圖係第2A圖中區域A2的放大圖，其繪示出晶片電容(chip-cap capacitor)嵌入於重佈線結構內。
第2C圖係繪示出根據本揭露一些實施例之半導體封裝組件剖面示意圖。
第3圖係繪示出根據本揭露一些實施例之具有層疊封裝(package on package,PoP)結構的半導體封裝組件的剖面示意圖。
第4圖係繪示出根據本揭露一些實施例之具有系統晶片(system-on-chip,SOC)封裝體的半導體封裝組件剖面示意圖，該SOC封裝體包括二個並排設置的半導體裸晶片(die)。
以下的說明為本發明之實施例。此說明之目的在於提供本發明的總體概念而並非用以侷限本發明的範圍。本發明之保護範圍當視後附之申請專利範圍所界定者為準。以下配合圖式說明本發明之實施例。
本發明將參照特定的實施例及參照圖式進行說明，然而並非用以侷限本發明的範圍而是以申請專利範圍所界定者為準。在所繪圖式中，某些部件的尺寸會為了闡述目的放大而未依比例繪示。外觀尺寸及相對尺寸並未對應於本發明的實際尺寸。
第1A圖係繪示出根據本揭露一些實施例之半導體封裝組件10a的剖面示意圖。第1B圖係第1A圖中區域A1的放大圖，其繪示出多層陶瓷電容(MLCC)150嵌入於重佈線結構內。在一些實施例中，半導體封裝組件10a為晶圓級半導體封裝組件，例如覆晶半導體封裝組件。
請參照第1A圖，半導體封裝組件10a包括至少一個 晶圓級半導體封裝體100a，裝設於一基體600上。在本實施例中，晶圓級半導體封裝體100a包括一系統晶片(SOC)封裝體。再者，基體600包括印刷電路板(PCB)，其可由聚丙烯(polypropylene,PP)所製成。在一些實施例中，基體600可包括一封裝基底。
在本實施例中，基體600可為一單層或多層結構。複數個導電墊(未繪示)及與其電性耦接的導線(未繪示)設置於基體600的表面602及/或基體600內。在此情形中，導線可包括信號導線區段及電源/接地區段，以供半導體封裝體100a的輸入/輸出(I/O)連接之用。在一實施例中，半導體封裝體100a直接裝設於導線上。在一些實施例中，設置於表面602的導電墊連接至不同的導線接端。在此情形中，這些導電墊供直接裝設於導線上的半導體封裝體100a之用。
半導體封裝體100a係藉由一接合製程裝設於基體600的表面602上。舉例來說，半導體封裝體100a包括複數個導電結構130，其藉由接合製程裝設於基體600上且電性耦接至基體600。半導體封裝體100a包括一半導體裸晶片100(例如，SOC裸晶片)及一重佈線(redistribution layer,RDL)結構126。舉例來說，SOC裸晶片可包括一邏輯裸晶片，其包括一中央處理單元(central processing unit,CPU)、圖像處理單元(graphics processing unit,GPU)、動態隨機存取記憶體(dynamic random access memory,DRAM)控制器或其任何組合。再者，舉例來說，導電結構130可包括一導電凸塊結構(例如銅凸塊或焊料凸塊結構)、導電柱體結構、導電接線結構或導電膏結構。
如第1A圖所示，由覆晶技術來製造半導體裸晶片100。半導體裸晶片100的接墊109電性連接至半導體裸晶片100的電路(未繪示)。在一些實施例中，接墊109屬於半導體裸晶片100的內連接結構(未繪示)的最上金屬層。半導體裸晶片100的接墊109與對應的導電結構111(例如，導電凸塊、柱體或錫膏)接觸。需注意的是整合於半導體封裝組件10a內的半導體裸晶片100的數量並未局限於所述的實施例。
重佈線(RDL)結構126(其也稱作扇出式(fan-out)結構)具有一第一表面101及與其相對的一第二表面103。半導體裸晶片100設置於RDL結構126的第一表面126上。半導體封裝體100a的半導體裸晶片100經由導電結構111而連接至RDL結構126。
在本實施例中，RDL結構126包括一或多個導線，設置於一金屬層間介電(inter-metal dielectric,IMD)層120內。舉例來說，複數個第一導線123設置於IMD層120內的一第一層位，且至少一第一導線123電性耦接至半導體裸晶片100。再者，複數個第二導線121設置於IMD層120內不同於第一層位的一第二層位。在此情形中，IMD層120可包括第一、第二及第三次介電層(sub-dielectric layer)120a、120b及120c，依序從RDL結構126的第二表面103朝向RDL結構126的第一表面101堆疊，使第一導線123位於第三次介電層120c上，而第二導線121位於第二次介電層120b上且為第一次介電層120a所覆蓋。再者，第一導線123藉由第二次介電層120b而與第二導線121隔開。在一些實施例中，IMD層120可由有機材料(包括高 分子材料)或無機材料(包括氮化矽(SiNx)、氧化矽(SiOx)、石墨烯(graphene)等等)所形成。舉例來說，第一、第二及第三次介電層120a、120b及120c由高分子材料製成，其中第一次介電層120a的厚度約為12微米(μm)，且第二次介電層120b的厚度約為24微米。
在一些實施例中，IMD層120為高k值介電層(k為介電層的介電常數)。在其他一些實施例中，IMD層120可由光敏性材料所製成，其包括乾膜光阻或膠帶膜(taping film)。
第二導線121的接墊部從第一次介電層120a的開口露出，且連接至導電結構130(其設置於RDL結構126的第二表面103)。同樣需注意的是第1A圖中導線的數量及RDL結構126中次介電層的數量僅為例示，且本發明並未侷限於此。
在本實施例中，半導體封裝體100a更包括至少一個電子部件，例如整合的被動裝置(IPD)，嵌入於RDL結構126內。IPD係經由RDL結構126電性耦接至半導體裸晶片100。在一些實施例中，IPD可包括電容、電感、電阻或其組合。再者，IPD包括至少一個電極，電性耦接至該等第二導線121的其中一者。
在本實施例中，舉例來說，IPD可為一電容，例如多層陶瓷電容(MLCC)150，如第1A及1B圖所示。MLCC 150係電性耦接至半導體裸晶片100。在此情形中，MLCC 150包括一本體152與分別設置於本體152兩端的第一及第二電極層154及156。再者，第一及第二電極層154及156覆蓋本體152的側壁、部分的上表面及部分的下表面。第一及第二電極層154及 156分別電性耦接於該等第二導線121中的至少二者。
在本實施例中，如第1A圖所示，半導體封裝體100a更包括一模塑化合物104，設置於RDL結構126的第一表面101上，且覆蓋並圍繞半導體裸晶片100。在一些實施例中，模塑化合物104由環氧化物、樹脂、可塑型高分子等等形成。模塑化合物104在實質上為液體時應用，接著經由化學反應而固化，例如位於環氧化物或樹脂中。在其他一些實施例中，模塑化合物104可為紫外光(UV)或熱力固化高分子，其為膠體或具延展性固體，且能夠設置於半導體裸晶片100周圍，接著可經由UV或熱力固化製程將其固化。模塑化合物104可以一模具(未繪示)進行固化。
在本實施例中，模塑化合物104包括穿過其內的通孔電極(via)106。通孔電極106電性耦接至RDL結構126的第一導線123，然後再經由第一導線123耦接至RDL結構126的第二導線121。再者，通孔電極106可圍繞半導體裸晶片100。在一些實施例中，通孔電極106可包括由銅構成的通過封裝體通孔電極(through package via,TPV)。
同樣地，導電結構130經由RDL結構126而與模塑化合物104隔開。換句話說，導電結構130未與模塑化合物104接觸。在一些實施例中，導電結構130可包括導電凸塊結構(例如，銅或焊料凸塊結構)、導電柱體結構、導電接線結構或導電膏結構。
根據上述實施例，半導體封裝組件10a係設計成用以製造IPD結構。舉例來說，MLCC 150嵌入於RDL結構126內。 MLCC 150於半導體封裝組件中提供可比擬的製程能力。再者，半導體封裝組件10a有助於改善表面黏著技術(surface-mount technology,SMT)良率，即使更換半導體裸晶片(例如，半導體裸晶片100)時。另外，由於縮短了半導體裸晶片(例如，半導體裸晶片100)與MLCC 150之間的佈線路徑，因此可改善嵌入的MLCC 150的信號完整性/電源完整性(signal integrity/power integrity,SI/PI)效能。嵌入的MLCC 150可為半導體封裝組件10a的系統整合提供設計彈性。
第1C圖係繪示出根據本揭露一些實施例之半導體封裝組件10b剖面示意圖。以下部件的實施例的說明係省略說明相同或相似於先前第1A圖中所述的部件。在本實施例中，除了半導體封裝組件10b的半導體封裝體100b更包括一半導體裸晶片160(例如，SOC裸晶片)嵌入於RDL結構126內以外，半導體封裝組件10b相似於第1A圖所示的半導體封裝組件10a。半導體裸晶片160係經由RDL結構126電性耦接至半導體裸晶片100。
再者，半導體裸晶片160包括至少一個接墊，電性耦接至該等第二導線121的其中一者。舉例來說，半導體裸晶片160包括接墊164，其電性耦接至第二導線121。
根據此實施例，半導體封裝組件10b係設計成用以製造IPD結構(即MLCC 150)及嵌入於RDL結構126內的半導體裸晶片160。MLCC 150及半導體裸晶片160於半導體封裝組件中提供可比擬的製程能力。再者，半導體封裝組件10b有助於改善SMT良率，即使更換半導體裸晶片(例如，半導體裸晶 片100)時。另外，由於縮短了半導體裸晶片(例如，半導體裸晶片100)與MLCC 150及半導體裸晶片160之間的佈線路徑，因此可改善嵌入的MLCC 150及半導體裸晶片160的SI/PI效能。嵌入的MLCC 150及半導體裸晶片160可對半導體封裝組件10b的系統整合提供設計彈性。
第2A圖係繪示出根據本揭露一些實施例之半導體封裝組件10c的剖面示意圖，而第2B圖係第2A圖中區域A2的放大圖，其繪示出晶片電容150’嵌入於重佈線結構內。以下部件的實施例的說明係省略說明相同或相似於先前第1A及1B圖中所述的部件。
在本實施例中，除了半導體封裝組件10c的半導體封裝體100c包括一晶片電容150’取代第1A及1B圖中的MLCC 150嵌入於RDL結構126內以外，半導體封裝組件10c相似於第1A圖所示的半導體封裝組件10a。
再者，晶片電容150’電性耦接至半導體裸晶片100。在此情形中，晶片電容150’包括一本體152’與分別設置於本體152’兩端的第一及第二電極層154’及156’。再者，第一及第二電極層154’及156’露出本體152’的部分側壁、本體152’的上表面與本體152’的部分下表面。第一及第二電極層154’及156’分別電性耦接於該等第二導線121中的至少二者。
根據上述實施例，半導體封裝組件10c係設計成用以製造IPD結構。舉例來說，晶片電容150’嵌入於RDL結構126內。晶片電容150’於半導體封裝組件中提供可比擬的製程能力。相似地，半導體封裝組件10c有助於改善SMT良率，即使 更換半導體裸晶片(例如，半導體裸晶片100)時。另外，由於縮短了半導體裸晶片(例如，半導體裸晶片100)與晶片電容150’之間的佈線路徑，因此可改善嵌入的晶片電容150’的SI/PI效能。嵌入的晶片電容150’可為半導體封裝組件10c的系統整合提供設計彈性。
第2C圖係繪示出根據本揭露一些實施例之半導體封裝組件10d剖面示意圖。以下部件的實施例的說明係省略說明相同或相似於先前第1C圖中所述的部件。在本實施例中，除了半導體封裝組件10d的半導體封裝體100d更包括一半導體裸晶片160(例如，SOC裸晶片)嵌入於RDL結構126內以外，半導體封裝組件10d相似於第2A圖所示的半導體封裝組件10c。半導體裸晶片160經由RDL結構126電性耦接至半導體裸晶片100。再者，半導體裸晶片160包括至少一接墊電性耦接至第二導線121的其中一者。舉例來說，半導體裸晶片160包括接墊164，其電性耦接至第二導線121。
根據此實施例，半導體封裝組件10d係設計成用以製造IPD結構(即，晶片電容150’)及嵌入於RDL結構126內的半導體裸晶片160。晶片電容150’及半導體裸晶片160於半導體封裝組件中提供可比擬的製程能力。再者，半導體封裝組件10d有助於改善SMT良率，即使更換半導體裸晶片(例如，半導體裸晶片100)時。另外，由於縮短了半導體裸晶片(例如，半導體裸晶片100)與晶片電容150’及半導體裸晶片160之間的佈線路徑，因此可改善嵌入的晶片電容150’及半導體裸晶片160的SI/PI效能。嵌入的晶片電容150’及半導體裸晶片160可為半 導體封裝組件10b的系統整合提供設計彈性。
第3圖係繪示出根據本揭露一些實施例之具有層疊封裝(PoP)結構的半導體封裝組件剖面示意圖。以下部件的實施例的說明係省略說明相同或相似於先前第1A至1C圖或第2A至2C圖中所述的部件。在本實施例中，除了半導體封裝體100e更包括一RDL結構226設置於半導體裸晶片100及模塑化合物104上，使RDL結構226藉由半導體裸晶片100及模塑化合物104而與RDL結構126隔開以外，半導體封裝體100e相似於第2A圖所示的半導體封裝體100c。再者，通孔電極106穿過模塑化合物104而形成RDL結構126與RDL結構226之間的電性連接。
RDL結構226具有一第一表面201及與其相對的一第二表面203。RDL結構226的第一表面201位於半導體裸晶片100及模塑化合物104上。亦即，相較於第二表面203，第一表面201係靠近於半導體裸晶片100且與模塑化合物104接觸。如同RDL結構126，RDL結構226可包括一或多個導線設置於一IMD層220內。舉例來說，複數個導線221及複數個介層連接窗223設置於IMD層220內，且該等導線221的其中至少一者電性連接至通孔電極106。在此情形中，IMD層220類似於IMD層120，且可包括第一、第二及第三次介電層220a、220b及220c依序從RDL結構226的第二表面203朝向RDL結構226的第一表面201堆疊。再者，IMD層220由類似於IMD層120的材料形成。
導線221的接墊部從第三次介電層220c的開口處露出。需注意的是第3圖中導線221與介層連接窗223的數量及 IMD層220的次介電層的數量僅為例示，且本發明並未侷限於此。如第3圖所示，RDL結構226藉由穿過RDL結構126與RDL結構226之間的模塑化合物104的通孔電極106而耦接至RDL結構126。
在一些實施例中，嵌入於RDL結構126內的晶片電容150’可取代為MLCC 150，如第1A圖所示。在一些實施例中，半導體裸晶片160與晶片電容150’或MLCC 150可一同嵌入於RDL結構126內，如第1C或2C圖所示。
在本實施例中，如第3圖所示，半導體封裝組件10e包括一半導體封裝體200a藉由一接合製程而疊置於半導體封裝體100e上。半導體封裝體200a可包括一記憶體封裝體，例如DRAM封裝體。半導體封裝體200a包括複數個導電結構328裝設於半導體封裝體100e上。半導體封裝體200a藉由半導體封裝體100e的RDL結構226及通孔電極106而耦接至RDL結構126。
在本實施例中，如第3圖所示，半導體封裝體200a包括一RDL結構326、至少一半導體裸晶片(例如，二個DRAM裸晶片300及302)及一模塑化合物304。RDL結構326具有相對的表面301及303。表面301供半導體裸晶片裝設於其上之用，而表面303供導電結構328(例如，凸塊)貼合於其上之用。
如同RDL結構126，RDL結構326可包括一或多個位於IMD層320內的導線。舉例來說，複數個第一導線321及複數個第二導線323設置於IMD層320內的不同層位。IMD層320的結構及材料類似於IMD層120的結構及材料。舉例來說，IMD層320可包括第一、第二及第三次介電層320a、320b及220c，依序從 RDL結構326的表面303朝向RDL結構326的表面301堆疊。
第一導線321的接墊部從第一次介電層320a的開口處露出。需注意的是第3圖中導線的數量及IMD層320的次介電層的數量僅為例示，且本發明並未侷限於此。
在此實施例中，如第3圖所示，半導體裸晶片302及300依序疊置於RDL結構326的表面301上，其中半導體裸晶片302利用一膏料(未繪示)而裝設於RDL結構326上。同樣地，半導體裸晶片300利用一膏料(未繪示)而疊置於半導體裸晶片302上。半導體裸晶片302具有接墊308位於其上，而半導體裸晶片300具有接墊310位於其上。
接墊308及310可分別藉由接線(例如，接線314及316)耦接至RDL結構326的接墊325。需注意的是半導體封裝體200a內堆疊的半導體裸晶片的數量並未局限於所述的實施例。在其他實施例中，二個半導體裸晶片300及302也可並排排列。
在本實施例中，模塑化合物304設置於RDL結構326的表面301上。再者，模塑化合物304覆蓋並圍繞二個半導體裸晶片300及302。模塑化合物304可由相同或相似於模塑化合物104的材料形成。
如第3圖所示，導電結構328設置於RDL結構326的表面303上，且電性耦接於RDL結構326的第一導線321與RDL結構226的介層連接窗223之間。半導體封裝體200a電性耦接至半導體封裝體100e的RDL結構126。如同導電結構130，導電結構328可包括銅或焊料凸塊結構、導電柱體結構、導電接線結 構或導電膏結構。
第4圖係繪示出根據本揭露其他一些實施例之半導體封裝組件10f的剖面示意圖，其包括具有二個並排的半導體裸晶片400a及400b的半導體封裝體100f。以下部件的實施例的說明係省略說明相同或相似於先前第1A至1B圖或第2A至2B圖中所述的部件。在本實施例中，如第4圖所示，半導體封裝體100f可為SOC封裝體，且包括二個並排設置的半導體裸晶片400a及400b。在一些實施例中，半導體裸晶片400a及400b中的至少一者為SOC裸晶片。舉例來說，半導體裸晶片400a及400b皆為SOC裸晶片。在其他實施例中，半導體裸晶片400a為SOC裸晶片，而半導體裸晶片400b為記憶體裸晶片，例如DRAM裸晶片。
在一些實施例中，IPD(例如，晶片電容150’)嵌入於RDL結構126內，且耦接至SOC裸晶片(例如，半導體裸晶片400a)。因此，半導體封裝組件10f的半導體封裝體100f包括純SOC封裝體或混合式SOC封裝體。然而，半導體裸晶片的數量及排列方式並未局限於所述的實施例。
在一些實施例中，嵌入於RDL結構126內的晶片電容150’可取代為MLCC 150，如第1A圖所示。在一些實施例中，一半導體裸晶片160及晶片電容150’或MLCC 150可一同嵌入於RDL結構126內，如第1C或2C圖所示。
第3及4圖所示的實施例提供一半導體封裝組件。在一些實施例中，半導體封裝組件係設計成用以製造IPD結構，例如嵌入於RDL結構126內的MLCC或晶片電容。半導體封 裝組件有助於改善SMT良率，即使更換半導體裸晶片(例如，SOC裸晶片)時。另外，由於縮短了半導體裸晶片(例如，SOC裸晶片)與IPD之間的佈線路徑，因此可改善嵌入的IPD的SI/PI效能。嵌入的IPD可為半導體封裝組件的系統整合提供設計彈性。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (15)

  1. 一種半導體封裝組件，包括：一第一半導體封裝體，包括：一第一重佈線結構，具有一第一表面及與其相對的一第二表面；一第一半導體裸晶片，設置於該第一重佈線結構的該第一表面上；一第一模塑化合物，設置於該第一重佈線結構的該第一表面上，且圍繞該第一半導體裸晶片；以及一電子部件，嵌入於該第一重佈線結構內，且經由該第一重佈線結構電性耦接至該第一半導體裸晶片；一第二半導體裸晶片，全部嵌入於該第一重佈線結構內。
  2. 如申請專利範圍第1項所述之半導體封裝組件，其中該電子部件為一被動裝置。
  3. 如申請專利範圍第1項或第2項所述之半導體封裝組件，其中該第一半導體封裝體更包括複數個第一導電結構，設置於該第一重佈線結構的該第二表面上，且電性耦接至該第一重佈線結構。
  4. 如申請專利範圍第3項所述之半導體封裝組件，其中更包括一印刷電路板，電性耦接至該等第一導電結構。
  5. 如申請專利範圍第1項或第2項所述之半導體封裝組件，其中該第一重佈線結構包括：一第一金屬層間介電層；複數個第一導線，位於該第一金屬層間介電層的一第一層位，且該等第一導線的其中一者電性耦接至該第一半導體裸晶片；以及複數個第二導線，位於該第一金屬層間介電層的不同於該第一層位的一第二層位。
  6. 如申請專利範圍第5項所述之半導體封裝組件，其中該電子部件包括至少一電極，電性耦接至該等第二導線的其中一者。
  7. 如申請專利範圍第2項所述之半導體封裝組件，其中該被動裝置包括電容、電感、電阻或其組合。
  8. 如申請專利範圍第1項或第2項所述之半導體封裝組件，其中該第一半導體封裝體還包括：一第二重佈線結構，設置於該第一半導體裸晶片及該第一模塑化合物上，使該第二重佈線結構藉由該第一半導體裸晶片及該第一模塑化合物而與該第一重佈線結構隔開；以及複數個第一通孔電極，穿過該第一模塑化合物以形成該第一重佈線結構與該第二重佈線結構之間的電性連接。
  9. 如申請專利範圍第8項所述之半導體封裝組件，其中更包括：一第二半導體封裝體，疊置於該第一半導體封裝體上，包括：一第三重佈線結構，電性耦接至該第二重佈線結構，且具有一第三表面及與其相對的一第四表面；一第三半導體裸晶片，設置於該第三重佈線結構的該第三表面上；以及一第二模塑化合物，設置於該第三重佈線結構的該第三表面上，且圍繞該第三半導體裸晶片。
  10. 如申請專利範圍第9項所述之半導體封裝組件，其中該第二半導體封裝體更包括複數個第二導電結構設置於該第三重佈線結構的該第四表面上，且電性耦接至該第二重佈線結構。
  11. 如申請專利範圍第9項所述之半導體封裝組件，其中該第一半導體封裝體為系統晶片封裝體，且該第二半導體封裝體為動態隨機存取記憶體封裝體。
  12. 如申請專利範圍第1項或第2項所述之半導體封裝組件，其中該第一半導體封裝體更包括一第四半導體裸晶片，設置於該第一重佈線結構的該第一表面上，使該第一半導體裸晶片及該第四半導體裸晶片並排排列。
  13. 如申請專利範圍第12項所述之半導體封裝組件，其中該第一半導體裸晶片為系統裸晶片，而該第四半導體裸晶片為動態隨機存取記憶體裸晶片。
  14. 如申請專利範圍第5項所述之半導體封裝組件，其中該電子部件為多層陶瓷電容，包括：一本體；以及第一及第二電極層，分別設置於該本體的兩端，使該第一及該第二電極層覆蓋該本體的側壁、局部的上表面及局部的下表面，其中該第一及該第二電極層分別電性耦接至該等第二導線的其中至少二者。
  15. 如申請專利範圍第5項所述之半導體封裝組件，其中該電子部件為晶片電容，包括：一本體；以及第一及第二電極層，分別設置於該本體的兩端，使該第一及該第二電極層露出該本體的側壁及局部的下表面，其中該第一及該第二電極層分別電性耦接至該等第二導線的其中至少二者。
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