TWI601247B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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Publication number
TWI601247B
TWI601247B TW105104430A TW105104430A TWI601247B TW I601247 B TWI601247 B TW I601247B TW 105104430 A TW105104430 A TW 105104430A TW 105104430 A TW105104430 A TW 105104430A TW I601247 B TWI601247 B TW I601247B
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Taiwan
Prior art keywords
semiconductor package
redistribution layer
semiconductor
layer structure
germanium wafer
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TW105104430A
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English (en)
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TW201633471A (zh
Inventor
林子閎
彭逸軒
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聯發科技股份有限公司
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Publication of TW201633471A publication Critical patent/TW201633471A/zh
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Publication of TWI601247B publication Critical patent/TWI601247B/zh

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    • H—ELECTRICITY
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體封裝結構
本發明涉及半導體領域，特別涉及一種具有被動元件(passive device)的半導體封裝結構。
為了確保電子產品和通信設備的小型化和多功能性，期望半導體封裝在尺寸上變小，以支持多引腳連接、高速度以及高功能性。傳統的半導體封裝一般把被動元件放置在PCB(Printed Circuit Board；印刷電路板)之上。但是，需要PCB提供額外的區域，用於被動元件安裝於其上。因此，難以降低封裝尺寸。
如此，期望創新的半導體封裝結構。
因此，本發明之主要目的即在於提供一種半導體封裝結構，可以降低半導體封裝結構之面積。
根據本發明至少一個實施例提供的一種半導體封裝結構，包含：一第一半導體封裝，包括：一第一半導體祼晶片；一第一模塑料，圍繞該第一半導體祼晶片；一第一重分佈層結構，設置在該第一模塑料的底面上，其中，該第一半導體祼晶片耦接至該第一重分佈層結構；一第二重分佈層結構，設置在該第一模塑料的頂面上；以及一被動元件，耦接至該第二重分佈層結構。
根據本發明至少一個實施例提供的一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一重分佈層結構；一第二重分佈層結構，位於該第一重分佈層結構之上；一第一模塑料，具有兩個分別與該第一重分佈層結構和該第二重分佈層結構接觸的相對表面；以及一被動元件，與該第二重分佈層結構接觸並且不與該第一模塑料接觸。
本發明實施例，由於被動元件集成於半導體封裝中，例如耦接至半導體封裝中的模塑料的頂面上的重分佈層結構或者與該重分佈層結構接觸，從而使得被動元件可以位於模塑料之邊界內而無需位於半導體封裝旁(被動元件設置在半導體封裝旁時，需要為其提供額外的區域，從而增加了半導體封裝結構的面積)，因此能夠降低半導體封裝結構的面積。
500a、500b‧‧‧半導體封裝結構
302、402、404‧‧‧半導體祼晶片
330‧‧‧被動元件
200‧‧‧基底
300‧‧‧半導體封裝
202‧‧‧祼晶片接觸面
320、306、428‧‧‧導電結構
308、328、418‧‧‧RDL結構
304、332、408、410‧‧‧連接墊
350、412‧‧‧模塑料
302b‧‧‧前表面
302a‧‧‧後表面
352、354、310、312、324、326、420、422‧‧‧表面
314、336、426‧‧‧導電線路
318、334、424‧‧‧IMD層
312、427‧‧‧阻焊層
322‧‧‧通孔
400‧‧‧DRAM封裝
414、416‧‧‧接合線
第1A圖是根據本公開一些實施例的包含半導體封裝的半導體封裝結構的剖面示意圖。
第1B圖是第1A圖的上視圖，示出了半導體封裝中的半導體祼晶片和被動元件的佈置。
第2圖是根據本公開一些實施例的包含半導體封裝以及堆疊於其上的另一半導體封裝的半導體封裝結構的剖面示意圖。
在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域中具有習知技術者應可理解，電子裝置製造商可能會用不同的名詞來稱呼同一個元件。 本說明書及後續的申請專利範圍並不以名稱的差異來作為區分元件的方式，而是以元件在功能上的差異來作為區分的準則。在通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語，故應解釋成「包含但不限定於」。以外，「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此，若文中描述一第一裝置耦接到一第二裝置，則代表該第一裝置可直接電氣連接於該第二裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝置。
本發明將參考特定實施例以及確定的圖式進行描述，但是本發明不限制於該特定實施例以及確定的圖式，並且本發明僅由申請專利範圍所限制。描述的圖式僅是原理圖並且非限制。在圖式中，出於說明目的以及非按比例繪製，誇大了某些元件的尺寸。圖式中元件的尺寸和相對尺寸不對應本發明實際中的真實尺寸。
第1A圖是根據本公開一些實施例的包含半導體封裝的半導體封裝結構500a的剖面示意圖。在一些實施例中，該半導體封裝結構500a可以為POP(Package on Package；封裝上封裝)半導體封裝結構或者SIP(System-in-Package；系統級封裝)半導體封裝結構。第1B圖是第1A圖的上視圖，示出了半導體封裝結構500a中的半導體祼晶片302和被動元件330的佈置。為了清楚地示出基底的佈置，半導體封裝結構500a中半導體祼晶片302和被動元件330在第1B圖中示出，而半導體封裝結構500a中的被動元件330下的RDL(Redistribution Layer；重分佈層或者重新佈線層)結構在第 1B圖中沒有示出。在下文中，相同的附圖標記表示相同的元件，並且出於簡潔，不重復描述相同的元件。
如第1A圖所示，半導體封裝結構500a包括：至少一個晶圓級半導體封裝，安裝於一基底200之上。在本實施例中，該晶圓級半導體封裝包括：半導體封裝300。
如第1A圖所示，基底200(例如PCB)可以由PP(polypropylene；聚丙烯)形成。需要注意的是，基底200可以是單層或複數層結構。複數個連接墊(未示出)和/或導電線路(未示出)設置在基底200的祼晶片接觸面202之上。在一個實施例中，導電線路包括：功率線路部份、信號線路部份或者接地線路部份，用於半導體封裝300的輸入/輸出(Input/Output；I/O)連接。另外，半導體封裝300可以直接安裝在導電線路之上。在一些其他實施例中，連接墊設置在祼晶片接觸面202之上，並且連接至導電線路的不同端。連接墊用於半導體封裝300直接安裝於其上。
如第1A圖所示，半導體封裝300通過接合(bonding)製程安裝在基底200的祼晶片接觸面202之上。半導體封裝300通過導電結構320安裝在基底200之上。半導體封裝300包括：半導體祼晶片302和2個RDL結構308和328。半導體祼晶片302例如可以包括邏輯祼晶片，該邏輯祼晶片包括：CPU(central processing unit；中央處理器)、GPU(Graphics Processing Unit；繪圖處理器)、DRAM(Dynamic Random Access Memory；動態隨機存取記憶體)控制器或者他們的組合。在另一實施例中，半導體祼晶片302可以為SOC 晶片，因此半導體封裝300可以包括：SOC晶片封裝。本公開的實施例不限制於此。在一些實施例中，半導體封裝300可以包括：類比處理設備封裝、數位處理設備封裝，或者另外的合適的半導體封裝。
如第1A圖所示，半導體祼晶片302通過覆晶(flip-chip)技術裝配。半導體祼晶片302的連接墊304設置在前表面302b之上，以電性連接至半導體祼晶片302的電路(未示出)。在一些實施例中，連接墊304屬於半導體祼晶片302的互連結構(未示出)的最上層金屬層。半導體祼晶片302的連接墊304與對應的導電結構306接觸，例如導電凸塊。需要注意的是，半導體封裝結構500a中集成的半導體祼晶片302的數量不限制於本實施例中公開的數量。
如第1A圖所示，半導體封裝300進一步包括：模塑料350，覆蓋以及圍繞半導體祼晶片302。模塑料350與半導體祼晶片302接觸。模塑料350具有分別接近半導體祼晶片302的前表面302b和後表面302a的相對表面352和354。模塑料350也覆蓋半導體祼晶片302的後表面302a。在一些實施例中，模塑料350可以由非導電材料形成，例如環氧樹脂、樹脂、可塑聚合物，等等。模塑料350可以在基本上為液體時應用，然後通過化學反應固化，例如在環氧樹脂或者樹脂中。在其他一些實施例中，模塑料350可以是作為能夠設置在半導體祼晶片302周圍的凝膠或者可塑固體而應用的紅外(ultraviolet；UV)或熱固化聚合物，然後通過UV或熱固化製程而固化。模塑料350可以使用模型(未示出)來固化。
如第1A圖所示，半導體封裝結構300進一步包括：2個RDL結構308和328，分別設置在半導體祼晶片302的前表面302b和後表面302a的上方。RDL結構308設置在模塑料350的表面352之上。半導體封裝300的半導體祼晶片302通過導電結構306連接至RDL結構308的表面310，例如導電凸塊或者焊膏(solder paste)。RDL結構308可以與模塑料350接觸。在一些實施例中，RDL結構308可以具有一個或複數個導電線路314，設置於一個或複數個IMD(Inter-Metal Dielectric；金屬間介電)層318中。導電線路314的連接墊部份暴露於阻焊層312的開口。但是，需要注意的是，第1A圖中所示的導電線路314的數量以及IMD層318的數量僅是示例而非本發明的限制。
如第1A圖所示，半導體封裝300進一步包括：導電結構320，設置在RDL結構308的表面312之上，該表面312遠離半導體祼晶片302。導電結構320通過暴露的阻焊層312的開口而耦接至導電線路314。另外，導電結構320通過RDL結構308自模塑料350分離。換言之，導電結構320免於與模塑料350接觸。在一些實施例中，導電結構320可以包括：諸如銅凸塊或者焊料凸塊結構等的導電凸塊結構，導電柱結構，導電線結構或者導電膠(conductive paste)結構。
如第1A圖所示，RDL結構328設置在模塑料350之上。RDL結構328的表面324(該表面324接近半導體祼晶片302)與模塑料350的相對表面354接觸。類似於RDL結構308，RDL結構328可以具有一個或複數個導電線路336，設 置在一個或複數個IMD層中334中。導電線路336的連接墊部份暴露於IMD層334的開口，該開口遠離模塑料350的相對表面354。但是，需要注意的是，第1A圖所示的導電線路336的數量以及IMD層的數量僅是示例而不是對本發明的限制。
如第1A圖所示，RDL結構328通過穿過RDL結構308和RDL結構328之間的模塑料350的通孔(via)322耦接至RDL結構308。半導體祼晶片302由通孔322圍繞。每個通孔322的兩個端分別接近RDL結構308的表面310以及RDL結構328的表面324。另外，RDL結構308的表面310和RDL結構328的表面324分別接近半導體祼晶片302。在一些實施例中，通孔322包括：由銅形成的TPV(Through Package Via；封裝通孔)。
如第1A圖所示，半導體封裝300進一步包括：一個或複數個被動元件330，安裝在RDL結構328之上並且耦接至RDL結構328。被動元件330具有兩個連接墊332，與RDL結構328的遠離半導體祼晶片302的表面326接觸。需要注意的是，被動元件330免於被模塑料350所覆蓋。另外，被動元件330免於與模塑料350接觸。在一些實施例中，被動元件330可以包括：被動元件晶片、MLCC(Multilayer Ceramic Chip Capacitor；複數層陶瓷晶片電容)設備，等等。
第1B圖示出了半導體封裝300的半導體祼晶片302和被動元件330的佈置。由於直接設置在模塑料350的頂面上的RDL結構328(第1A圖)具有為安裝於其上的被動元 件330提供重分佈(重新導向)的功能。因此，在第1B圖所示的上視圖中，被動元件330可以佈置在模塑料350的邊界內。因此，被動元件330可以無需通過外部的導電結構(例如導電結構320)而耦接至半導體祼晶片302，如第1A圖所示，該外部的導電結構設置在半導體封裝300之外(例如基底200的連接墊和/或導電線路)。
第2圖是包括半導體封裝300以及堆疊於其上的DRAM封裝400的半導體封裝結構500b的剖面示意圖。為了說明本公開的實施例，此中將DRAM封裝作為示例描述。但是，本公開的實施例不限制於任何特定應用。出於簡潔，下述實施例中，與參考第1A~1B圖已描述的元件相同或者相似的元件不再重復描述。
如第2圖所示，第1A圖中所示的半導體封裝結構500a與第2圖中所示的半導體封裝結構500b之間的一個不同在於：半導體封裝結構500b進一步包括：半導體封裝，通過接合製程堆疊於半導體封裝300之上。在本實施例中，該半導體封裝包括：記憶體封裝，例如，DRAM封裝400。公開的實施例不限制於此。在一些實施例中，堆疊在半導體封裝300之上的半導體封裝可以包括：類比處理設備封裝，數位處理設備封裝或者另外的合適的半導體封裝。DRAM封裝400通過導電結構428安裝在半導體封裝300之上。DRAM封裝400通過半導體封裝300的RDL結構328和通孔322耦接至RDL結構308。
如第2圖所示，DRAM封裝400包括：RDL結構418，至少一個半導體祼晶片(例如兩個半導體祼晶片402和 404)以及模塑料412。由於DRAM封裝400堆疊在半導體封裝300之上，所以RDL結構328設置在RDL結構308和418之間。RDL結構418具有相對的表面420和422。表面420用於半導體祼晶片安裝於其上，表面422用於導電結構428依附在其上。類似於RDL結構308和328，RDL結構418可以具有一個或複數個導電線路426，設置在一個或複數個IMD層424中。導電線路426的連接墊部份暴露於阻焊層427的開口。但是，需要注意的是，第2圖所示的導電線路426的數量和IMD層424的數量僅是示例而不是本發明的限制。
在第2圖所示的實施例中，半導體祼晶片402和404均為DRAM祼晶片。DRAM祼晶片402使用粘貼劑(未示出)安裝在RDL結構418的表面420之上。另外，DRAM祼晶片404使用粘貼劑(未示出)堆疊在DRAM祼晶片402之上。DRAM祼晶片402和404通過接合線可以耦接至RDL結構418，例如接合線414和416。如圖所示，接合線414的兩端分別連接至RDL結構418的表面420上的連接墊以及DRAM祼晶片402的連接墊408；接合線416的兩端分別連接至RDL結構418的表面420上的連接墊以及DRAM祼晶片402的連接墊410。但是，堆疊的DRAM祼晶片的數量不限制於公開的實施例。可選的，第2圖所示的兩個DRAM祼晶片402和404可以一個挨一個(side by side)地佈置。因此，DRAM祼晶片402和404可以通過粘貼劑(未示出)安裝在RDL結構418的表面420之上。
如第2圖所示，模塑料412圍繞DRAM祼晶片402 和404。另外，模塑料412與RDL結構418的表面420以及DRAM祼晶片402和404接觸。類似於模塑料350，模塑料412可以由非導電材料形成，例如環氧樹脂、樹脂、可塑聚合物，等等。
如第2圖所示，DRAM封裝400進一步包括：導電結構428，設置在RDL結構418的遠離DRAM祼晶片402和404的表面422之上。通過在阻焊層427的開口形成導電結構428，以耦接至導電線路426。另外，導電結構428通過RDL結構418與模塑料412分離。換言之，導電結構428免於接觸模塑料412。需要注意的是，RDL結構328和418之間的被動元件330被導電結構428圍繞。另外，被動元件330免於接觸DRAM封裝400。類似於導電結構320，導電結構428可以包括：諸如銅凸塊或焊料凸塊等的導電凸塊結構，導電柱結構，導電線結構或者導電膠結構。
可以對本公開的實施例進行多種變化和/或修改。例如，半導體封裝結構500b不限制於包括：SOC晶片封裝以及垂直堆疊於該SOC晶片封裝之上的記憶體封裝。在一些實施例中，半導體封裝結構500b可以包括：自SOC晶片封裝、記憶體封裝、類比處理封裝、數位處理封裝和其他適合的半導體封裝中選擇的2個堆疊的封裝。例如，第2圖所示的半導體封裝300可以為類比處理封裝，並且第2圖所示的DRAM封裝400可以由數位處理封裝替換。
實施例提供了半導體封裝結構。該半導體封裝結構包括：至少一個半導體封裝，例如，SOC封裝。該半導體封 裝包括：半導體祼晶片，圍繞該半導體祼晶片的模塑料，頂部RDL結構以及底部RDL結構。頂部和底部RDL結構分別與模塑料的頂面和底面接觸。SOC封裝進一步包括：被動元件，耦接至設置在模塑料的頂面之上的RDL結構。可選地，半導體封裝結構進一步包括：垂直堆疊於其上的另一半導體封裝，例如DRAM封裝。需要注意的是，設置在頂部RDL結構之上的被動元件免於接觸半導體封裝的模塑料以及其他的半導體封裝。
根據本公開一些實施例的半導體封裝結構具有下述優勢。直接設置在模塑料的底面上的RDL結構具有為安裝於其上的半導體祼晶片提供重分佈(重新導向)的功能。另外，直接設置在模塑料的頂面上的RDL結構具有為安裝於其上的被動元件提供重分佈(重新導向)的功能。另外，穿過模塑料並且連接至兩個RDL結構的通孔作為半導體封裝的內部導電結構。因此，被動元件可以無需外部的導電結構而耦接至半導體祼晶片，該外部的導電結構設置在半導體封裝之外(例如基底的連接墊或者導電線路)。由於縮短了的RDL繞線路徑，因此可以改善半導體封裝的訊號完整性/功率完整性(Signal Integrity/Power Integrity；SI/PI)性能。進一步，可以降低基底的面積。另外，半導體封裝結構進一步包括：直接設置在模塑料的頂面上的RDL結構，並且該半導體封裝結構可以提供集成靈活性，例如設備插入和熱解決方案。另外，使用相類似的製程來製造RDL結構可以在半導體封裝結構中提供可比較的製程性能。
以上所述僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內所作的任何修改、等同替換和改進等，均應包含在本發明的保護範圍之內。
300‧‧‧半導體封裝
302‧‧‧半導體祼晶片
330‧‧‧被動元件
332‧‧‧連接墊
350‧‧‧模塑料

Claims (26)

  1. 一種半導體封裝結構，包含：一第一半導體封裝，包括：一第一半導體祼晶片；一第一模塑料，圍繞該第一半導體祼晶片；一第一重分佈層結構，設置在該第一模塑料的底面上，其中，該第一半導體祼晶片耦接至該第一重分佈層結構；一第二重分佈層結構，設置在該第一模塑料的頂面上；以及一被動元件，耦接至該第二重分佈層結構並且不與該第一模塑料接觸。
  2. 如申請專利範圍第1項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一導電結構，設置在該第一重分佈層結構的第一表面之上，該第一重分佈層結構的第一表面遠離該第一半導體祼晶片，其中，該第一導電結構耦接至該第一重分佈層結構。
  3. 如申請專利範圍第2項所述的半導體封裝結構，其中，該被動元件設置在該第二重分佈層結構的第一表面之上，該第二重分佈層結構的第一表面遠離該第一半導體祼晶片。
  4. 如申請專利範圍第1項所述的半導體封裝結構，其中，該被動元件不被該第一模塑料覆蓋。
  5. 如申請專利範圍第3項所述的半導體封裝結構，其中，該第二重分佈層結構通過複數個第一通孔耦接至該第一重分佈層結構，該等第一通孔穿過該第一和第二重分佈層結構 之間的該第一模塑料。
  6. 如申請專利範圍第5項所述的半導體封裝結構，其中，該等第一通孔圍繞該第一半導體祼晶片。
  7. 如申請專利範圍第5項所述的半導體封裝結構，其中，該等第一通孔中的每一個的兩端分別接近該第一重分佈層結構的第二表面以及該第二重分佈層結構的第二表面，其中該第一重分佈層結構的第二表面以及該第二重分佈層結構的第二表面均接近該第一半導體祼晶片。
  8. 如申請專利範圍第5項所述的半導體封裝結構，其中，進一步包括：一第二半導體封裝，堆疊在該第一半導體封裝之上，並且包括：一第三重分佈層結構；一第二半導體祼晶片，耦接至該第三重分佈層結構；以及一第二模塑料，圍繞該第二半導體祼晶片，並且該第二模塑料與該第三重分佈層結構以及該第二半導體祼晶片均接觸。
  9. 如申請專利範圍第8項所述的半導體封裝結構，其中，該第二重分佈層結構設置在該第一重分佈層結構和該第三重分佈層結構之間。
  10. 如申請專利範圍第8項所述的半導體封裝結構，其中，該第二半導體封裝進一步包括：複數個第二導電結構，設置在該第三重分佈層結構中遠離該第二半導體祼晶片的表面之上，其中，該等第二導電結構耦接至該第三重分佈層結 構。
  11. 如申請專利範圍第10項所述的半導體封裝結構，其中，該等第二導電結構圍繞該被動元件。
  12. 如申請專利範圍第8項所述的半導體封裝結構，其中，該被動元件與該第二半導體封裝不接觸。
  13. 如申請專利範圍第8項所述的半導體封裝結構，其中，該第二半導體封裝通過該第二重分佈層結構以及該等第一通孔耦接至該第一重分佈層結構。
  14. 如申請專利範圍第8項所述的半導體封裝結構，其中，該第一半導體祼晶片為片上系統祼晶片，以及該第二半導體祼晶片為動態隨機存取記憶體祼晶片；並且，該第一半導體封裝為片上系統封裝，以及該第二半導體封裝為動態隨機存取記憶體封裝。
  15. 一種半導體封裝結構，包括：一第一半導體封裝，包括：一第一重分佈層結構；一第二重分佈層結構，位於該第一重分佈層結構之上；一第一模塑料，具有兩個分別與該第一重分佈層結構和該第二重分佈層結構接觸的相對表面；以及一被動元件，與該第二重分佈層結構接觸並且不與該第一模塑料接觸。
  16. 如申請專利範圍第15項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：複數個第一通孔，穿過該第一和第二重分佈層結構之間的該第一模塑料。
  17. 如申請專利範圍第16項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一半導體祼晶片，耦接至該第一重分佈層結構；該第一模塑料以及該等第一通孔圍繞該第一半導體祼晶片。
  18. 如申請專利範圍第17項所述的半導體封裝結構，其中，該第一半導體祼晶片耦接至該第一重分佈層結構中接近該第一半導體祼晶片的表面。
  19. 如申請專利範圍第17項所述的半導體封裝結構，其中，該被動元件與該第二重分佈層結構中遠離該第一半導體祼晶片的表面接觸。
  20. 如申請專利範圍第17項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一導電結構，設置在該第一重分佈層結構中遠離該第一半導體祼晶片的表面之上，其中，該第一導電結構耦接至該第一重分佈層結構。
  21. 如申請專利範圍第15項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一導電結構，與該第一重分佈層結構接觸以及不與該第一模塑料接觸。
  22. 如申請專利範圍第21項所述的半導體封裝結構，其中，該第一半導體封裝進一步包括：一第一半導體祼晶片，耦接至該第一重分佈層結構，並且由該第一模塑料以及複數個第一通孔圍繞，其中，該等第一通孔穿過該第一和第二重分佈層結構之間的該第一模塑料。
  23. 如申請專利範圍第16或22項所述的半導體封裝結構，其中，該等第一通孔耦接至該第一和第二重分佈層結構。
  24. 如申請專利範圍第16或21項所述的半導體封裝結構，進一步包括：一第二半導體封裝，堆疊在該第一半導體封裝之上，並且包括：一第三重分佈層結構；一第二半導體祼晶片，耦接至該第二重分佈層結構；一第二模塑料，圍繞該第二半導體祼晶片，並且與該第三重分佈層結構以及該第二半導體祼晶片接觸；以及複數個第二導電結構，設置在該第三重分佈層結構中遠離該第二半導體祼晶片的表面之上，其中，該等第二導電結構耦接至該第三重分佈層結構。
  25. 如申請專利範圍第24項所述的半導體封裝結構，其中，該第二重分佈層結構設置在該第一和第三重分佈層結構之間。
  26. 如申請專利範圍第24項所述的半導體封裝結構，其中，該等第二導電結構圍繞該被動元件，並且該被動元件不與該第二半導體封裝接觸。
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