TW201411746A - 於扇出晶圓級封裝形成當作垂直互連之導線柱的半導體裝置及方法 - Google Patents

於扇出晶圓級封裝形成當作垂直互連之導線柱的半導體裝置及方法 Download PDF

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TW201411746A
TW201411746A TW102122681A TW102122681A TW201411746A TW 201411746 A TW201411746 A TW 201411746A TW 102122681 A TW102122681 A TW 102122681A TW 102122681 A TW102122681 A TW 102122681A TW 201411746 A TW201411746 A TW 201411746A
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substrate
semiconductor
encapsulant
semiconductor die
conductive
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TW102122681A
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TWI594343B (zh
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Pandi C Marimuthu
Sheila Marie L Alvarez
Yaojian Lin
Jose A Caparas
Yang Kern Jonathan Tan
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Stats Chippac Ltd
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Abstract

半導體裝置具有基板和配置於基板之第一表面上的半導體晶粒。導線柱附接於基板的第一表面。導線柱包括基底部分和柄部分。接合墊形成於基板的第二表面上。包封物沉積於基板、半導體晶粒、導線柱上。部分的包封物是以雷射直接燒蝕(LDA)而移除以暴露導線柱。部分的包封物是以LDA而移除以暴露基板。互連結構形成於包封物上並且電連接到導線柱和半導體晶粒。凸塊形成於互連結構上。半導體封裝配置於包封物上並且電連接到基板。離散半導體裝置配置於包封物上並且電連接到基板。

Description

於扇出晶圓級封裝形成當作垂直互連之導線柱的半導體裝置及方法 【主張國內優先權】
本申請案主張2012年9月14日申請的美國臨時申請案第61/701,419號的權益，該案之全文以引用方式併入本文中。
本發明一般關於半導體裝置，更特別的是關於在扇出晶圓級封裝(fan-out wafer level package，Fo-WLP)形成當作垂直互連之導線柱的半導體裝置及方法。
半導體裝置乃通常發現於現代電子產品中。半導體裝置的電構件數目和密度多所變化。離散半導體裝置一般包含一種電構件，譬如發光二極體(light emitting diode，LED)、小訊號電晶體、電阻器、電容器、電感器、功率金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor，MOSFET)。積體半導體裝置典型包含數百到數百萬個電構件。積體半導體裝置的範例包括微控制器、微處理器、電荷耦合裝置(charged-coupled device，CCD)、太陽能電池、數位微鏡裝置(digital micro-mirror device，DMD)。
半導體裝置執行廣泛的功能，例如訊號處理、高速計算、傳 送和接收電磁訊號、控制電子裝置、將陽光轉換為電力、產生電視顯示器的視覺投影。半導體裝置乃發現於娛樂、通訊、功率轉換、網路、電腦、消費性產品等領域。半導體裝置也發現於軍事用途、航空、汽車、工業控制器、辦公室設備。
半導體裝置乃利用半導體材料的電性質。半導體材料的結構允許其導電度藉由施加電場或基極電流或者透過摻雜過程來操控。摻雜將雜質引入半導體材料裡以操控和控制半導體裝置的導電度。
半導體裝置包含主動和被動的電結構。主動結構包括雙極和場效電晶體，其控制電流的流動。藉由變化摻雜的程度和施加的電場或基極電流，電晶體則促進或限制電流的流動。被動結構包括電阻器、電容器、電感器，其產生執行多樣電功能所需的電壓和電流關係。被動和主動結構乃電連接以形成電路，其能使半導體裝置執行高速操作和其他有用的功能。
半導體裝置一般使用二複雜的製程來製造，亦即前端製造和後端製造，其各可能涉及數百個步驟。前端製造涉及在半導體晶圓的表面上形成多個晶粒。每個半導體晶粒典型是相同的，並且包含電連接主動和被動構件所形成的電路。後端製造涉及從完工的晶圓單離出獨立的半導體晶粒，並且封裝晶粒以提供結構支持和環境隔離。在此使用的「半導體晶粒」(semiconductor die)一詞是指該詞的單數和複數形式，據此可以是指單一個半導體裝置和多個半導體裝置。
半導體製造的一個目標是要製造更小的半導體裝置。更小的裝置典型消耗較少的電力、具有較高的性能、可以更有效率的製造。附帶而言，較小的半導體裝置具有較小的佔地面積，這對於較小的末端產品來 說是想要的。較小的半導體晶粒尺寸可以由前端過程的改善而達成，而導致半導體晶粒具有較小的、更高密度的主動和被動構件。藉由改善電互連和封裝材料，後端過程可以導致半導體裝置封裝具有較小的佔地面積。
半導體封裝通常使用導電柱或通孔來做為穿過半導體晶粒周圍之包封物的垂直互連，其譬如在頂側互連結構和底側互連結構之間。通孔典型乃形成穿過包封物而被填充了導電材料。導電通孔的形成很花時間並且涉及昂貴的設備。導電通孔可能從頂側互連結構和底側互連結構脫層，導致製造的缺陷或潛在的缺陷。
扇出晶圓級封裝中需要簡單和有成本效益的垂直互連結構。據此，於一實施例，本發明是製作半導體裝置的方法，其包括以下步驟：提供基板；將半導體晶粒配置於基板的第一表面上；將導線柱附接於基板的第一表面；將包封物沉積於基板、半導體晶粒、導線柱上；以及將互連結構形成於包封物上並且電連接於導線柱。
於另一實施例，本發明是製作半導體裝置的方法，其包括以下步驟：提供基板；將半導體晶粒配置於基板上；將導線柱附接於基板；以及將包封物沉積於基板、半導體晶粒、導線柱上。
於另一實施例，本發明是半導體裝置，其包括基板和配置於基板上的半導體晶粒。導線柱附接於基板。包封物沉積於基板、半導體晶粒、導線柱上。互連結構形成於包封物上。
於另一實施例，本發明是半導體裝置，其包括基板和配置於基板上的半導體晶粒。導線柱附接於基板。包封物沉積於基板、半導體晶 粒、導線柱上。
50‧‧‧電子裝置
52‧‧‧晶片載體基板或印刷電路板(PCB)
54‧‧‧導電訊號線路
56‧‧‧接合線封裝
58‧‧‧覆晶
60‧‧‧球柵陣列(BGA)
62‧‧‧凸塊晶片載體(BCC)
64‧‧‧雙列直插式封裝(DIP)
66‧‧‧地柵陣列(LGA)
68‧‧‧多晶片模組(MCM)
70‧‧‧四面扁平無導線封裝(QFN)
72‧‧‧四面扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中間載體
80‧‧‧導線
82‧‧‧接合線
84‧‧‧包封物
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧底填物或環氧樹脂黏著材料
94‧‧‧接合線
96、98‧‧‧接觸墊
100‧‧‧模製化合物或包封物
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧載體
108‧‧‧有效區域
110、112‧‧‧凸塊
114‧‧‧訊號線
116‧‧‧模製化合物或包封物
120‧‧‧半導體晶圓
122‧‧‧基板材料
124‧‧‧半導體晶粒或構件
126‧‧‧非有效之晶粒晶圓間的區域或鋸道
128‧‧‧背面
130‧‧‧有效表面
132‧‧‧導電層
134‧‧‧鋸片或雷射切割工具
140‧‧‧中介基版
142‧‧‧絕緣或介電層
144‧‧‧垂直互連導電通孔
146、148‧‧‧導電層或再佈線層(RDL)
150‧‧‧導線柱
150a‧‧‧基底部分
150b‧‧‧柄
160‧‧‧載體或暫時基板
162‧‧‧介面層或雙面膠帶
164‧‧‧包封物或模製化合物
166‧‧‧雷射
170‧‧‧增層互連結構
172‧‧‧導電層或再佈線層
174‧‧‧絕緣或鈍化層
178‧‧‧研磨器
180‧‧‧雷射
182‧‧‧球或凸塊
184‧‧‧扇出晶圓級封裝
190‧‧‧中介基版
192‧‧‧絕緣或介電層
194‧‧‧垂直互連導電通孔
196、198‧‧‧導電層或再佈線層
200‧‧‧導電層
202‧‧‧導線柱
202a‧‧‧基底部分
202b‧‧‧柄
210‧‧‧載體或暫時基板
212‧‧‧介面層或雙面膠帶
214‧‧‧包封物或模製化合物
216‧‧‧雷射
220‧‧‧增層互連結構
222‧‧‧導電層或再佈線層
224‧‧‧絕緣或鈍化層
228‧‧‧研磨器
230‧‧‧球或凸塊
232‧‧‧扇出晶圓級封裝
240‧‧‧半導體封裝
242‧‧‧半導體晶粒或構件
244‧‧‧背面
246‧‧‧有效表面
250‧‧‧基板
252‧‧‧導電線路
254‧‧‧接合線
256‧‧‧接觸墊
258‧‧‧包封物
260‧‧‧凸塊
262‧‧‧封裝上封裝(PoP)
270‧‧‧半導體封裝
272‧‧‧半導體晶粒或構件
274‧‧‧背面
276‧‧‧有效表面
280‧‧‧基板
282‧‧‧導電線路
284‧‧‧接合線
286‧‧‧接觸墊
288‧‧‧包封物
290‧‧‧凸塊
292‧‧‧系統級封裝(SiP)
294‧‧‧半導體裝置
298‧‧‧導電膏
圖1示範印刷電路板(printed circuit board，PCB)，其表面上安裝了不同類型的封裝；圖2a~2c示範安裝於PCB之代表性半導體封裝的進一步細節；圖3a~3c示範半導體晶圓，其具有由鋸道所分開的多個半導體晶粒；圖4a~4k示範於扇出晶圓級封裝中形成導線柱而做為垂直互連的過程；圖5示範扇出晶圓級封裝中之半導體晶粒的相反指向；圖6a~6i示範於扇出晶圓級封裝中形成導線柱而做為垂直互連的另一過程；圖7a~7b示範扇出晶圓級封裝之封裝上封裝(package-on-package，PoP)安排，其具有導線柱來做為垂直互連；以及圖8a~8b示範扇出晶圓級封裝之系統級封裝(system-in-package，SiP)安排，其具有導線柱來做為垂直互連。
於下面參考圖式的敘述，本發明乃描述於一或更多個實施例，其中圖式的相同數字代表相同或類似的元件。雖然本發明就達成本發明目的之最佳模式來敘述，不過熟於此技術者將體會本發明打算涵蓋可以包括在本發明之精神和範圍裡的替代方案、修改和等同者，就如底下揭示和圖式支持之所附申請專利範圍及其等同者所界定的。
半導體裝置一般使用二複雜的製程來製造：前端製造和後端 製造。前端製造涉及在半導體晶圓的表面上形成多個晶粒。晶圓上的每個晶粒包含主動和被動的電構件，其電連接以形成功能性電路。例如電晶體和二極體的主動電構件具有控制電流流動的能力。例如電容器、電感器、電阻器的被動電構件則產生執行電路功能所需的電壓和電流關係。
藉由一系列的過程步驟，包括摻雜、沉積、光微影術、蝕刻、平坦化，而將被動和主動構件形成於半導體晶圓的表面上。摻雜藉由例如離子佈植或熱擴散的技術而將雜質引入半導體材料裡。摻雜過程藉由動態改變半導體材料導電度以回應於電場或基極電流，而修改了主動裝置中之半導體材料的導電度。電晶體包含變化摻雜類型和程度的多個區域，其視需要來安排而在施加電場或基極電流時能使電晶體促進或限制電流的流動。
主動和被動構件是由不同電性質的材料層所形成。諸層可以由各式各樣的沉積技術所形成，該等技術部分是由要沉積的材料類型所決定。舉例而言，薄膜沉積可以涉及化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、電解電鍍、無電電鍍等過程。每層一般加以圖案化以形成多個部分的主動構件、被動構件或構件之間的電連接。
後端製造是指將完工的晶圓切割或單離化成為獨立的半導體晶粒，然後為了結構支持和環境隔離而封裝半導體晶粒。為了單離化半導體晶粒，晶圓沿著稱為鋸道或劃線之晶圓的非功能性區域而刻劃並斷開。晶圓使用雷射切割工具或鋸片來單離化。在單離化之後，獨立的半導體晶粒安裝到封裝基板，該基板包括針腳或接觸墊以與其他的系統構件互 連。形成於半導體晶粒上的接觸墊然後連接到封裝裡的接觸墊。電連接可以由焊料凸塊、柱凸塊、導電膏或打線接合所做成。包封物或其他模製材料沉積於封裝上以提供實體支持和電隔離。完工的封裝然後插入電系統裡，而讓其他的系統構件可得到半導體裝置的功能。
圖1示範電子裝置50，其具有晶片載體基板或印刷電路板(PCB)52，而表面上安裝了多個半導體封裝。電子裝置50可以具有一種半導體封裝或多種半導體封裝，此視用途而定。為了示範，不同類型的半導體封裝乃顯示於圖1。
電子裝置50可以是自立式系統，其使用半導體封裝來執行一或更多個電功能。替代而言，電子裝置50可以是更大系統的次構件。舉例而言，電子裝置50可以是行動電話、個人數位助理(personal digital assistant，PDA)、數位攝影機(digital video camera，DVC)或其他電子通訊裝置的一部分。替代而言，電子裝置50可以是繪圖卡、網路介面卡或其他訊號處理卡而可以插入電腦裡。半導體封裝可以包括微處理器、記憶體、特用積體電路(application specific integrated circuit，ASIC)、邏輯電路、類比電路、RF電路、離散裝置或其他的半導體晶粒或電構件。迷你化和減重對於要被市場接受的產品來說是基本的。半導體裝置之間的距離必須縮減以達成較高的密度。
於圖1，PCB 52提供一般的基板以用於安裝在PCB上之半導體封裝的結構支持和電互連。導電訊號線路54使用蒸鍍、電解電鍍、無電電鍍、網版印刷或其他適合的金屬沉積過程而形成於PCB 52的表面上或諸層裡。訊號線路54提供半導體封裝、安裝的構件、其他的外部系統構件 每一者之間的電通訊。線路54也提供電力和接地連接給每個半導體封裝。
於某些實施例，半導體裝置具有二個封裝層級。第一級封裝是用於將半導體晶粒機械和電附接到中間載體的技術。第二級封裝涉及將中間載體機械和電附接到PCB。於其他的實施例，半導體裝置可以僅具有第一級封裝，其中晶粒乃直接機械和電安裝到PCB。
為了示範，幾種第一級封裝，包括接合線封裝56和覆晶58，乃顯示在PCB 52上。附帶而言，幾種第二級封裝，包括球柵陣列(ball grid array，BGA)60、凸塊晶片載體(bump chip carrier，BCC)62、雙列直插式封裝(dual in-line package，DIP)64、地柵陣列(land grid array，LGA)66、多晶片模組(multi-chip module，MCM)68、四面扁平無導線封裝(quad flat non-leaded package，QFN)70、四面扁平封裝72，乃顯示安裝在PCB 52上。視系統需求而定，以第一和第二級封裝方式的任何組合所組構之半導體封裝的任何組合以及其他電子構件都可以連接到PCB 52。於某些實施例，電子裝置50包括單一附接的半導體封裝，而其他的實施例需要多個互連的封裝。藉由將一或更多個半導體封裝組合於單一基板上，製造商可以把預製的構件併入電子裝置和系統裡。因為半導體封裝包括複雜的功能性，所以電子裝置可以使用較不昂貴的構件和流線化的製程來製造。所得的裝置不太可能失效並且製造上較不昂貴，而導致消費者有較低的成本。
圖2a~2c顯示範例性半導體封裝。圖2a示範安裝在PCB 52上之DIP 64的進一步細節。半導體晶粒74包括有效區域，其包含類比或數位電路而實施成為晶粒裡所形成的主動裝置、被動裝置、導電層、介電層，並且根據晶粒的電設計而電互連。舉例而言，電路可以包括一或更多個電 晶體、二極體、電感器、電容器、電阻器和其他的電路元件而形成在半導體晶粒74的有效區域裡。接觸墊76是一或更多層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接到半導體晶粒74裡所形成的電路元件。於DIP 64的組裝期間，半導體晶粒74使用金一矽共晶層或黏著材料(例如熱環氧樹脂或環氧樹脂)而安裝到中間載體78。封裝體包括絕緣性封裝材料，例如聚合物或陶瓷。導線80和接合線82提供半導體晶粒74和PCB 52之間的電互連。包封物84沉積於封裝上以用於環境保護，其避免溼氣和顆粒進入封裝而污染了半導體晶粒74或接合線82。
圖2b示範安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88使用底填物或環氧樹脂黏著材料92而安裝於載體90上。接合線94提供接觸墊96和98之間的第一級封裝互連。模製化合物或包封物100沉積於半導體晶粒88和接合線94上以提供用於裝置的實體支持和電隔離。接觸墊102使用適合的金屬沉積過程(例如電解電鍍或無電電鍍)而形成於PCB 52的表面上以避免氧化。接觸墊102電連接到PCB 52中的一或更多條導電訊號線路54。凸塊104則形成在BCC 62的接觸墊98和PCB 52的接觸墊102之間。
於圖2c，半導體晶粒58是以覆晶方式第一級封裝而面朝下的安裝到中間載體106。半導體晶粒58的有效區域108包含類比或數位電路，其實施成為根據晶粒的電設計而形成的主動裝置、被動裝置、導電層、介電層。舉例而言，電路在有效區域108裡可以包括一或更多個電晶體、二極體、電感器、電容器、電阻器和其他電路元件。半導體晶粒58透過凸塊110而電和機械連接到載體106。
BGA 60使用凸塊112而以BGA方式第二級封裝來電和機械連接到PCB 52。半導體晶粒58透過凸塊110、訊號線114、凸塊112而電連接到PCB 52中的導電訊號線路54。模製化合物或包封物116沉積於半導體晶粒58和載體106上以提供用於裝置的實體支持和電隔離。覆晶半導體裝置提供從半導體晶粒58上的主動裝置到PCB 52上的導線之短的導電路徑，以便減少訊號傳遞距離、降低電容以及改善整體電路性能。於另一實施例，半導體晶粒58可以使用覆晶方式第一級封裝而無中間載體106來直接機械和電連接到PCB 52。
圖3a顯示半導體晶圓120，其具有基板材料122，例如矽、鍺、砷化鎵、磷化銦或碳化矽以用於結構支持。多個半導體晶粒或構件124形成在晶圓120上而由非有效之晶粒晶圓間的區域或鋸道126所分開，如上所述。鋸道126提供切割區域以將半導體晶圓120單離化成為獨立的半導體晶粒124。
圖3b顯示部分之半導體晶圓120的截面圖。每個半導體晶粒124具有背面128和有效表面130，有效表面130包含類比或數位電路，其實施成為晶粒裡所形成的主動裝置、被動裝置、導電層、介電層，並且根據晶粒的電設計和功能而電互連。舉例而言，電路可以包括形成於有效表面130裡的一或更多個電晶體、二極體和其他電路元件以實施類比電路或數位電路，例如數位訊號處理器(digital signal processor，DSP)、ASIC、記憶體或其他的訊號處理電路。半導體晶粒124也可以包含積體被動裝置(integrated passive device，IPD)，例如電感器、電容器、電阻器以用於RF訊號處理。於一實施例，半導體晶粒124是球柵陣列(BGA)型裝置。
導電層132使用PVD、CVD、電解電鍍、無電電鍍過程或其他適合的金屬沉積過程而形成於有效表面130上。導電層132可以是一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層132操作成接觸墊而電連接到有效表面130上的電路。導電層132可以形成接觸墊，其配置成邊靠邊而與半導體晶粒124的邊緣有第一距離，如圖3b所示。替代而言，導電層132可以形成接觸墊，其偏移成多列，致使第一列的接觸墊乃配置成與晶粒的邊緣有第一距離，並且與第一列交錯之第二列的接觸墊乃配置成與晶粒的邊緣有第二距離。
於圖3c，半導體晶圓120使用鋸片或雷射切割工具134而透過鋸道126單離化成為獨立的半導體晶粒124。
圖4a~4k相關於圖1和2a~2c來示範在扇出晶圓級封裝的基板和增層互連結構(build-up interconnect)之間形成導線柱而做為垂直互連的過程。圖4a顯示中介基版140，其包括一或更多個層合的聚四氟乙烯預浸物(prepreg)、FR-4、FR-1、CEM-1或CEM-3而具有酚棉紙、環氧樹脂、樹脂、編織玻璃、毛玻璃、聚酯和其他強化纖維或織物的組合。替代而言，基板140包含一或更多個絕緣或介電層142。
多個通孔使用雷射鑽孔、機械鑽孔或深反應性離子蝕刻(deep reactive ion etching，DRIE)而形成穿過基板140。通孔使用電解電鍍、無電電鍍過程或其他適合的沉積過程而填充了Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)或其他適合的導電材料，以形成Z方向的垂直互連導電通孔144。
導電層或再佈線層(redistribution layer，RDL)146使用例如印 刷、PVD、CVD、濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成於基板140的第一表面和導電通孔144上。導電層146包括一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層146電連接於導電通孔144。
導電層或再佈線層148使用例如印刷、PVD、CVD、濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成基板140相對於第一表面的第二表面和導電通孔144上。導電層148包括一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層148電連接於導電通孔144和導電層146。於另一實施例，在形成導電層146和/或導電層148之後，導電通孔144才形成穿過基板140。
所得的中介基版140根據半導體晶粒124的電功能而經由導電層146、148和導電通孔144來提供跨越基板的垂直和側向電互連。根據半導體晶粒124的設計和功能，部分的導電層146、148和導電通孔144是電相通或電隔離的。
基板140也可以是多層的可撓性層合物、陶瓷、銅箔、玻璃或半導體晶圓，其所包括的有效表面包含一或更多個電晶體、二極體和其他電路元件以實施類比電路或數位電路。
於圖4b，來自圖3c的半導體晶粒124舉例而言使用拾放操作而讓有效表面130指向基板以安裝於中介基版140。半導體晶粒124以晶粒附接黏著劑(例如環氧樹脂)而固定於基板140。半導體晶粒124的導電層132電連接於基板140的導電層146。圖4c顯示半導體晶粒124安裝於基板140。
於圖4d，多個導線柱150藉由壓縮接合、針腳接合或呈自由空氣球(free air ball，FAB)或圈環形式的球接合而附接於基板140。導線柱150壓縮接觸著導電層146，此顯示為基底部分150a。柄150b可以切成適當的長度，譬如250~500微米(μm)。導線柱150提供Z方向的垂直互連結構。
圖4e顯示載體或暫時基板160，其包含犧牲性基底材料，例如矽、聚合物、氧化鈹、玻璃或其他適合的低成本、堅固材料以用於結構支持。介面層或雙面膠帶162形成於載體160上而做為暫時的黏著接合膜、蝕刻停止層或熱釋放層。來自圖4d之基板、半導體晶粒和導線柱的組件翻轉過來並且安裝於載體160和介面層162。導線柱150可以等高於半導體晶粒124或較矮於半導體晶粒，以避免在安裝於載體160期間使導線柱彎曲。導線柱150也可以高於半導體晶粒124。導線柱150具有足夠的直徑以於後續的製程期間維持堅固和穩定。
於圖4f，包封物或模製化合物164使用糊膏印刷、壓縮模製、轉移模製、液態包封物模製、真空層合、旋塗或其他適合的施加器而沉積於載體160上和基板140、半導體晶粒124、導線柱150周圍。包封物164可以是聚合性複合材料，例如具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或具有適當填料的聚合物。包封物164是非導電的並且環境上保護半導體裝置免於外部元件和污染物。
於圖4g，載體160和介面層162藉由化學蝕刻、機械剝除、化學機械平坦化(chemical mechanical planarization，CMP)、機械研磨、熱烘烤、UV光、雷射掃描或溼式脫除而移除。將基板、半導體晶粒和導線柱的組件翻轉過來。
部分的包封物164使用雷射166而以淺深度的雷射直接燒蝕(laser direct ablation，LDA)而移除以暴露導線柱150的柄150b。替代而言，部分的包封物164是透過圖案化光阻層而以蝕刻過程來移除以暴露導線柱150。如果導線柱因為是等高或高於半導體晶粒124而已經暴露，則可以不須要再暴露導線柱150。
於圖4h，增層互連結構170形成於包封物164和半導體晶粒124上。增層互連結構170包括導電層或再佈線層172，其使用例如濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成。導電層172可以是一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。一部分的導電層172延伸到包封物164暴露導線柱150的移除部分裡以電連接於導線柱。其他部分的導電層172則可以是電相通或電隔離的，此視半導體晶粒124的設計和功能而定。
增層互連結構170進一步包括絕緣或鈍化層174，其使用PVD、CVD、印刷、旋塗、噴塗、燒結或熱氧化而形成於包封物164和半導體晶粒124上和導電層172周圍以用於電隔離。絕緣層174包含一或更多層的二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化鉭(Ta2O5)、氧化鋁(Al2O3)或其他具有類似絕緣和結構性質的材料。
於圖4i，包封物164相對於互連結構170的部分則使用研磨器178而經歷研磨操作，以將包封物的表面加以平坦化和減少厚度。也可以使用化學蝕刻或CMP過程以移除包封物164之研磨操作和平坦化所導致的機械損傷。減少厚度的包封物164仍維持著覆蓋基板140以保護導電層148。
於圖4j，部分的包封物164使用雷射180而以淺深度LDA來移除，以暴露基板140的導電層148而供電互連於其他的半導體裝置，如於圖7a~7b和圖8a~8b所討論。
於圖4k，導電凸塊材料使用蒸鍍、電解電鍍、無電電鍍、球滴或網版印刷過程而沉積於導電層172上。凸塊材料可以是Al、Sn、Ni、Au、Ag、鉛(Pb)、Bi、Cu、焊料及其組合，而可選用助焊溶液。舉例而言，凸塊材料可以是共晶Sn/Pb、高鉛焊料或無鉛焊料。凸塊材料使用適合的附接或接合過程而接合於導電層172。於一實施例，凸塊材料藉由將材料加熱到其熔點之上而重熔以形成球或凸塊182。於某些應用，凸塊182重熔二次以改善對導電層172的電接觸。於一實施例，凸塊182形成於具有潤溼層、阻障層、黏著層的UBM上。凸塊也可以壓縮接合或熱壓縮接合於導電層172。凸塊182代表一種可以形成於導電層172上的互連結構。互連結構也可以使用接合線、導電膏、柱凸塊、微凸塊或其他的電互連。
扇出晶圓級封裝184使用導線柱150來做為基板140和增層互連結構170之間的垂直電互連。導線柱150簡化了製程以降低成本和減少扇出晶圓級封裝之垂直互連結構中的脫層問題。
圖5顯示的實施例乃使半導體晶粒124的背面128安裝於中介基版140。如果須要的話，部分的包封物164藉由LDA而移除以暴露導電層132，其類似於圖4g。部分的導電層172延伸到包封物164暴露半導體晶粒124之導電層132的移除部分裡以電連接於半導體晶粒，其類似於圖4h。
圖6a~6i相關於圖1和2a~2c來示範在扇出晶圓級封裝的基 板和增層互連結構之間形成導線柱而做為垂直互連的另一過程。圖6a顯示中介基版190，其包括一或更多個層合的聚四氟乙烯預浸物、FR-4、FR-1、CEM-1或CEM-3而具有酚棉紙、環氧樹脂、樹脂、編織玻璃、毛玻璃、聚酯和其他強化纖維或織物的組合。替代而言，基板190包含一或更多個絕緣或介電層192。
多個通孔使用雷射鑽孔、機械鑽孔或DRIE而形成穿過基板190。通孔使用電解電鍍、無電電鍍過程或其他適合的沉積過程而填充了Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他適合的導電材料，以形成Z方向的垂直互連導電通孔194。
導電層或再佈線層196使用例如印刷、PVD、CVD、濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成於基板190的第一表面和導電通孔194上。導電層196包括一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層196電連接於導電通孔194。
導電層或再佈線層198使用例如印刷、PVD、CVD、濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成於基板190相對於第一表面的第二表面和導電通孔194上。導電層198包括一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。導電層198電連接於導電通孔194和導電層196。於另一實施例，在形成導電層196和/或導電層198之後，導電通孔194才形成穿過基板190。
導電層200使用例如印刷、PVD、CVD、濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成於導電層198上並且在半導體晶粒124的安裝位置外。導電層200包括一或更多層的Al、Cu、Sn、Ni、Au、 Ag或其他適合的導電材料。導電層200操作成為接合墊，其電連接於導電層198和導電通孔194。
所得的中介基版190根據半導體晶粒124的電功能而經由導電層196、198和導電通孔194來提供跨越基板的垂直和側向電互連。根據半導體晶粒124的設計和功能，部分的導電層196、198和導電通孔194是電相通或電隔離的。
基板190也可以是多層的可撓性層合物、陶瓷、銅箔、玻璃或半導體晶圓，其所包括的有效表面包含一或更多個電晶體、二極體和其他電路元件以實施類比電路或數位電路。
來自圖3c的半導體晶粒124舉例而言使用拾放操作而讓背面128朝向基板以安裝於中介基版190。半導體晶粒124是以晶粒附接黏著劑(例如環氧樹脂)而固定於基板190。圖6b顯示半導體晶粒124安裝於基板190。
於圖6c，多個導線柱202藉由壓縮接合、針腳接合或呈FAB或圈環形式的球接合而附接於基板190。導線柱202壓縮接觸著導電層196，此顯示為基底部分202a。柄202b可以切成適當的長度，譬如250~500微米。導線柱202提供Z方向的垂直互連結構。
圖6d顯示載體或暫時基板210，其包含犧牲性基底材料，例如矽、聚合物、氧化鈹、玻璃或其他適合的低成本、堅固材料以用於結構支持。介面層或雙面膠帶212形成於載體210上而做為暫時的黏著接合膜、蝕刻停止層或熱釋放層。來自圖6c之基板、半導體晶粒和導線柱的組件翻轉過來並且安裝於載體210和介面層212。導線柱202可以等高於半導 體晶粒124或較矮於半導體晶粒，以避免在安裝於載體210期間使導線柱彎曲。導線柱202也可以高於半導體晶粒124。導線柱202具有足夠的直徑以於後續的製程期間維持堅固和穩定。
於圖6e，包封物或模製化合物214使用糊膏印刷、壓縮模製、轉移模製、液態包封物模製、真空層合、旋塗或其他適合的施加器而沉積於載體210上和基板190、半導體晶粒124、導線柱202周圍。包封物214可以是聚合性複合材料，例如具有填料的環氧樹脂、具有填料的環氧丙烯酸酯或具有適當填料的聚合物。包封物214是非導電的並且環境上保護半導體裝置免於外部元件和污染物。
於圖6f，載體210和介面層212藉由化學蝕刻、機械剝除、CMP、機械研磨、熱烘烤、UV光、雷射掃描或溼式脫除而移除。將基板、半導體晶粒和導線柱的組件翻轉過來。
部分的包封物214使用雷射216而以淺深度LDA來移除以暴露導線柱202的柄202b。替代而言，部分的包封物214是透過圖案化光阻層而以蝕刻過程來移除以暴露導線柱202。如果導線柱因為是等高或高於半導體晶粒124而已經暴露，則可以不須要再暴露導線柱202。如果須要的話，部分的包封物214也使用雷射216而以淺深度LDA來移除以暴露半導體晶粒124的導電層132。
於圖6g，增層互連結構220形成於包封物214和半導體晶粒124上。增層互連結構220包括導電層或再佈線層222，其使用例如濺鍍、電解電鍍、無電電鍍的圖案化和金屬沉積過程而形成。導電層222可以是一或更多層的Al、Cu、Sn、Ni、Au、Ag或其他適合的導電材料。一部分的 導電層222延伸到包封物214暴露導線柱202的移除部分裡以電連接於導線柱。另一部分的導電層222電連接於半導體晶粒124的導電層132。其他部分的導電層222則可以是電相通或電隔離的，此視半導體晶粒124的設計和功能而定。
增層互連結構220進一步包括絕緣或鈍化層224，其使用PVD、CVD、印刷、旋塗、噴塗、燒結或熱氧化而形成於包封物214和半導體晶粒124上而在導電層222周圍以用於電隔離。絕緣層224包含一或更多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3或其他具有類似絕緣和結構性質的材料。
於圖6h，包封物214相對於互連結構220的部分則使用研磨器228而經歷研磨操作，以將包封物的表面加以平坦化、減少厚度、暴露導電層200。也可以使用化學蝕刻或CMP過程以移除包封物214之研磨操作和平坦化所導致的機械損傷。減少厚度的包封物214仍維持覆蓋著基板190以保護導電層198。
於圖6i，導電凸塊材料使用蒸鍍、電解電鍍、無電電鍍、球滴或網版印刷過程而沉積於導電層222上。凸塊材料可以是Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其組合，而可選用助焊溶液。舉例而言，凸塊材料可以是共晶Sn/Pb、高鉛焊料或無鉛焊料。凸塊材料使用適合的附接或接合過程而接合於導電層222。於一實施例，凸塊材料藉由將材料加熱到其熔點之上而重熔以形成球或凸塊230。於某些應用，凸塊230重熔二次以改善對導電層222的電接觸。於一實施例，凸塊230形成於具有潤溼層、阻障層、黏著層的UBM上。凸塊也可以壓縮接合或熱壓縮接合於導電層 222。凸塊230代表一種可以形成於導電層222上的互連結構。互連結構也可以使用接合線、導電膏、柱凸塊、微凸塊或其他的電互連。
扇出晶圓級封裝232使用導線柱202來做為基板190和增層互連結構220之間的垂直電互連。導線柱202簡化了製程以降低成本和減少扇出晶圓級封裝之垂直互連結構中的脫層問題。
圖7a~7b顯示的實施例乃以封裝上封裝(PoP)安排來堆疊半導體封裝。於圖7a，半導體封裝240包括半導體晶粒或構件242，其具有背面244和有效表面246，而有效表面246包含類比或數位電路，其實施成為晶粒裡所形成的主動裝置、被動裝置、導電層、介電層，並且根據晶粒的電設計和功能而電互連。舉例而言，電路可以包括有效表面246裡所形成的一或更多個電晶體、二極體和其他電路元件以實施類比電路或數位電路，例如DSP、ASIC、記憶體或其他的訊號處理電路。半導體晶粒242也可以包含IPD，例如電感器、電容器、電阻器以用於RF訊號處理。於一實施例，半導體晶粒242是BGA或陸柵陣列(LGA)型裝置。
半導體晶粒242安裝於基板250，其包括導電線路252。多條接合線254連接在半導體晶粒242之有效表面246上形成的接觸墊256和基板250的導電線路252之間。包封物258沉積於半導體晶粒242、基板250、接合線254上。凸塊260形成於基板250相對於半導體晶粒242的導電線路252上。
圖7b顯示半導體封裝240安裝於來自圖4k的扇出晶圓級封裝184，而使凸塊260接合於基板140的導電層148而成為PoP 262。
圖8a~8b顯示的另一實施例乃以PoP或系統級封裝(SiP)安排 來堆疊半導體封裝。於圖8a，半導體封裝270包括半導體晶粒或構件272，其具有背面274和有效表面276，而有效表面276包含類比或數位電路，其實施成為晶粒裡所形成的主動裝置、被動裝置、導電層、介電層，並且根據晶粒的電設計和功能而電互連。舉例而言，電路可以包括有效表面276裡所形成的一或更多個電晶體、二極體和其他電路元件以實施類比電路或數位電路，例如DSP、ASIC、記憶體或其他的訊號處理電路。半導體晶粒272也可以包含IPD，例如電感器、電容器、電阻器以用於RF訊號處理。於一實施例，半導體晶粒272是BGA或LGA型裝置。
半導體晶粒272安裝於基板280，其包括導電線路282。多條接合線284連接在半導體晶粒272之有效表面276上所形成的接觸墊286和基板280的導電線路282之間。包封物288沉積於半導體晶粒272、基板280、接合線284上。凸塊290形成於基板280相對於半導體晶粒272的導電線路282上。
圖8b顯示半導體封裝270安裝於來自圖4k的扇出晶圓級封裝184，而使凸塊290接合於導電層148而成為SiP 292。附帶而言，離散半導體裝置294配置於包封物164上，並且以導電膏298而電連接於基板140的導電層148。離散半導體裝置294可以是被動構件，例如電感器、電容器或電阻器。離散半導體裝置294也可以是主動構件，例如電晶體或二極體。
雖然已經詳細示範本發明的一或更多個實施例，不過熟練的技術者將體會那些實施例可以做出修改和調適，而不偏離本發明如列於以下請求項的範圍。
124‧‧‧半導體晶粒或構件
128‧‧‧背面
130‧‧‧有效表面
132‧‧‧導電層
140‧‧‧中介基版
142‧‧‧絕緣或介電層
144‧‧‧垂直互連導電通孔
146、148‧‧‧導電層或再佈線層(RDL)
150‧‧‧導線柱
150a‧‧‧基底部分
150b‧‧‧柄
164‧‧‧包封物或模製化合物
170‧‧‧增層互連結構
172‧‧‧導電層或再佈線層
174‧‧‧絕緣或鈍化層
182‧‧‧球或凸塊
184‧‧‧扇出晶圓級封裝

Claims (15)

  1. 一種製作半導體裝置的方法，其包括：提供基板；將半導體晶粒配置於該基板的第一表面上；將導線柱附接於該基板的該第一表面；將包封物沉積於該基板、該半導體晶粒、該導線柱上；以及將互連結構形成於該包封物上並且電連接於該導線柱。
  2. 如申請專利範圍第1項的方法，其進一步包括移除部分的該包封物以暴露該導線柱。
  3. 如申請專利範圍第1項的方法，其進一步包括以雷射直接燒蝕來移除部分的該包封物。
  4. 如申請專利範圍第1項的方法，其進一步包括將接合墊形成於相對於該基板之該第一表面的該基板之第二表面上。
  5. 一種製作半導體裝置的方法，其包括：提供基板；將半導體晶粒配置於該基板上；將導線柱附接於該基板；以及將包封物沉積於該基板、該半導體晶粒、該導線柱上。
  6. 如申請專利範圍第5項的方法，其進一步包括將互連結構形成於該包封物上並且電連接於該導線柱。
  7. 如申請專利範圍第5項的方法，其進一步包括移除部分的該包封物以暴露該導線柱。
  8. 如申請專利範圍第5項的方法，其進一步包括移除部分的該包封物以暴露該基板。
  9. 如申請專利範圍第5項的方法，其進一步包括將接合墊形成於該基板相對於該導線柱的表面上。
  10. 一種半導體裝置，其包括：基板；半導體晶粒，其配置於該基板上；導線柱，其附接於乾基板；包封物，其沉積於該基板、該半導體晶粒、該導線柱上。
  11. 如申請專利範圍第10項的半導體裝置，其進一步包括互連結構，該互連結構形成於該包封物上。
  12. 如申請專利範圍第11項的半導體裝置，其中該互連結構電耦合於該導線柱。
  13. 如申請專利範圍第11項的半導體裝置，其中該互連結構電耦合於該半導體晶粒。
  14. 如申請專利範圍第10項的半導體裝置，其進一步包括接合墊，該接合墊形成於該基板相對於該導線柱的表面上。
  15. 如申請專利範圍第10項的半導體裝置，其進一步包括半導體封裝，該半導體封裝配置於該半導體晶粒上並且電連接於該基板。
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