JP6320799B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6320799B2 JP6320799B2 JP2014044494A JP2014044494A JP6320799B2 JP 6320799 B2 JP6320799 B2 JP 6320799B2 JP 2014044494 A JP2014044494 A JP 2014044494A JP 2014044494 A JP2014044494 A JP 2014044494A JP 6320799 B2 JP6320799 B2 JP 6320799B2
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- 239000004065 semiconductor Substances 0.000 title claims description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000000758 substrate Substances 0.000 claims description 61
- 238000002513 implantation Methods 0.000 claims description 56
- 239000002019 doping agent Substances 0.000 claims description 49
- 239000002344 surface layer Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 9
- 230000008018 melting Effects 0.000 claims description 9
- 239000000155 melt Substances 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 description 32
- 230000007547 defect Effects 0.000 description 13
- 230000003213 activating effect Effects 0.000 description 12
- 238000000137 annealing Methods 0.000 description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 9
- 239000011574 phosphorus Substances 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 230000004913 activation Effects 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
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- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Description
(a)表面にIGBT区画とダイオード区画とが画定された半導体基板の前記IGBT区画の表層部に、第1導電型の第1のドーパントをイオン注入して第1の注入領域を形成する工程と、
(b)前記半導体基板の前記IGBT区画の、前記第1の注入領域より浅い領域に、前記第1導電型とは反対の第2導電型の第2のドーパントをイオン注入することにより、第2の注入領域を形成する工程と、
(c)前記半導体基板の前記ダイオード区画の表層部に、前記第1導電型の第3のドーパントを、前記第2のドーパントより高濃度にイオン注入することにより、注入された領域をアモルファス化して第3の注入領域を形成する工程と、
(d)前記工程(a)、(b)及び(c)の後に、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記第3の注入領域が部分的に溶融し、前記第1の注入領域の前記第1のドーパントが活性化する条件で、第1のパルスレーザビームで走査する工程と、
(e)前記工程(d)の後に、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記第1のパルスレーザビームよりパルス幅の短い第2のパルスレーザビームで走査することにより、前記半導体基板の前記IGBT区画及び前記ダイオード区画の全域において、前記第2の注入領域より浅い表層部を溶融させ、結晶化させる工程と
を有する半導体装置の製造方法が提供される。
(a)表面にIGBT区画とダイオード区画とが画定された半導体基板の前記IGBT区画の表層部に、第1導電型の第1のドーパントをイオン注入して第1の注入領域を形成する工程と、
(b)前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記半導体基板の表面が溶融しない条件で、第1のパルスレーザビームで走査することにより、前記第1の注入領域の前記第1のドーパントを活性化させる工程と、
(c)前記工程(b)の後に、前記半導体基板の前記IGBT区画の、前記第1の注入領域より浅い領域に、前記第1導電型とは反対の第2導電型の第2のドーパントをイオン注入することにより、第2の注入領域を形成する工程と、
(d)前記半導体基板の前記ダイオード区画の表層部に、前記第1導電型の第3のドーパントを、前記第2のドーパントより高濃度にイオン注入することにより、注入された領域をアモルファス化して第3の注入領域を形成する工程と、
(e)前記工程(c)及び(d)の後に、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記第1のパルスレーザビームよりパルス幅の短い第2のパルスレーザビームで走査することにより、前記半導体基板の前記第2の注入領域及び前記第3の注入領域の少なくとも表層部を溶融させて、結晶化させることにより、前記第2のドーパント及び前記第3のドーパントを活性化させる工程と
を有し、
前記工程(b)で用いられる前記第1のパルスレーザビームは、前記工程(d)で形成されるアモルファス化された前記第3の注入領域の少なくとも表層部を溶融させることができる条件で前記半導体基板を走査する半導体装置の製造方法が提供される。
第1のパルスレーザビームを用いたレーザアニール時に、ダイオード区画の表層部が溶融しない。これにより、半導体基板の表面荒れを防止することができる。
表層部に、p型のアノード領域25が形成されている。第2の面14の表層部に、n型のカソード領域26が形成されている。アノード領域25は、ベース領域15と同一の深さを有する。カソード領域26は、バッファ領域21より浅い。第1の面13にアノード電極27が形成され、第2の面14にカソード電極28が形成されている。
%である。走査方向に関するビーム断面の幅をWtで表し、時間軸上で相互に隣り合う2ショットのパルスレーザビームのビーム断面が重なる部分の幅をWoで表したとき、オーバラップ率はWo/Wtで定義される。
その表面の荒れを解消することができる。
り、第3のドーパントが活性化し、カソード領域26が形成される。さらに、第2の注入領域20a(図5F)が溶融した後、結晶化することにより、第2のドーパントが活性化し、コレクタ領域20が形成される。第2の注入領域20a内の格子欠陥50(図5F)はほぼ消滅する。
11 IGBT区画
12 ダイオード区画
13 第1の面
14 第2の面
15 p型ベース領域
16 n型エミッタ領域
17 ゲート電極
18 ゲート絶縁膜
19 エミッタ電極
20 p型コレクタ領域
20a 第2の注入領域
21 n型バッファ領域
21a 第1の注入領域
22 コレクタ電極
25 アノード領域
26 カソード領域
26a 第3の注入領域
27 アノード電極
28 カソード電極
31 第2のレーザ光源
31A、31B 固体レーザ発振器
32A、32B アッテネータ
33A、33B ビームエキスパンダ
34 ミラー
35 ビームスプリッタ
36 シリンドリカルレンズアレイ群
37 ベンディングミラー
41 第1のレーザ光源
42 アッテネータ
43 ビームエキスパンダ
44 シリンドリカルレンズアレイ群
45 ダイクロイックミラー
46 コンデンサレンズ
47 伝搬光学系
48 ステージ
49 制御装置
50 格子欠陥
55 第1のパルスレーザビーム
56 第2のパルスレーザビーム
Claims (3)
- (a)表面にIGBT区画とダイオード区画とが画定された半導体基板の前記IGBT区画の表層部に、第1導電型の第1のドーパントをイオン注入して第1の注入領域を形成する工程と、
(b)前記半導体基板の前記IGBT区画の、前記第1の注入領域より浅い領域に、前記第1導電型とは反対の第2導電型の第2のドーパントをイオン注入することにより、第2の注入領域を形成する工程と、
(c)前記半導体基板の前記ダイオード区画の表層部に、前記第1導電型の第3のドーパントを、前記第2のドーパントより高濃度にイオン注入することにより、注入された領域をアモルファス化して第3の注入領域を形成する工程と、
(d)前記工程(a)、(b)及び(c)の後に、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記第3の注入領域が部分的に溶融し、前記第1の注入領域の前記第1のドーパントが活性化する条件で、第1のパルスレーザビームで走査する工程と、
(e)前記工程(d)の後に、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記第1のパルスレーザビームよりパルス幅の短い第2のパルスレーザビームで走査することにより、前記半導体基板の前記IGBT区画及び前記ダイオード区画の全域において、前記第2の注入領域より浅い表層部を溶融させ、結晶化させる工程と
を有する半導体装置の製造方法。 - 前記工程(d)において、前記半導体基板の前記IGBT区画及び前記ダイオード区画を、前記半導体基板の前記IGBT区画は溶融しない条件で、前記第1のパルスレーザビームで走査する請求項1に記載の半導体装置の製造方法。
- 前記工程(c)で形成される前記第3の注入領域は、前記工程(a)で形成される前記第1の注入領域より浅い請求項1または2に記載の半導体装置の製造方法。
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US20200235229A1 (en) | 2020-07-23 |
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CN106062959A (zh) | 2016-10-26 |
TWI559378B (zh) | 2016-11-21 |
US20160372583A1 (en) | 2016-12-22 |
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TW201535485A (zh) | 2015-09-16 |
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