CN103681368A - 半导体装置和将线柱形成为fo-wlp中的垂直互连的方法 - Google Patents

半导体装置和将线柱形成为fo-wlp中的垂直互连的方法 Download PDF

Info

Publication number
CN103681368A
CN103681368A CN201310149140.0A CN201310149140A CN103681368A CN 103681368 A CN103681368 A CN 103681368A CN 201310149140 A CN201310149140 A CN 201310149140A CN 103681368 A CN103681368 A CN 103681368A
Authority
CN
China
Prior art keywords
substrate
semiconductor element
terminal
sealant
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310149140.0A
Other languages
English (en)
Other versions
CN103681368B (zh
Inventor
P.C.马里穆图
S.M.L.阿尔瓦雷斯
林耀剑
J.A.卡帕拉斯
陈严谨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changdian Integrated Circuit Shaoxing Co ltd
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Publication of CN103681368A publication Critical patent/CN103681368A/zh
Application granted granted Critical
Publication of CN103681368B publication Critical patent/CN103681368B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/2633—Bombardment with radiation with high-energy radiation for etching, e.g. sputteretching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02311—Additive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2512—Layout
    • H01L2224/25171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49174—Stacked arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1082—Shape of the containers for improving alignment between containers, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure

Abstract

半导体装置具有衬底和设置在该衬底的第一表面上的半导体管芯。线柱附连到该衬底的第一表面。线柱包括基底部分和杆部分。接合盘在衬底的第二表面上形成。密封剂沉积在衬底、半导体管芯和线柱上。密封剂的一部分通过LDA去除来暴露线柱。密封剂的一部分通过LDA去除来暴露衬底。互连结构在密封剂上形成并且电连接到线柱和半导体管芯。凸点在互连结构上形成。半导体封装件设置在密封剂上并且电连接到衬底。分立半导体装置设置在密封剂上并且电连接到衬底。

Description

半导体装置和将线柱形成为FO-WLP中的垂直互连的方法
要求国内优先权
本申请要求于2012年9月14日提交的美国临时申请号61/701,419的权益，该申请通过引用合并于此。
技术领域
本发明一般来说涉及半导体装置，并且更特别地，涉及将线柱形成为扇出晶片级封装（Fo-WLP）中的垂直互连的方法和半导体装置。
背景技术
通常在现代的电子产品中发现半导体装置。半导体装置在电子组件的数量和密度方面不同。分立半导体装置一般包含一个类型的电组件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、感应器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成的半导体装置典型地包含数百至数百万的电组件。集成的半导体装置的示例包括微控制器、微处理器、带电-耦合的装置（CCD）、太阳能电池和数字微镜装置（DMD）。
半导体装置执行广泛的功能，例如信号处理、高速计算、传送和接收电磁信号、控制电子装置、将太阳光变换为电以及对电视显示器创建视觉投影。在娱乐、通信、功率转换、网络、计算机和消费者产品的领域中发现半导体装置。还在军事应用、航空、汽车、工业控制器和办公设备中发现半导体装置。
半导体装置利用半导体材料的电特性。半导体材料的结构允许它的电导率通过施加电场或基极电流或通过掺杂过程而操纵。掺杂将杂质引入半导体材料来操纵和控制半导体装置的导电率。
半导体装置包含有源和无源电结构。有源结构（其包括双极和场效应晶体管）控制电流的流动。通过改变掺杂水平和施加电场或基极电流，晶体管促进或限制电流的流动。无源结构（其包括电阻器、电容器和感应器）创建执行多种电功能所必需的电压和电流之间的关系。无源和有源结构电连接来形成电路，其使半导体装置能够执行高速操作和其他有用的功能。
一般使用两个复杂的制造过程制造半导体装置，即，前端制造和后端制造，每个潜在地牵涉数百个步骤。前端制造牵涉在半导体晶片的表面上形成多个管芯（die）。每个半导体管芯典型地是相同的并且包含由电连接有源和无源组件形成的电路。后端制造牵涉使来自完成的晶片的单独半导体管芯单个化并且封装该管芯来提供结构支承和环境隔离。如本文使用的术语“半导体管芯”指词的单数或复数形式两者，并且因此，可以指单个半导体装置和多个半导体装置两者。
半导体制造的一个目标是生产较小的半导体装置。较小的装置典型地消耗更少的电力、具有更高的性能并且可以被有效地生产。另外，较小的半导体装置具有更小的占用空间，这对于较小的最终产品是可期望的。较小的半导体管芯尺寸可以通过前端过程中的改进而实现，从而导致具有更小、更高密度的有源和无源组件的半导体管芯。后端过程可通过电互连和封装材料中的改进而导致具有较小占用空间的半导体装置封装件。
半导体封装件通常通过半导体管芯周围的密封剂使用导电柱或通路作为在例如顶部互连结构与底部互连结构之间的垂直互连。通路典型地通过密封剂形成并且用导电材料填充。导电通路的形成耗时并且牵涉昂贵的设备。导电通路可从顶部互连结构和底部结构变成分层的，从而导致制造缺陷或潜在缺陷。
发明内容
在Fo-WLP中存在对简单且成本有效的垂直互连结构的需要。因此，在一个实施例中，本发明是制作半导体装置的方法，其包括步骤：提供衬底、将半导体管芯设置在所述衬底的第一表面上、将线柱附连到所述衬底的所述第一表面、将密封剂沉积在所述衬底、半导体管芯和线柱上、以及在所述密封剂上形成互连结构并且电连接到所述线柱。
在另一个实施例中，本发明是制作半导体装置的方法，其包括以下步骤：提供衬底、将半导体管芯设置在所述衬底上、将线柱附连到所述衬底、以及将密封剂沉积在所述衬底、半导体管芯和线柱上。
在另一个实施例中，本发明是半导体装置，其包括衬底和设置在该衬底上的半导体管芯。线柱附连到该衬底。密封剂沉积在衬底、半导体管芯和线柱上。互连结构在该密封剂上形成。
在另一个实施例中，本发明是半导体装置，其包括衬底和设置在该衬底上的半导体管芯。线柱附连到该衬底。密封剂沉积在衬底、半导体管芯和线柱上。
附图说明
图1图示印刷电路板（PCB），其具有安装到它的表面的不同类型的封装件；
图2a-2c图示安装到PCB的代表性半导体封装件的另外的细节；
图3a-3c图示具有由锯道分开的多个半导体管芯的半导体晶片；
图4a-4k图示将线柱形成为Fo-WLP中的垂直互连的过程；
图5图示Fo-WLP中的半导体管芯的相对取向；
图6a-6i图示使线柱形成为Fo-WLP中的垂直互连的另一个过程；
图7a-7b图示带有Fo-WLP的PoP布置，该Fo-WLP具有作为垂直互连的线柱；以及
图8a-8b图示带有Fo-WLP的SiP布置，该Fo-WLP具有作为垂直互连的线柱。
具体实施方式
在下面的描述中参考图（其中类似的数字代表相同或相似的元件）在一个或多个实施例中描述本发明。尽管根据用于实现本发明的目的的最佳模式来描述本发明，本领域内技术人员将意识到意在涵盖如可包括在本发明的精神和范围内的备选、修改和等同物，本发明的精神和范围如由随附权利要求和它们的等同物限定，如由下面的公开和图支持的。
一般使用两个复杂的制造过程制造半导体装置：前端制造和后端制造。前端制造牵涉在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含有源和无源电组件，其电连接来形成功能电路。例如晶体管和二极管的有源电组件具有控制电流流动的能力。例如电容器、感应器和电阻器的无源电组件创建执行电路功能所必需的电压和电流之间的关系。
无源和有源组件通过一系列过程步骤（其包括掺杂、沉积、光刻、蚀刻和平坦化）在半导体晶片的表面上形成。掺杂通过例如离子注入或热扩散的技术将杂质引入半导体材料内。掺杂过程通过响应于电场或基极电流动态改变半导体材料导电率而在有源装置中修改半导体材料的电导率。晶体管包含具有在必要时布置以使晶体管能够在施加电场或基极电流时促进或限制电流流动的不同类型和程度的掺杂的区域。
有源和无源组件由具有不同电特性的材料层形成。这些层可以由部分通过沉积的材料的类型确定的多种沉积技术形成。例如，薄膜沉积可以牵涉化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀和无电电镀过程。每个层一般被图案化来形成有源组件、无源组件或这些组件之间的电连接的部分。
后端制造指将完成的晶片切割或单个化为单独半导体管芯并且然后封装该半导体管芯以用于结构支承和环境隔离。为了将半导体管芯单个化，沿晶片的非功能区域刻划晶片或使晶片断裂，叫作锯道或划痕。使用激光切割工具或锯条来使晶片单个化。在单个化之后，单独半导体管芯安装到封装衬底，其包括用于与其他系统组件互连的管脚或接触盘。在半导体管芯上形成的接触盘然后连接到封装件内的接触盘。可以用焊料凸点、柱凸点、导电膏或引线接合作出电连接。密封剂或其他模塑材料沉积在封装件上来提供物理支承和电隔离。完成的封装件然后插入电系统内并且半导体装置的功能性对其他系统组件变得可用。
图1图示电子装置50，该电子装置50具有芯片载体衬底或印刷电路板（PCB）52，其具有安装在它的表面上的多个半导体封装件。该电子装置50可以具有一个类型的半导体封装件，或多个类型的半导体封装件，这取决于应用。为了说明目的，在图1中示出不同类型的半导体封装件。
电子装置50可以是使用半导体封装件来执行一个或多个电功能的独立系统。备选地，电子装置50可以是较大系统的子组件。例如，电子装置50可以是蜂窝电话、个人数字助理（PDA）、数字视频摄像机（DVC）或其他电子通信装置的一部分。备选地，电子装置50可以是显卡、网络接口卡或可以插入计算机内的其他信号处理卡。半导体封装件可以包括微处理器、存储器、专用集成电路（ASIC）、逻辑电路、模拟电路、RF电路、分立装置或其他半导体管芯或电组件。小型化和重量减少对于被市场接受的产品是必要的。半导体装置之间的距离必须减小来实现更高的密度。
在图1中，PCB 52为安装在PCB上的半导体封装件的结构支承和电互连提供通用衬底。导电信号迹线54使用蒸发、电解电镀、无电电镀、丝网印刷或其他适合的金属沉积过程在衬底上或在PCB 52的层内形成。信号迹线54在半导体封装件中的每个、安装的组件和其他外部系统组件之间提供电通信。迹线54还向半导体封装件中的每个提供电力和接地连接。
在一些实施例中，半导体装置具有两个封装级。第一级封装是用于使半导体管芯机械和电附连到中间载体的技术。第二级封装牵涉使中间载体机械和电附连到PCB。在其他实施例中，半导体装置可仅具有第一级封装，其中管芯直接机械和电安装到PCB。
为了说明目的，若干类型的第一级封装在PCB 52上示出，其包括接合线封装56和倒装芯片58。另外，若干类型的第二级封装示出安装在PCB 52上，其包括球栅阵列（BGA）60、凸点芯片载体（BCC）62、双列直插封装（DIP）64、焊盘栅阵列（LGA）66、多芯片模块（MCM）68、四侧无引线扁平封装（QFN）70和四侧扁平封装72。取决于系统要求，半导体封装件的任何组合（配置有第一和第二级封装类型的任何组合）以及其他电子组件可以连接到PCB 52。在一些实施例中，电子装置50包括单个附连的半导体封装件，而其他实施例要求多个互连的封装件。通过在单个衬底上组合一个或多个半导体封装件，制造商可以将预制的组件并入电子装置和系统。因为半导体封装件包括高级功能性，电子装置可以使用较不昂贵的组件和流水线制造过程制造。所得的装置较不太可能出故障并且制造起来较不昂贵，从而对消费者产生更低的成本。
图2a-2c示出示范性半导体封装件。图2a图示安装在PCB 52上的DIP 64的另外的细节。半导体管芯74包括包含模拟或数字电路的有源区域，所述模拟或数字电路实现为根据该管芯的电设计在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，该电路可以包括一个或多个晶体管、二极管、感应器、电容器、电阻器和在半导体管芯74的有源区域内形成的其他电路元件。接触盘76是一层或多层导电材料，例如铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）或银（Ag），并且电连接到在半导体管芯74内形成的电路元件。在DIP 64的组装期间，半导体管芯74使用金硅共晶层或例如热环氧或环氧树脂的粘合剂材料安装到中间载体78。封装体包括例如聚合物或陶瓷的绝缘封装材料。导体引线80和接合线82提供半导体管芯74和PCB 52之间的电互连。密封剂84沉积在封装件上以通过防止湿气或颗粒进入封装件并且污染半导体管芯74或接合线82而用于环境保护。
图2b图示安装在PCB 52上的BCC 62的另外的细节。半导体管芯88使用底部填充或环氧树脂粘合剂材料92安装在载体90上。接合线94提供接触盘96和98之间的第一级封装互连。模塑化合物或密封剂100沉积在半导体管芯88和接合线94上来提供装置的物理支承和电隔离。接触盘102使用例如电解电镀或无电电镀的适合的金属沉积过程在PCB 52的表面上形成来防止氧化。接触盘102电连接到PCB 52中的一个或多个导电信号迹线54。凸点104在BCC 62的接触盘98和PCB 52的接触盘102之间形成。
在图2c中，半导体管芯58向下面向中间载体106用倒装芯片类型第一级封装来安装。半导体管芯58的有源区域108包含模拟或数字电路，其实现为根据该管芯的电设计形成的有源装置、无源装置、导电层和介电层。例如，该电路可以包括一个或多个晶体管、二极管、感应器、电容器、电阻器和在有源区域108内的其他电路元件。半导体管芯58通过凸点110电和机械地连接到载体106。
BGA 60使用凸点112用BGA类型第二级封装电并且机械地连接到PCB 52。半导体管芯58通过凸点110、信号线114和凸点112电连接到PCB 52中的导电信号迹线54。模塑化合物或密封剂116沉积在半导体管芯58和载体106上来提供装置的物理支承和电隔离。倒装芯片半导体装置提供从半导体管芯58上的有源装置到PCB 52上的导电轨道的短电导路径，以便减少信号传播距离，降低电容并且改进总体电路性能。在另一个实施例中，半导体管芯58可以使用倒装芯片类型第一级封装而没有中间载体106直接机械和电连接到PCB 52。
图3a示出具有例如硅、锗、砷化镓、磷化铟或碳化硅的基础衬底材料122用于结构支承的半导体晶片120。多个半导体管芯或组件124在晶片120上形成，它们由非活性的管芯间晶片区域或如上文描述的锯道126分开。锯道126提供切割区域来将半导体晶片120单个化成单独半导体管芯124。
图3b示出半导体晶片120的一部分的横截面视图。每个半导体管芯124具有背表面128和包含模拟或数字电路的有源表面130，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，该电路可包括一个或多个晶体管、二极管和在有源表面130内形成的其他电路元件，来实现模拟电路或数字电路，例如数字信号处理器（DSP）、ASIC、存储器或其他信号处理电路。半导体管芯124还可包含集成的无源装置（IPD）（例如感应器、电容器和电阻器）以用于RF信号处理。在一个实施例中，半导体管芯124是球栅阵列（BGA）类型装置。
导电层132使用PVD、CVD、电解电镀、无电电镀过程或其他适合的金属沉积过程在有源表面130上形成。导电层132可以是一层或多层Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料。导电层132作为电连接到有源表面130上的电路的接触盘来操作。导电层132可以形成为并排设置在离半导体管芯124的边缘第一距离的接触盘，如在图3b中示出的。备选地，导电层132可以形成为在多行中偏置的接触盘，使得第一行接触盘设置在离管芯的边缘第一距离，并且与该第一行交替的第二行接触盘设置在离管芯的边缘第二距离。
在图3c中，半导体晶片120使用锯条或激光切割工具134通过锯道126单个化成单独半导体管芯124。
图4a-4k与图1和2a-2c有关地图示在Fo-WLP中将线柱形成为衬底和建立的互连结构之间的垂直互连的过程。图4a示出插入器衬底140，其包括预浸渍聚四氟乙烯（预浸渍体）、FR-4、FR-1、CEM-1或CEM-3与酚醛棉纸、环氧、树脂、纺织玻璃、雾面玻璃、聚酯和其他增强纤维或织物的组合的一个或多个片状层。备选地，衬底140包含一个或多个绝缘或介电层142。
使用激光钻孔、机械钻孔或深反应离子蚀刻（DRIE）形成通过衬底140的多个通路。使用电解电镀、无电电镀过程或其他适合的沉积过程用Al、Cu、Sn、Ni、Au、Ag、钛（Ti）、钨（W）或其他适合的导电材料填充通路来形成z方向垂直互连导电通路144。
导电层或重新分配层（RDL）146在导电通路144和衬底140的第一表面上使用例如印刷、PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积过程而形成。导电层146包括Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层146电连接到导电通路144。
导电层或RDL 148在与第一表面和导电通路144相对的衬底140的第二表面上使用例如印刷、PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积过程而形成。导电层148包括Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层148电连接到导电通路144和导电层146。在另一个实施例中，在形成导电层146和/或导电层148之后，形成通过衬底140的导电通路144。
根据半导体管芯124的电功能，所得的插入器衬底140通过导电层146和148以及导电通路144提供垂直和横向地跨越衬底的电互连。根据半导体管芯124的设计和功能，导电层146和148以及导电通路144的部分电共用或电隔离。
衬底140还可以是多层柔性压层、陶瓷、铜箔、玻璃或半导体晶片，其包括包含一个或多个晶体管、二极管和其他电路元件来实现模拟电路或数字电路的有源表面。
在图4b中，来自图3c的半导体管芯124使用例如具有朝衬底取向的有源表面130的取和放操作而安装到插入器衬底140。用例如环氧树脂的管芯附连粘合剂将半导体管芯124固定到衬底140。半导体管芯124的导电层132电连接到衬底140的导电层146。图4c示出安装到衬底140的半导体管芯124。
在图4d中，多个线柱150通过压力接合、针脚式接合或球接合（其采用自由空气球（FAB）或环轮廓的形式）而附连到衬底140。线柱150在与导电层146接触时压挤，示出为基底部分150a。杆150b可以切割成适当的长度，例如250-500微米（μm）。线柱150提供z方向垂直互连结构。
图4e示出载体或临时衬底160，其包含例如硅、聚合物、氧化铍、玻璃或其他适合的低成本刚性材料的牺牲基底材料以用于结构支承。接口层或双面带162在载体160上形成为临时粘附接合膜、蚀刻停止层或热释放层。来自图4d的衬底、半导体管芯和线柱组装件倒转并且安装到载体160和接口层162。线柱150可以与半导体管芯124高度相同或高度比半导体管芯更小来避免在安装到载体160期间使线柱弯曲。线柱150高度还可以大于半导体管芯124。线柱150具有足够的直径以在后续制造过程期间保持刚性和稳定。
在图4f中，使用膏印刷、压缩模塑、传递模塑、液态密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物164沉积在载体160上和衬底140、半导体管芯124和线柱150周围。密封剂164可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂164是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。
在图4g中，载体160和接口层162通过化学蚀刻、机械去皮、化学机械平坦化（CMP）、机械研磨、热烘、UV光、激光扫描或湿法脱模而去除。倒转衬底、半导体管芯和线柱组装件。
密封剂164的一部分使用激光器166通过浅部激光直接烧蚀（LDA）而去除来暴露线柱150的杆150b。备选地，密封剂140的一部分通过图案化的光致抗蚀剂层由蚀刻过程去除来暴露线柱150。如果线柱本来已经暴露具有与半导体管芯124相同高度或比半导体管芯124更大高度，线柱150的暴露可以不是必需的。
在图4h中，建立的互连结构170在密封剂164和半导体管芯124上形成。该建立的互连结构170包括使用例如溅射、电解电镀和无电电镀的图案化和金属沉积过程形成的导电层或RDL 172。导电层172可以是 Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的中的一个或多个层。导电层172的一部分延伸到密封剂164的去除部分内，其使线柱150暴露以电连接到线柱。导电层172的其他部分可以电共用或电隔离，这取决于半导体管芯124的设计和功能。
建立的互连结构 170进一步包括绝缘或钝化层174，其使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在密封剂164和半导体管芯124上以及导电层172周围形成以用于电隔离。绝缘层174包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）或具有相似绝缘和结构特性的其他材料的一个或多个层。
在图4i中，与互连结构170相对的密封剂164的一部分经历利用研磨机178来使表面平坦化并且使密封剂的厚度减小的研磨操作。化学蚀刻或CMP过程也可以用于去除由研磨操作产生的机械损坏并且使密封剂164平坦化。厚度减小的密封剂164仍然覆盖衬底140来保护导电层148。
在图4j中，密封剂164的一部分使用激光器180通过浅部LDA而去除来暴露衬底140的导电层148以用于电互连到其他半导体装置，如在图7a-7b和8a-8b中讨论的。
在图4k中，导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在导电层172上。该凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、铅（Pb）、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层172。在一个实施例中，通过将材料加热到它的熔点以上来形成球或凸点182而使凸点材料软熔。在一些应用中，凸点182再次被软熔来改进到导电层172的电接触。在一个实施例中，凸点182在具有浸湿层、阻挡层和粘附层的UBM上形成。凸点还可以压力接合或热压接合到导电层172。凸点182代表可以在导电层172上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。
Fo-WLP 184使用线柱150以用于衬底140与建立的互连结构170之间的垂直电互连。线柱150使制造过程简化来减少成本并且减少关于Fo-WLP中的垂直互连结构的分层问题。
图5示出一实施例，其中半导体管芯124将背表面128安装到插入器衬底140。如必要的话，与图4g相似，密封剂164的一部分通过LAD而去除来暴露导电层132。与图4h相似，导电层172的一部分延伸到密封剂164的去除部分内，其使半导体管芯124的导电层132暴露以电连接到半导体管芯。
图6a-6i与图1和2a-2c有关地图示在Fo-WLP中将线柱形成为衬底和建立的互连结构之间的垂直互连的另一个过程。图6a示出插入器衬底190，其包括聚四氟乙烯预浸渍体、FR-4、FR-1、CEM-1或CEM-3与酚醛棉纸、环氧、树脂、纺织玻璃、雾面玻璃、聚酯和其他增强纤维或织物的组合的一个或多个片状层。备选地，衬底190包含一个或多个绝缘或介电层192。
使用激光钻孔、机械钻孔或DRIE形成通过衬底190的多个通路。使用电解电镀、无电电镀过程或其他适合的沉积过程用Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他适合的导电材料填充通路来形成z方向垂直互连导电通路194。
导电层或RDL 196在导电通路194和衬底190的第一表面上使用例如印刷、PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积过程而形成。导电层196包括Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层196电连接到导电通路194。导电层或RDL 198在与第一表面和导电通路194相对的衬底190的第二表面上使用例如印刷、PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积过程而形成。导电层198包括Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层198电连接到导电通路194和导电层196。在另一个实施例中，在形成导电层196和/或导电层198之后，形成通过衬底190的导电通路194。
导电层200在半导体管芯124的安装位置外部在导电层198上使用例如印刷、PVD、CVD、溅射、电解电镀和无电电镀的图案化和金属沉积过程而形成。导电层200包括Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。导电层200作为电连接到导电层198和导电通路194的接合盘而操作。
根据半导体管芯124的电功能，所得的插入器衬底190通过导电层196和198以及导电通路194提供垂直和横向地跨越衬底的电互连。根据半导体管芯124的设计和功能，导电层196和198以及导电通路194的部分电共用或电隔离。
衬底190还可以是多层柔性压层、陶瓷、铜箔、玻璃或半导体晶片，其包括包含一个或多个晶体管、二极管和其他电路元件来实现模拟电路或数字电路的有关表面。
来自图3c的半导体管芯124使用例如具有朝衬底取向的背表面128的取和放操作而安装到插入器衬底190。用例如环氧树脂的管芯附连粘合剂将半导体管芯124固定到衬底190。图6b示出安装到衬底190的半导体管芯124。
在图6c中，多个线柱202通过压力接合、针脚式接合或球接合（其采用FAB或环轮廓的形式）而附连到衬底190。线柱202在与导电层196接触时压挤，示出为基底部分202a。杆202b可以切割成适当的长度，例如250-500微米μm。线柱202提供z方向垂直互连结构。
图6d示出载体或临时衬底210，其包含例如硅、聚合物、氧化铍、玻璃或其他适合的低成本刚性材料的牺牲基底材料以用于结构支承。接口层或双面带212在载体210上形成为临时粘附接合膜、蚀刻停止层或热释放层。来自图6c的衬底、半导体管芯和线柱组装件倒转并且安装到载体210和接口层212。线柱202可以与半导体管芯124高度相同或高度比半导体管芯更小来避免在安装到载体190期间使线柱弯曲。线柱202高度还可以大于半导体管芯124。线柱202具有足够的直径以在后续制造过程期间保持刚性和稳定。
在6e中，使用膏印刷、压缩模塑、传递模塑、液体密封剂模塑、真空叠层、旋涂或其他适合的涂抹器将密封剂或模塑化合物214沉积在载体210上和衬底190、半导体管芯124和线柱202周围。密封剂214可以是聚合复合材料，例如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯或具有合适的填充物的聚合物。密封剂214是非导电的并且在环境上保护半导体装置免受外部元件或污染物影响。
在图6f中，载体210和接口层212通过化学蚀刻、机械去皮、CMP、机械研磨、热烘、UV光、激光扫描或湿法脱模而去除。倒转衬底、半导体管芯和线柱组装件。
密封剂214的一部分使用激光器216通过浅部LDA而去除来暴露线柱202的杆202b。备选地，密封剂214的一部分通过图案化的光致抗蚀剂层由蚀刻过程去除来暴露线柱202。如果线柱本来已经暴露具有与半导体管芯124相同高度或比半导体管芯124更大高度，线柱202的暴露可以不是必需的。如必要的话，密封剂164的一部分也使用激光器126通过浅部LDA去除来暴露半导体管芯124的导电层132。
在图6g中，建立的互连结构220在密封剂214和半导体管芯124上形成。该建立的互连结构220包括使用例如溅射、电解电镀和无电电镀的图案化和金属沉积过程形成的导电层或RDL 222。导电层222可以是 Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料中的一个或多个层。导电层222的一个部分延伸到密封剂214的去除部分内，其使线柱202暴露以电连接到线柱。导电层222的另一部分电连接到半导体管芯124的导电层132。导电层222的其他部分可以电共用或电隔离，这取决于半导体管芯124的设计和功能。
建立的互连结构 220进一步包括绝缘或钝化层224，其使用PVD、CVD、印刷、旋涂、喷涂、烧结或热氧化在密封剂214和半导体管芯124上以及导电层222周围形成以用于电隔离。绝缘层224包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似绝缘和结构特性的其他材料的一个或多个层。
在图6h中，与互连结构220相对的密封剂214的一部分经历利用研磨机228来使表面平坦化并且使密封剂的厚度减小并且暴露导电层200的研磨操作。化学蚀刻或CMP过程可以用于去除由研磨操作产生的机械损坏并且使密封剂214平坦化。厚度减小的密封剂214仍然覆盖衬底190来保护导电层198。
在图6i中，导电凸点材料使用蒸发、电解电镀、无电电镀、落球或丝网印刷过程而沉积在导电层222上。该凸点材料可以是具有可选的焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸点材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。凸点材料使用适合的附连或接合过程接合到导电层222。在一个实施例中，通过将材料加热到它的熔点以上来形成球或凸点230而使凸点材料软熔。在一些应用中，凸点230再次被软熔来改进到导电层222的电接触。在一个实施例中，凸点230在具有浸湿层、阻挡层和粘附层的UBM上形成。凸点还可以压力接合或热压接合到导电层222。凸点230代表可以在导电层222上形成的一个类型的互连结构。该互连结构还可以使用接合线、导电膏、柱凸点、微凸点或其他电互连。
Fo-WLP 232使用线柱202用于衬底190与建立的互连结构220之间的垂直电互连。线柱202使制造过程简化来减少成本并且减少关于Fo-WLP中的垂直互连结构的分层问题。
图7a-7b示出用于采用层叠封装（PoP）布置使半导体封装件堆叠的实施例。在图7a中，半导体封装240包括半导体管芯或组件242，其具有包含模拟或数字电路的背表面244和有源表面246，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，电路可包括一个或多个晶体管、二极管和在有源表面246内形成来实现例如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路的其他电路元件。半导体管芯242还可包含IPD，例如感应器、电容器和电阻器，以用于RF信号处理。在一个实施例中，半导体管芯242是BGA或焊盘栅阵列（LGA）类型装置。
半导体管芯242安装到衬底250，其包括导电迹线252。多个接合线254连接于在半导体管芯242的有源表面246上形成的接触盘256与衬底250的导电迹线252之间。密封剂258沉积在半导体管芯242、衬底250和接合线254上。凸点260在与半导体管芯242相对的衬底250的导电迹线252上形成。
图7b示出半导体封装件240安装到来自图4k的Fo-WLP 184作为PoP 262，其中凸点260接合到衬底140的导电层148。
图8a-8b示出用于采用PoP或系统级封装（SiP）布置使半导体封装件堆叠的另一个实施例。在图8a中，半导体封装件270包括半导体管芯或组件272，其具有包含模拟或数字电路的背表面274和有源表面276，所述模拟或数字电路实现为根据该管芯的电设计和功能在该管芯内形成并且电互连的有源装置、无源装置、导电层和介电层。例如，电路可包括一个或多个晶体管、二极管和在有源表面276内形成来实现例如DSP、ASIC、存储器或其他信号处理电路的模拟电路或数字电路的其他电路元件。半导体管芯272还可包含IPD，例如感应器、电容器和电阻器，以用于RF信号处理。在一个实施例中，半导体管芯272是BGA或LGA类型装置。
半导体管芯272安装到衬底280，其包括导电迹线282。多个接合线284连接于在半导体管芯272的有源表面286上形成的接触盘286与衬底280的导电迹线282之间。密封剂288沉积在半导体管芯272、衬底280和接合线284上。凸点290在与半导体管芯272相对的衬底280的导电迹线282上形成。
图8b示出半导体封装件270安装到来自图4k的Fo-WLP 184作为SiP 292,其中凸点290接合到导电层148。另外，分立半导体装置294设置在密封剂164上并且用导电膏298电连接到衬底140的导电层148。分立半导体装置294可以是无源组件，例如感应器、电容器或电阻器。分立半导体装置294还可以是有源组件，例如晶体管或二极管。
尽管已经详细地图示本发明的一个或多个实施例，技术人员将意识到可对那些实施例作出修改和调整而不偏离如在随附权利要求中阐述的本发明的范围。

Claims (15)

1.一种制作半导体装置的方法，包括：
提供衬底；
将半导体管芯设置在所述衬底的第一表面上；
将线柱附连到所述衬底的所述第一表面；
将密封剂沉积在所述衬底、半导体管芯和线柱上；以及
在所述密封剂上形成互连结构并且电连接到所述线柱。
2.如权利要求1所述的方法，进一步包括去除所述密封剂的一部分以暴露所述线柱。
3.如权利要求1所述的方法，进一步包括通过激光直接烧蚀去除所述密封剂的一部分。
4.如权利要求1所述的方法，进一步包括在与所述衬底的所述第一表面相对的所述衬底的第二表面上形成接合盘。
5.一种制作半导体装置的方法，包括：
提供衬底；
将半导体管芯设置在所述衬底上；
将线柱附连到所述衬底；以及
将密封剂沉积在所述衬底、半导体管芯和线柱上。
6.如权利要求5所述的方法，进一步包括在所述密封剂上形成互连结构并且电连接到所述线柱。
7.如权利要求5所述的方法，进一步包括去除所述密封剂的一部分以暴露所述线柱。
8.如权利要求5所述的方法，进一步包括去除所述密封剂的一部分以暴露所述衬底。
9.如权利要求5所述的方法，进一步包括在与所述线柱相对的所述衬底的表面上形成接合盘。
10.一种半导体装置，包括：
衬底；
半导体管芯，其设置在所述衬底上；
线柱，其附连到所述衬底；以及
密封剂，其沉积在所述衬底、半导体管芯和线柱上。
11.如权利要求10所述的半导体装置，进一步包括在所述密封剂上形成的互连结构。
12.如权利要求11所述的半导体装置，其中，所述互连结构电耦合到所述线柱。
13.如权利要求11所述的半导体装置，其中，所述互连结构电耦合到所述半导体管芯。
14.如权利要求10所述的半导体装置，进一步包括在与所述线柱相对的所述衬底的表面上形成的接合盘。
15.如权利要求10所述的半导体装置，进一步包括设置在所述半导体管芯上并且电连接到所述衬底的半导体封装件。
CN201310149140.0A 2012-09-14 2013-04-26 半导体装置和将线柱形成为fo‑wlp中的垂直互连的方法 Active CN103681368B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261701419P 2012-09-14 2012-09-14
US61/701419 2012-09-14
US13/832,781 US9443797B2 (en) 2012-09-14 2013-03-15 Semiconductor device having wire studs as vertical interconnect in FO-WLP
US13/832781 2013-03-15

Publications (2)

Publication Number Publication Date
CN103681368A true CN103681368A (zh) 2014-03-26
CN103681368B CN103681368B (zh) 2018-01-30

Family

ID=50273626

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310149140.0A Active CN103681368B (zh) 2012-09-14 2013-04-26 半导体装置和将线柱形成为fo‑wlp中的垂直互连的方法

Country Status (4)

Country Link
US (2) US9443797B2 (zh)
CN (1) CN103681368B (zh)
SG (1) SG2013050265A (zh)
TW (1) TWI594343B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970312A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 封装件及其形成方法
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same

Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
KR20140126598A (ko) * 2013-04-23 2014-10-31 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9633869B2 (en) * 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9076724B1 (en) 2013-09-26 2015-07-07 Stats Chippac Ltd. Integrated circuit system with debonding adhesive and method of manufacture thereof
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9406588B2 (en) * 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
JP6320799B2 (ja) * 2014-03-07 2018-05-09 住友重機械工業株式会社 半導体装置の製造方法
US9318452B2 (en) 2014-03-21 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9613910B2 (en) * 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9355963B2 (en) * 2014-09-26 2016-05-31 Qualcomm Incorporated Semiconductor package interconnections and method of making the same
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) * 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10212496B2 (en) * 2015-10-28 2019-02-19 Ciena Corporation High port count switching module, apparatus, and method
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9842820B1 (en) * 2015-12-04 2017-12-12 Altera Corporation Wafer-level fan-out wirebond packages
US20190206833A1 (en) * 2015-12-23 2019-07-04 Intel IP Corporation Eplb/ewlb based pop for hbm or customized package stack
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9613895B1 (en) * 2016-03-03 2017-04-04 Inotera Memories, Inc. Semiconductor package with double side molding
US10373884B2 (en) * 2016-03-31 2019-08-06 Samsung Electronics Co., Ltd. Fan-out semiconductor package for packaging semiconductor chip and capacitors
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
KR102632563B1 (ko) 2016-08-05 2024-02-02 삼성전자주식회사 반도체 패키지
KR101982044B1 (ko) 2016-08-31 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
KR101973431B1 (ko) * 2016-09-29 2019-04-29 삼성전기주식회사 팬-아웃 반도체 패키지
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10283377B1 (en) * 2017-11-07 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
JP2019110201A (ja) * 2017-12-18 2019-07-04 ルネサスエレクトロニクス株式会社 電子装置および電子機器
US20190244943A1 (en) * 2018-02-08 2019-08-08 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US11315891B2 (en) * 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
KR102048319B1 (ko) * 2018-07-20 2019-11-25 삼성전자주식회사 반도체 패키지
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11217546B2 (en) * 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11257747B2 (en) * 2019-04-12 2022-02-22 Powertech Technology Inc. Semiconductor package with conductive via in encapsulation connecting to conductive element
KR20210022785A (ko) * 2019-08-20 2021-03-04 삼성디스플레이 주식회사 표시 장치
US11521958B2 (en) * 2019-11-05 2022-12-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package with conductive pillars and reinforcing and encapsulating layers
KR20210095442A (ko) 2020-01-23 2021-08-02 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20220017022A (ko) 2020-08-03 2022-02-11 삼성전자주식회사 반도체 패키지
US20220238473A1 (en) * 2021-01-25 2022-07-28 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices and corresponding semiconductor device
TWI814678B (zh) * 2023-02-13 2023-09-01 福懋科技股份有限公司 半導體封裝的製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090273094A1 (en) * 2008-05-02 2009-11-05 Jong-Woo Ha Integrated circuit package on package system
US20100084754A1 (en) * 2007-06-12 2010-04-08 Samsung Electro-Mechanics Co., Ltd Semiconductor package
US20100214759A1 (en) * 2008-05-19 2010-08-26 Texas Instruments Incorporated Integrated Circuit Package Having Integrated Faraday Shield
US20100244222A1 (en) * 2009-03-25 2010-09-30 Chi Heejo Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US20120038064A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die

Family Cites Families (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955523A (en) 1986-12-17 1990-09-11 Raychem Corporation Interconnection of electronic components
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
US5601740A (en) 1993-11-16 1997-02-11 Formfactor, Inc. Method and apparatus for wirebonding, for severing bond wires, and for forming balls on the ends of bond wires
US5455390A (en) 1994-02-01 1995-10-03 Tessera, Inc. Microelectronics unit mounting with multiple lead bonding
US5495667A (en) 1994-11-07 1996-03-05 Micron Technology, Inc. Method for forming contact pins for semiconductor dice and interconnects
DE69737621T2 (de) 1996-10-01 2007-12-20 Matsushita Electric Industrial Co., Ltd., Kadoma Halbleiterelement mit einer Höckerelektrode
US5764486A (en) * 1996-10-10 1998-06-09 Hewlett Packard Company Cost effective structure and method for interconnecting a flip chip with a substrate
US6133072A (en) 1996-12-13 2000-10-17 Tessera, Inc. Microelectronic connector with planar elastomer sockets
US20030215445A1 (en) * 1997-05-23 2003-11-20 Ginette Serrero Methods and compositions for inhibiting the growth of hematopoietic malignant cells
DE19823623A1 (de) 1998-05-27 1999-12-02 Bosch Gmbh Robert Verfahren und Kontaktstelle zur Herstellung einer elektrischen Verbindung
JP4526651B2 (ja) 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP3486872B2 (ja) 2001-01-26 2004-01-13 Ｎｅｃセミコンダクターズ九州株式会社 半導体装置及びその製造方法
KR100422346B1 (ko) 2001-06-12 2004-03-12 주식회사 하이닉스반도체 칩크기 패키지 구조 및 그 제조방법
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US7227095B2 (en) 2003-08-06 2007-06-05 Micron Technology, Inc. Wire bonders and methods of wire-bonding
JP4204989B2 (ja) * 2004-01-30 2009-01-07 新光電気工業株式会社 半導体装置及びその製造方法
US20070108583A1 (en) 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
JP2007165383A (ja) 2005-12-09 2007-06-28 Ibiden Co Ltd 部品実装用ピンを形成したプリント基板
US7993972B2 (en) * 2008-03-04 2011-08-09 Stats Chippac, Ltd. Wafer level die integration and method therefor
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
JP4906462B2 (ja) 2006-10-11 2012-03-28 新光電気工業株式会社 電子部品内蔵基板および電子部品内蔵基板の製造方法
US7898093B1 (en) * 2006-11-02 2011-03-01 Amkor Technology, Inc. Exposed die overmolded flip chip package and fabrication method
US8133762B2 (en) * 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US20080116564A1 (en) * 2006-11-21 2008-05-22 Advanced Chip Engineering Technology Inc. Wafer level package with die receiving cavity and method of the same
US7608921B2 (en) 2006-12-07 2009-10-27 Stats Chippac, Inc. Multi-layer semiconductor package
US20080136004A1 (en) * 2006-12-08 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chip package structure and method of forming the same
US8609463B2 (en) * 2007-03-16 2013-12-17 Stats Chippac Ltd. Integrated circuit package system employing multi-package module techniques
US20080246126A1 (en) * 2007-04-04 2008-10-09 Freescale Semiconductor, Inc. Stacked and shielded die packages with interconnects
KR100909322B1 (ko) * 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
SG148901A1 (en) * 2007-07-09 2009-01-29 Micron Technology Inc Packaged semiconductor assemblies and methods for manufacturing such assemblies
US9330945B2 (en) * 2007-09-18 2016-05-03 Stats Chippac Ltd. Integrated circuit package system with multi-chip module
US7777351B1 (en) * 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US20090140408A1 (en) * 2007-11-30 2009-06-04 Taewoo Lee Integrated circuit package-on-package system with stacking via interconnect
US8035210B2 (en) 2007-12-28 2011-10-11 Stats Chippac Ltd. Integrated circuit package system with interposer
US8035211B2 (en) * 2008-03-26 2011-10-11 Stats Chippac Ltd. Integrated circuit package system with support structure under wire-in-film adhesive
US8030136B2 (en) * 2008-05-15 2011-10-04 Stats Chippac, Ltd. Semiconductor device and method of conforming conductive vias between insulating layers in saw streets
US20100006987A1 (en) * 2008-07-09 2010-01-14 Rajen Murugan Integrated circuit package with emi shield
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US7776655B2 (en) * 2008-12-10 2010-08-17 Stats Chippac, Ltd. Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US7927917B2 (en) * 2009-06-19 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with inward and outward interconnects and method of manufacture thereof
US8021930B2 (en) * 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US8169058B2 (en) * 2009-08-21 2012-05-01 Stats Chippac, Ltd. Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars
US8383457B2 (en) 2010-09-03 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect
US9397050B2 (en) * 2009-08-31 2016-07-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant
US8164158B2 (en) * 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US7867821B1 (en) * 2009-09-18 2011-01-11 Stats Chippac Ltd. Integrated circuit package system with through semiconductor vias and method of manufacture thereof
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8390108B2 (en) * 2009-12-16 2013-03-05 Stats Chippac Ltd. Integrated circuit packaging system with stacking interconnect and method of manufacture thereof
US7928552B1 (en) * 2010-03-12 2011-04-19 Stats Chippac Ltd. Integrated circuit packaging system with multi-tier conductive interconnects and method of manufacture thereof
US8558392B2 (en) * 2010-05-14 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant
US8357564B2 (en) * 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US8105872B2 (en) * 2010-06-02 2012-01-31 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die
US8304296B2 (en) * 2010-06-23 2012-11-06 Stats Chippac Ltd. Semiconductor packaging system with multipart conductive pillars and method of manufacture thereof
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8318541B2 (en) * 2010-08-10 2012-11-27 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
US8354297B2 (en) * 2010-09-03 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming different height conductive pillars to electrically interconnect stacked laterally offset semiconductor die
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8384227B2 (en) 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US8502387B2 (en) * 2010-12-09 2013-08-06 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnection and method of manufacture thereof
US9406658B2 (en) * 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8531021B2 (en) * 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
US8466544B2 (en) 2011-02-25 2013-06-18 Stats Chippac, Ltd. Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP
US9064781B2 (en) * 2011-03-03 2015-06-23 Broadcom Corporation Package 3D interconnection and method of making same
US8883561B2 (en) * 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US8710668B2 (en) * 2011-06-17 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with laser hole and method of manufacture thereof
US8816404B2 (en) * 2011-09-16 2014-08-26 Stats Chippac, Ltd. Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant
US8698297B2 (en) * 2011-09-23 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with stack device
US8716065B2 (en) * 2011-09-23 2014-05-06 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8922013B2 (en) * 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package
US8922005B2 (en) * 2012-04-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US20140057394A1 (en) * 2012-08-24 2014-02-27 Stmicroelectronics Pte Ltd. Method for making a double-sided fanout semiconductor package with embedded surface mount devices, and product made
US9818734B2 (en) * 2012-09-14 2017-11-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
US9601402B2 (en) * 2014-02-14 2017-03-21 Phoenix Pioneer Technology Co., Ltd. Package apparatus and manufacturing method thereof
US9812337B2 (en) * 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9786614B2 (en) * 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100084754A1 (en) * 2007-06-12 2010-04-08 Samsung Electro-Mechanics Co., Ltd Semiconductor package
US20090273094A1 (en) * 2008-05-02 2009-11-05 Jong-Woo Ha Integrated circuit package on package system
US20100214759A1 (en) * 2008-05-19 2010-08-26 Texas Instruments Incorporated Integrated Circuit Package Having Integrated Faraday Shield
US20100244222A1 (en) * 2009-03-25 2010-09-30 Chi Heejo Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof
US20120038064A1 (en) * 2010-08-16 2012-02-16 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970312A (zh) * 2018-09-28 2020-04-07 台湾积体电路制造股份有限公司 封装件及其形成方法
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
CN110970312B (zh) * 2018-09-28 2022-03-04 台湾积体电路制造股份有限公司 封装件及其形成方法

Also Published As

Publication number Publication date
TW201411746A (zh) 2014-03-16
SG2013050265A (en) 2014-04-28
TWI594343B (zh) 2017-08-01
CN103681368B (zh) 2018-01-30
US20140077364A1 (en) 2014-03-20
US10446523B2 (en) 2019-10-15
US9443797B2 (en) 2016-09-13
US20160336299A1 (en) 2016-11-17

Similar Documents

Publication Publication Date Title
CN103681368A (zh) 半导体装置和将线柱形成为fo-wlp中的垂直互连的方法
US9478486B2 (en) Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
CN102376595B (zh) 形成具有导电层和导电通孔的fo-wlcsp的方法和半导体器件
CN102194740B (zh) 半导体器件及其形成方法
CN103681468B (zh) 在Fo-WLCSP中形成双面互连结构的半导体器件和方法
CN102194718B (zh) 半导体器件及其制造方法
CN103681607B (zh) 半导体器件及其制作方法
CN102237281B (zh) 半导体器件及其制造方法
US9515016B2 (en) Semiconductor package and method of forming z-direction conductive posts embedded in structurally protective encapsulant
US8183087B2 (en) Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component
CN102543772B (zh) 结合晶片级不同尺寸半导体管芯的方法和半导体器件
CN102194717B (zh) 半导体器件和在半导体管芯周围形成绝缘层的方法
CN102412197B (zh) 形成具有绝缘环形环的导电tsv的方法和半导体器件
US8110477B2 (en) Semiconductor device and method of forming high-frequency circuit structure and method thereof
CN101989558B (zh) 半导体器件及其制造方法
CN203481192U (zh) 半导体器件
CN103715108A (zh) 半导体装置和将密封剂沉积在嵌入式wlcsp中的方法
TWI523126B (zh) 在包含膠封或包含在具有與晶圓級晶片尺寸封裝的大型陣列中的熱膨脹係數相似的熱膨脹係數的空白晶粒之印刷電路板中形成孔穴的半導體裝置和方法
CN103943553A (zh) 半导体器件和形成具有垂直互连单元的低轮廓扇出式封装的方法
US7897502B2 (en) Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
CN103915353A (zh) 半导体器件以及使用标准化载体形成嵌入式晶片级芯片尺寸封装的方法
CN203288575U (zh) 半导体装置
CN104037124A (zh) 形成用于fo-ewlb中电源/接地平面的嵌入导电层的半导体器件和方法
CN203288584U (zh) 半导体装置
CN203351587U (zh) 半导体器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
EXSB Decision made by sipo to initiate substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Singapore City

Patentee after: STATS ChipPAC Pte. Ltd.

Address before: Singapore City

Patentee before: STATS ChipPAC Pte. Ltd.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20200107

Address after: No. 500, Linjiang Road, Yuecheng District, Shaoxing City, Zhejiang Province

Patentee after: Changdian integrated circuit (Shaoxing) Co.,Ltd.

Address before: Singapore City

Patentee before: STATS ChipPAC Pte. Ltd.