TWI455258B - 內埋元件封裝結構及製造方法 - Google Patents
內埋元件封裝結構及製造方法 Download PDFInfo
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Description
本發明涉及一種內埋元件封裝結構及製造方法,尤其涉及包括金屬彈性組件的內埋元件封裝結構及製造方法。
現有技術中,內埋元件封裝結構是在基板上製造收容槽,將被動元件固定在該收容槽內,再對基板進行封裝。由於需要在基板上製造收容槽,使得基板加工工藝複雜,成本高,不易實現量產。而且被動元件的尺寸需要小於收容槽,因此現有技術的內埋元件封裝結構無法適用全系列規格的被動元件,需要訂制特別外觀的被動元件。
有鑑於此,需提供一種內埋元件封裝結構及製造方法,被動元件內埋於封膠體內,適用全系列規格的被動元件,且制程簡單,能有效降低製造成本。
本發明提供的內埋元件封裝結構,包括基板、至少一個晶片、複數被動元件、複數金屬彈性組件及第一封膠體。該晶片、該等被動元件及該等金屬彈性組件之一端電連接於該基板,該第一封膠體包覆該晶片、該等被動元件及該等金屬彈性組件於該基板上,每一個金屬彈性組件包括金屬彈性件及設於該金屬彈性件之兩端
的第一金屬片及第二金屬片,該第一金屬片固定於該基板並與該基板電連接,該第二金屬片裸露於該第一封膠體之外表面,該第二金屬片在金屬彈性件的彈力作用下可以緊貼模具,以消除該第二金屬片之間的高度誤差,以保證第一封膠體之外表面的平整度,該等金屬彈性組件之第二金屬片相互連接形成連續的金屬屏蔽罩以屏蔽該內埋元件封裝結構,防止電磁干擾。
優選地,該第一金屬片及該第二金屬片之邊緣為斜面。
優選地,該金屬彈性件為彈簧。
優選地,該晶片透過導熱膠與該金屬屏蔽罩固定連接,該晶片借助該金屬屏蔽罩散熱。
本發明提供的內埋元件封裝結構的製造方法,用於將至少一個晶片及複數被動元件內埋於第一封膠體內。該內埋元件封裝結構的製造方法包括:將該晶片、該等被動元件及複數金屬彈性組件之一端固定於基板並與該基板電連接,該等金屬彈性組件包括金屬彈性件及設於該金屬彈性件之兩端的第一金屬片及第二金屬片,該第一金屬片固定於該基板並與該基板電連接;利用注膠成型技術固定及填埋該晶片、該等被動元件及該等金屬彈性組件以形成第一封膠體,該等金屬彈性組件之第二金屬片裸露於該第一封膠體之外表面,該第二金屬片在金屬彈性件的彈力作用下可以緊貼模具,以消除該第二金屬片之間的高度誤差,以保證第一封膠體之外表面的平整度;及蝕刻該等金屬彈性組件之第二金屬片的表面殘留的膠體以使該等金屬彈性組件之第二金屬片完全裸露於該第一封膠體之外表面,並使該等金屬彈性組件之第二金屬片相互連接形成連續的金屬屏蔽罩以屏蔽該內埋元件封裝結構,防止電
子干擾。
優選地,該晶片透過導熱膠與該金屬屏蔽罩固定連接,該晶片借助該金屬屏蔽罩散熱。
相較於現有技術,本發明的內埋元件封裝結構將被動元件內埋於封膠體內,並透過設置金屬彈性組件將基板的輸入/輸出接口導出至封膠體之外表面。由於金屬彈性組件在封裝過程中可適應不同的高度變化,故此種封裝結構適用全系列規格的被動元件,無需訂制特殊外觀的被動元件,從而降低了封裝產品的成本。
100‧‧‧內埋元件封裝結構
10‧‧‧基板
11‧‧‧第一表面
12‧‧‧第二表面
13‧‧‧第一電路層
14‧‧‧第二電路層
15‧‧‧貫孔
20‧‧‧被動元件
30‧‧‧金屬彈性組件
31‧‧‧金屬彈性件
32‧‧‧第一金屬片
33‧‧‧第二金屬片
34‧‧‧斜面
41‧‧‧晶片
42‧‧‧電子元件
50‧‧‧第一封膠體
51‧‧‧外表面
60‧‧‧第二封膠體
71‧‧‧錫膏
72‧‧‧膠體
73‧‧‧導熱膠
74‧‧‧錫球
80‧‧‧金屬線
90‧‧‧金屬屏蔽罩
圖1係本發明一具體實施方式的內埋元件封裝結構截面示意圖。
圖2係圖1中內埋元件封裝結構另一方向截面示意圖,該內埋元件封裝結構具有電磁屏蔽結構。
圖3係圖2所示內埋元件封裝結構示意圖,該內埋元件封裝結構具有電磁屏蔽及散熱結構。
圖4係將晶片、被動元件及金屬彈性組件固定於基板的示意圖。
圖5係圖1中內埋元件封裝結構之基板的第二表面封裝電子元件之示意圖。
請同時參照圖1及圖2。本發明之內埋元件封裝結構100包括基板10、複數被動元件20、複數金屬彈性組件30、至少一個晶片41及第一封膠體50。該等被動元件20、晶片41及金屬彈性組件30之一端電連接於該基板10。該第一封膠體50包覆該等被動元件20、金屬彈性組件30及晶片41於該基板10之上。該等金屬彈性組件30之
另一端裸露於該第一封膠體50之外表面51。該基板10之輸入/輸出接口透過該等金屬彈性組件30導出至第一封膠體50之外表面51。也就是說,金屬彈性組件30與設於基板10上的電路層電連接,透過金屬彈性組件30裸露於該第一封膠體50之外表面51的部分,實現基板10與外界電路之間的電連接。
基板10包括第一表面11、與該第一表面11相對設置的第二表面12及貫通該第一表面11及第二表面12的複數貫孔15。該第一表面11設有第一電路層13,該第二表面12設有第二電路層14,該第一電路層13及該第二電路層14透過該貫孔15實現電連接。本實施方式中,該基板10之輸入/輸出接口(未圖示)設於該基板10之第二表面12的第二電路層14之上。
該等被動元件20透過第一封膠體50固定於該基板10之第一表面11並透過錫膏71與該基板10之第一電路層13電連接。該晶片41透過膠體72與該基板10之第一電路層13固定,並透過金屬導線80與該基板10第一電路層13實現電連接。當然,晶片41也可以透過錫球74與該基板10之第一電路層13直接固定並實現電連接,如圖3所示。
金屬彈性組件30之一端透過錫膏71與該基板10固定並與基板10之第一電路層13電連接,另一端裸露於第一封膠體50之外表面51。由於基板10之輸入/輸出接口位於基板10之第二表面12的第二電路層14,該基板10之輸入/輸出接口透過貫孔15從第二電路層14被導入到第一電路層13,並透過金屬彈性組件30從該第一電路層13導出至第一封膠體50之外表面51。由於該基板10之輸入/輸出接口被導出至第一封膠體50之外表面51,基板10之第二表面12無
需與外部電路連接,因此,基板10之第二表面12可以封裝其它電子元件42實現堆疊式封裝,從而可以減小產品的尺寸,如圖5所示。電子元件42固定於基板10之第二表面12並與基板10之第二電路層14電連接。第二封膠體60包覆該電子元件42。本實施方式中,該第一及第二封膠體50、60為環氧樹脂。
本發明之內埋元件封裝結構100將被動元件20內埋第一封膠體50內,並透過設置金屬彈性組件30將位於基板10之第二表面12的輸入/輸出接口導出至第一封膠體50之外表面51,以實現內埋元件封裝結構。由於金屬彈性組件30在封裝過程中可適應被動元件20不同的高度變化,故此種封裝結構100適用全系列規格的被動元件20,無需訂制特殊外觀的被動元件20,從而降低了封裝產品的成本。同時,該基板10之第二表面12無需與外部電路連接,可以封裝其它電子元件42,實現堆疊式封裝,以減小產品的尺寸。
本實施方式中,每一個金屬彈性組件30包括金屬彈性件31及分別設於金屬彈性件31之兩端的第一金屬片32及第二金屬片33。第一金屬片32固定於該基板10之第一表面11並與該基板10之第一電路層13電連接,第二金屬片33裸露於該第一封膠體50之外表面51。第一封膠體50在注塑成型過程中,該等金屬彈性組件30由於該金屬彈性件31的彈性不會因為注塑模具的壓力而被損壞。同時,該第二金屬片33在金屬彈性件31的彈性作用下與注塑模具之上模具始終保持緊密接觸,不但可以防止環氧樹脂覆蓋該第二金屬片33以使該第二金屬片33裸露於第一封膠體50之外表面51,還可以消除該第二金屬片33之間的高度誤差,保證第一封膠體50之外表面51的平整度。本實施方式中,金屬彈性件31為彈簧,第一金屬片
32及第二金屬片33之材質為銅,其表面均鍍錫。當然,在本發明的其他實施方式中,金屬彈性件31可以為金屬彈片,第一金屬片32及第二金屬片33也可以為其它金屬材質,其表面亦可以根據實際需求鍍金或鍍銀。
本實施方式中,該等金屬彈性組件30之第一金屬片32及第二金屬片33之邊緣均為斜面34,該斜面34的設置有利於環氧樹脂與該金屬片32、33緊密結合,防止金屬彈性組件30鬆動,以增強內埋元件封裝結構100的性能穩定性。
請參照圖2。作為本發明的改進,該等金屬彈性組件30之第二金屬片33相互連接形成連續的金屬屏蔽罩90。該金屬屏蔽罩90遮蔽該等被動元件20及晶片41並與基板10之電路層13、14電連接,從而對內埋元件封裝結構100實現電磁屏蔽功能。
請參照圖3。作為本發明的進一步改進,本發明之內埋元件封裝結構100之晶片41透過導熱膠73與該金屬屏蔽罩90固定連接,從而該晶片41可借助該金屬屏蔽罩90散熱。
本發明之內埋元件封裝結構製造方法用於將至少一個晶片41及複數被動元件20內埋於第一封膠體50內。該內埋元件封裝結構製造方法包括如下步驟。
請參閱圖4,將該晶片41、該等被動元件20及複數金屬彈性組件30之一端利用表面貼裝技術(SMT)固定於該基板10並與該基板10實現電連接。本實施方式中,被動元件20透過錫膏71焊接於該基板10之第一表面11並與第一電路層13電連接,金屬彈性組件30透過第一金屬片32與基板10之第一表面11固定。該第一金屬片32透
過錫膏71焊接於該基板10之第一表面11並與第一電路層13電連接。晶片41透過錫球74與基板10之第一表面11固定並實現電連接。在其它實施方式中,晶片41透過膠體72與基板固定並透過金屬線80與基板10實現電連接。
利用注膠成型技術固定及填埋該等被動元件20、該晶片41及該等金屬彈性組件30以形成第一封膠體50,該等金屬彈性組件30之另一端裸露於該第一封膠體50之外表面51。本實施方式中,該等金屬彈性組件30之另一端,即第二金屬片33裸露於該第一封膠體50之外表面51。位於基板10之第二表面12的輸入/輸出接口透過基板10之貫孔15從第二電路層14被導入到第一電路層13,並透過金屬彈性組件30從該第一電路層13導出至第一封膠體50之外表面51。
蝕刻金屬彈性組件30之另一端的表面殘留的環氧樹脂以使彈性元件30之另一端的表面完全裸露於該第一封膠體50之外表面51。本實施方式中,蝕刻金屬彈性組件30之第二金屬片33之表面殘留的環氧樹脂以使第二金屬片33之表面完全裸露於該第一封膠體50之外表面51。
在金屬彈性組件30之另一端的表面電鍍錫。當然根據實際需要,若不需要鍍錫,該步驟亦可以省略。
本發明的內埋元件封裝結構製造方法利用表面貼裝技術(SMT)及注膠成型技術將被動元件20內埋於封膠體內,並透過金屬彈性組件30將基板之輸入/輸出接口導出至該第一封膠體50之外表面51以實現內埋元件封裝結構,制程簡單,製造成本低。
綜上所述,本創作符合發明專利要件,爰依法提出專利申請。惟,以上該僅為本創作之較佳實施例,舉凡熟悉本案技藝之人士,在爰依本創作精神所作之等效修飾或變化,皆應涵蓋於以下之申請專利範圍內。
100‧‧‧內埋元件封裝結構
10‧‧‧基板
11‧‧‧第一表面
12‧‧‧第二表面
13‧‧‧第一電路層
14‧‧‧第二電路層
15‧‧‧貫孔
20‧‧‧被動元件
30‧‧‧金屬彈性組件
31‧‧‧金屬彈性件
32‧‧‧第一金屬片
33‧‧‧第二金屬片
34‧‧‧斜面
50‧‧‧第一封膠體
51‧‧‧外表面
71‧‧‧錫膏
Claims (6)
- 一種內埋元件封裝結構,包括基板、至少一個晶片、複數被動元件及第一封膠體,其改良在於,該內埋元件封裝結構還包括複數金屬彈性組件,該晶片、該等被動元件及該等金屬彈性組件之一端電連接於該基板,該第一封膠體包覆該晶片、該等被動元件及該等金屬彈性組件於該基板之上,每一個金屬彈性組件包括金屬彈性件及設於該金屬彈性件之兩端的第一金屬片及第二金屬片,該第一金屬片固定於該基板並與該基板電連接,該第二金屬片裸露於該第一封膠體之外表面,該第二金屬片在金屬彈性件的彈力作用下可以緊貼模具,以消除該第二金屬片之間的高度誤差,以保證第一封膠體之外表面的平整度,該等金屬彈性組件之第二金屬片相互連接形成連續的金屬屏蔽罩以屏蔽該內埋元件封裝結構,防止電磁干擾。
- 如申請專利範圍第1項所述的內埋元件封裝結構,其改良在於,該第一金屬片及該第二金屬片之邊緣為斜面。
- 如申請專利範圍第1項所述的內埋元件封裝結構,其改良在於,該金屬彈性件為彈簧。
- 如申請專利範圍第1項所述的內埋元件封裝結構,其改良在於,該晶片透過導熱膠與該金屬屏蔽罩固定連接,該晶片借助該金屬屏蔽罩散熱。
- 一種內埋元件封裝結構的製造方法,用於將至少一個晶片及複數被動元件內埋於第一封膠體內,其改良在於,該內埋元件封裝結構的製造方法包括:將該晶片、該等被動元件及複數金屬彈性組件固定於基板並與該基板電連接,該等金屬彈性組件包括金屬彈性件及設於該金屬彈性件之兩端的 第一金屬片及第二金屬片,該第一金屬片固定於該基板並與該基板電連接;利用注膠成型技術固定及填埋該晶片、該等被動元件及該等金屬彈性組件以形成第一封膠體,該等金屬彈性組件之第二金屬片裸露於該第一封膠體之外表面,該第二金屬片在金屬彈性件的彈力作用下可以緊貼模具,以消除該第二金屬片之間的高度誤差,以保證第一封膠體之外表面的平整度;及蝕刻該等金屬彈性組件之第二金屬片的表面殘留的膠體以使該等金屬彈性組件之第二金屬片完全裸露於該第一封膠體之外表面,並使該等金屬彈性組件之第二金屬片相互連接形成連續的金屬屏蔽罩以屏蔽該內埋元件封裝結構,防止電子干擾。
- 如申請專利範圍第5項所述的內埋元件封裝結構的製造方法,其改良在於,該晶片透過導熱膠與該金屬屏蔽罩固定連接,該晶片借助該金屬屏蔽罩散。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5297006A (en) * | 1991-08-13 | 1994-03-22 | Fujitsu Limited | Three-dimensional multi-chip module |
US6548326B2 (en) * | 1999-06-21 | 2003-04-15 | Shinko Electronic Industries Co., Ltd. | Semiconductor device and process of producing same |
US20090085138A1 (en) * | 2007-09-28 | 2009-04-02 | Samsung Electro-Mechanics Co., Ltd. | Glass cap molding package, manufacturing method thereof and camera module |
US20100117212A1 (en) * | 2006-02-28 | 2010-05-13 | Micron Technology, Inc. | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
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US20020004320A1 (en) * | 1995-05-26 | 2002-01-10 | David V. Pedersen | Attaratus for socketably receiving interconnection elements of an electronic component |
US7109410B2 (en) * | 2003-04-15 | 2006-09-19 | Wavezero, Inc. | EMI shielding for electronic component packaging |
JP4559757B2 (ja) * | 2004-03-18 | 2010-10-13 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7564066B2 (en) * | 2005-11-09 | 2009-07-21 | Intel Corporation | Multi-chip assembly with optically coupled die |
US8373264B2 (en) * | 2008-07-31 | 2013-02-12 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture thereof |
JP2011530190A (ja) | 2008-08-04 | 2011-12-15 | クラスタード システムズ カンパニー | 接点を冷却した電子機器匡体 |
CN201336417Y (zh) * | 2008-12-12 | 2009-10-28 | 鸿富锦精密工业(深圳)有限公司 | 弹片装置 |
US8477499B2 (en) * | 2009-06-05 | 2013-07-02 | Laird Technologies, Inc. | Assemblies and methods for dissipating heat from handheld electronic devices |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5297006A (en) * | 1991-08-13 | 1994-03-22 | Fujitsu Limited | Three-dimensional multi-chip module |
US6548326B2 (en) * | 1999-06-21 | 2003-04-15 | Shinko Electronic Industries Co., Ltd. | Semiconductor device and process of producing same |
US20100117212A1 (en) * | 2006-02-28 | 2010-05-13 | Micron Technology, Inc. | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US20090085138A1 (en) * | 2007-09-28 | 2009-04-02 | Samsung Electro-Mechanics Co., Ltd. | Glass cap molding package, manufacturing method thereof and camera module |
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