JP2002076252A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2002076252A
JP2002076252A JP2000263015A JP2000263015A JP2002076252A JP 2002076252 A JP2002076252 A JP 2002076252A JP 2000263015 A JP2000263015 A JP 2000263015A JP 2000263015 A JP2000263015 A JP 2000263015A JP 2002076252 A JP2002076252 A JP 2002076252A
Authority
JP
Japan
Prior art keywords
chip
substrate
semiconductor
semiconductor device
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2000263015A
Other languages
English (en)
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2000263015A priority Critical patent/JP2002076252A/ja
Priority to KR10-2001-0052047A priority patent/KR100426825B1/ko
Priority to US09/942,313 priority patent/US6600221B2/en
Publication of JP2002076252A publication Critical patent/JP2002076252A/ja
Abandoned legal-status Critical Current

Links

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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

(57)【要約】 【課題】 基板とチップの熱膨張率差を吸収して、信頼
性の高い半導体装置を提供する。 【解決手段】 基板１上に複数の半導体チップ２、３、
４を積層させた半導体装置において、前記基板１上に前
記複数の半導体チップの内のチップサイズの最も小さい
半導体チップ２を組み付け、この半導体チップ２上に順
にチップサイズの大きな半導体チップ２、３を積層し、
この積層した半導体チップ２、３、４のボンディングパ
ッド２ａ、３ａ、４ａ直上に当たる前記基板１の部位に
は、ボンディングワイヤー５挿通用の貫通孔６を設け、
前記ボンディングワイヤー５は、前記貫通孔６を挿通せ
しめ、且つ、前記半導体チップ３ｓ、４ｓの表面に対し
て、ほぼ垂直をなすように配線したことを特徴とする。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、半導体装置に係わ
り、特に、複数の半導体チップを積層した半導体装置に
関する。
【０００２】
【従来の技術】図２に示した半導体装置は、特開平１０
−８４０７６号公報に示された半導体装置である。
【０００３】この半導体装置は、小チップ１０、大チッ
プ２０と、内部端子３３と外部端子３６とが電気配線３
８で接続された配線基板３０と、チップ側端子４３と基
板側端子４６とが電気配線４７で接続された補助枠４０
とから構成され、小チップ１０は、配線基板３０の中央
部に配置されて、その電極パッド１３が、半田ボール１
４を介して配線基板３０の内部端子３３に接続し、ま
た、補助枠４０は、小チップ１０の外周に嵌合されて、
補助枠４０の電極パッド４６は、半田ボール４８を介し
て配線基板３０の内部端子３３に接続されている。更
に、大チップ２０は、小チップ１０と及び補助枠４０上
に重ねられて、その電極パッド２３が、補助枠４０のチ
ップ側端子４３に半田ボール２４を介して接続する構造
になっている。
【０００４】しかし、上記した半導体装置は、基板３０
と大チップ２０の接続を補助枠４０を用いて行っている
が、この補助枠４０は、製造が困難なのでコストが高
い。更に、上記した半導体装置は、チップと基板の接合
力が大きく、このため、基板とチップの熱膨張率差に基
づき生じる基板とチップの熱応力を逃がすことができに
くく、温度サイクル信頼性が低いという欠点があった。
【０００５】又、図３に示す基板７０上に半導体チップ
７１、７２、７３を順に積層した積層型半導体装置の場
合、基板７０にスルーホール７４を設ける必要であり、
このため、基板７０の製造コストが高くなるという欠点
がある。
【０００６】
【発明が解決しようとする課題】本発明の目的は、上記
した従来技術の欠点を改良し、特に、基板とチップの熱
膨張率差を吸収して、信頼性の高い半導体装置を提供す
ると共に、製造コストが安価な新規な半導体装置を提供
することにある。
【０００７】
【課題を解決するための手段】本発明は上記した目的を
達成するため、基本的には、以下に記載されたような技
術構成を採用するものである。
【０００８】即ち、本発明に係わる半導体装置は、基板
上に複数の半導体チップを積層させた半導体装置におい
て、前記基板上に前記複数の半導体チップの内のチップ
サイズの最も小さい半導体チップを組み付け、この半導
体チップ上に順にチップサイズの大きな半導体チップを
積層し、この積層した半導体チップのボンディングパッ
ド直上に当たる前記基板の部位には、ボンディングワイ
ヤー挿通用の貫通孔を設け、前記ボンディングワイヤー
は、前記貫通孔を挿通せしめ、且つ、前記半導体チップ
の表面に対して、ほぼ垂直をなすように配線したことを
特徴とするものである。
【０００９】
【発明の実施の形態】本発明に係わる半導体装置は、基
板上に複数の半導体チップを積層させた半導体装置にお
いて、前記基板上に前記複数の半導体チップの内のチッ
プサイズの最も小さい半導体チップを組み付け、この半
導体チップ上に順にチップサイズの大きな半導体チップ
を積層し、この積層した半導体チップのボンディングパ
ッド直上に当たる前記基板の部位には、ボンディングワ
イヤー挿通用の貫通孔を設け、前記ボンディングワイヤ
ーは、前記貫通孔を挿通せしめ、且つ、前記半導体チッ
プの表面に対して、ほぼ垂直をなすように配線したこと
を特徴とするものである。
【００１０】このような構造の場合、基板とチップの熱
膨張率差に基づき生じる基板及びチップの熱応力が小さ
いから、温度サイクル信頼性が向上し、しかも、安価に
製造できる優れた特徴を有する。
【００１１】
【実施例】以下に、本発明に係わる半導体装置の具体例
を図面を参照しながら詳細に説明する。
【００１２】図１は、本発明に係わる半導体装置の具体
例を示す断面図であって、この図１には、基板１上に複
数の半導体チップ２、３、４を積層させた半導体装置に
おいて、前記基板１上に前記複数の半導体チップの内の
チップサイズの最も小さい半導体チップ２を組み付け、
この半導体チップ２上に順にチップサイズの大きな半導
体チップ２、３を積層し、この積層した半導体チップ
２、３、４のボンディングパッド２ａ、３ａ、４ａ直上
に当たる前記基板１の部位には、ボンディングワイヤー
５挿通用の貫通孔６を設け、前記ボンディングワイヤー
５は、前記貫通孔６を挿通せしめ、且つ、前記半導体チ
ップ３ｓ、４ｓの表面に対して、ほぼ垂直をなすように
配線したことを特徴とする半導体装置が示されている。
【００１３】以下に、本発明の半導体装置の具体例を更
に詳細に説明する。
【００１４】ガラスエポキシ基板（もしくはテープ基板
もしくはセラミック基板）１のはんだボール７を搭載接
合する面には、銅等の導電性金属からなる配線８が形成
され、また、ガラスエポキシ基板１上の配線８にワイヤ
ーボンディングするため、ガラスエポキシ基板１に貫通
孔６を設けている。
【００１５】図では、半導体チップを三つ重ねている
が、二つでも、或いは、三つ以上の複数個を積み重ねて
接合してもよい。各チップのサイズはそれぞれ異なり、
チップサイズの小さいものから順に、基板１上へ絶縁性
のエポキシ樹脂とアクリルゴムの混合接着剤９を用いて
接合する。チップを接合する位置は、チップの中心と基
板の中心とを一致させるように一般的には接合するが、
偏心していてもよい。チップは回路が形成されている面
を基板１側へ向けて接合し、各チップ２、３、４のパッ
ド２ａ、３ａ、４ａから基板１の貫通孔６を通して基板
１へワイヤーボンディングを行う。ワイヤーボンディン
グは、各パッドから基板１上の配線８へ最短距離で配線
するが、パッドや配線のレイアウト上、困難であれば長
めに結線しても良い。
【００１６】図１では、最小チップ２のパッド２ａは、
チップ２の中心付近に位置しており、２番目３番目のチ
ップ３、４は、それぞれチップの周辺にパッド３ａ、４
ａが形成されている。最小チップ２のパッド位置２ａ
は、中心付近でも周辺でもよいが、２番目３番目のチッ
プでは、周辺部にパッドを位置させなければならない。
【００１７】チップ全体と基板１の貫通孔６付近を覆う
ように金型にてエポキシ樹脂１０にて封入する。
【００１８】なお、最外側の最もサイズの大きいチップ
４の裏面は樹脂封入せず、露出させて、チップからの放
熱効果を上げている。そして、基板１に、はんだボール
７を搭載して、本発明の半導体装置を完成させる。
【００１９】
【発明の効果】本発明に係わる半導体装置は、上述のよ
うに構成したので、以下のような効果を奏する。 （１）基板が片面配線のため、基板を製造する製造工程
が少なく、製造コストが安くなる。また、片面配線のた
め、基板に表裏配線を結ぶ微細な貫通孔が不要となり、
基板製造コストが安くなる。 （２）ワイヤが短いので、ワイヤコストが安い。 （３）チップで一番小さいものから順に基板に接合搭載
するために、基板とチップの熱膨張率差をエポキシ樹脂
にて緩和でき、温度サイクル信頼性が向上する。
【図面の簡単な説明】
【図１】本発明に係わる半導体装置を示す断面図であ
る。
【図２】従来の半導体装置の断面図である。
【図３】従来の他の半導体装置の断面図である。
【符号の説明】
１ 基板 ２、３、４ 半導体チップ ５ ワイヤー ６ 貫通孔 ７ 半田ボール ８ 基板上の配線 ９ 接着剤 １０ 封止樹脂

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】 基板上に複数の半導体チップを積層させ
    た半導体装置において、 前記基板上に前記複数の半導体チップの内のチップサイ
    ズの最も小さい半導体チップを組み付け、この半導体チ
    ップ上に順にチップサイズの大きな半導体チップを積層
    し、この積層した半導体チップのボンディングパッド直
    上に当たる前記基板の部位には、ボンディングワイヤー
    挿通用の貫通孔を設け、前記ボンディングワイヤーは、
    前記貫通孔を挿通せしめ、且つ、前記半導体チップの表
    面に対して、ほぼ垂直をなすように配線したことを特徴
    とする半導体装置。
JP2000263015A 2000-08-31 2000-08-31 半導体装置 Abandoned JP2002076252A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000263015A JP2002076252A (ja) 2000-08-31 2000-08-31 半導体装置
KR10-2001-0052047A KR100426825B1 (ko) 2000-08-31 2001-08-28 반도체 장치
US09/942,313 US6600221B2 (en) 2000-08-31 2001-08-29 Semiconductor device with stacked semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000263015A JP2002076252A (ja) 2000-08-31 2000-08-31 半導体装置

Publications (1)

Publication Number Publication Date
JP2002076252A true JP2002076252A (ja) 2002-03-15

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Country Link
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