CN100334726C - 开窗型多芯片半导体封装件 - Google Patents

开窗型多芯片半导体封装件 Download PDF

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CN100334726C
CN100334726C CNB021435774A CN02143577A CN100334726C CN 100334726 C CN100334726 C CN 100334726C CN B021435774 A CNB021435774 A CN B021435774A CN 02143577 A CN02143577 A CN 02143577A CN 100334726 C CN100334726 C CN 100334726C
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曾维桢
陈锦德
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Siliconware Precision Industries Co Ltd
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Abstract

一种开窗型多芯片半导体封装件，接置至少一第一芯片及第二芯片在开设有开孔的基板的一表面上，并堆栈至少一第三芯片在第一芯片与第二芯片上，形成在该开孔中的焊线使各该芯片彼此形成电性连接关系且电性连接至基板，且该芯片是以一第一封装胶体包覆，并令一第二封装胶体填充至该开孔中以包覆该焊线。由于该芯片设置在基板的同一表面上，且其上布设的导电结构(如焊垫)朝同一方向列置，故可缩短焊线长度、增进芯片电性传递速度，能改善整个封装件的电性及运行功效。

Description

开窗型多芯片半导体封装件
技术领域
本发明是关于一种半导体封装件，特别是关于一种开窗型(Window-Type)多芯片半导体封装件，它是利用一开设有开孔的基板作为芯片承载件(Chip Carrier)，令多个芯片堆栈在该基板上。
背景技术
开窗型半导体封装件是采用先进的封装技术，其特点是，在基板开设有至少一贯穿基板的开孔，使芯片以覆盖该开孔的方式接置在基板上，并通过形成在该开孔中的焊线，电性连接至该基板。这种封装结构的优点是可缩短焊线长度，有效增进芯片与基板间的电性传递及性能。
美国专利第6,218,731号案发明的开窗型半导体封装件1，如图4所示，包括一基板10，开设有一贯穿基板10的开孔100；一芯片11，接置在基板10的上表面101上，使布设在芯片11的作用表面110的焊垫111外露在开孔100中；多条形成在开孔100中的焊线12，焊接至芯片11的焊垫111，用以电性连接芯片11的作用表面110至基板10的下表面102；一形成在基板10的上表面101上的第一封装胶体13，用来包覆芯片11；一形成在基板10的下表面102上的第二封装胶体14，用来填充开孔100并包覆焊线12；以及多个焊球15，植接在基板10的下表面102上、不影响第二封装胶体14的区域，焊球15是作为半导体封装件1与外界电性连接的媒介。
为增加运行速度及电性功能，台湾专利公告第407354号案发明的开窗型双芯片半导体封装件1′，如图5所示，是在上述半导体封装件1的芯片11(下称＂第一芯片＂)上，以背对背方式堆栈一第二芯片16，使第二芯片16的非作用表面160与第一芯片11的非作用表面112粘接。第二芯片16的作用表面161是相对于第一芯片11的作用表面110，使布设在第二芯片16的作用表面161上的焊垫162也与第一芯片11的焊垫111相对地列置，使得电性连接第二芯片16的焊垫162至基板10的上表面101的焊线12′，比电性连接第一芯片11的焊垫111至基板10的下表面102的焊线12长度增长许多。这种结构有诸多缺点，过长的焊线12′会延迟第二芯片16的电性传递速度，使第二芯片16的运作速度无法与第一芯片11匹配；再者，以背对背方式堆栈的第一芯片11与第二芯片16使其作用表面110、161上的电子器件与电路(未图标)成相对布设关系(焊垫位置不兼容“Pin to Pin Incompatible”)，故无法堆栈相同的芯片。
美国专利第6,281,578号案发明的开窗型多芯片(三芯片)半导体封装件1＂，如图6所示，是在基板10的上表面101上接置有第一芯片11及第二芯片16，其中第一芯片11与第二芯片16间以开孔100间隔而分置在开孔100相对的两侧；基板10的下表面102上接置有第三芯片17，使布设在第三芯片17的作用表面170上的焊垫171外露在开孔100中，使得该焊垫171可与焊线12＂焊接，令第三芯片17可通过焊线12＂电性连接至基板10及第二芯片16，同时，第一芯片11也可通过焊线12”电性连接至第二芯片16、基板10；再者，基板10结合有多条导脚18，以使该芯片11、16、17能够与外界装置(如印刷电路板，未图标)电性连接。此半导体封装件1＂的三个芯片11、16、17都以其作用表面110、160、170朝上(Face-Up)的方式与基板10接合，因此能够摒弃上述以背对背方式堆栈芯片造成的缺点。然而，由于该芯片11、16、17分置在基板10的上、下表面101、102上，使焊线长度无法有效缩短，例如连接第二芯片16、第三芯片17间的焊线12＂长度较一般焊线长度要长，故难以大幅提升电性传递功效。
其它相关现有技术，如美国专利第6,265,763及6,414,396号案等，也提供了开窗型多芯片半导体封装结构；然上述诸多封装结构都不能在基板的同一表面上堆栈多个芯片，因此达不到缩短焊线长度、改善整体封装结构的效能。
发明内容
本发明的目的在于提供一种开窗型多芯片半导体封装件，使多个芯片堆栈在开设有开孔的基板的同一表面上，使芯片上所布设的导电结构(如焊垫)朝同一方向排列，以缩短焊线长度、增进芯片电性传递速度，从而能有效改善整体封装件的电性及运行效率。
本发明的另一目的在于提供一种开窗型多芯片半导体封装件，可堆栈多个具有中心焊垫的芯片在开设有开孔的基板的同一表面上。
为达成上述目的，本发明一种开窗型多芯片半导体封装件，包括：一基板，具有一上表面及一相对的下表面，该基板开设有至少一贯穿该上、下表面的开孔；至少一第一芯片及一第二芯片，各该芯片具有一作用表面及一相对的非作用表面，使该第一芯片与第二芯片的作用表面分别接置在该基板的上表面上，并使该第一芯片与第二芯片分别部分地自该开孔相对的两侧突伸在该开孔中，且该第一芯片与第二芯片间形成有一间隙，令布设在该第一芯片与第二芯片的作用表面上的焊垫借该基板的开孔外露；至少一第三芯片，具有一作用表面及一相对的非作用表面，使该第三芯片的作用表面接置在该第一芯片与第二芯片的非作用表面上，并遮盖该间隙，令布设在该第三芯片的作用表面上的焊垫借助该间隙外露；所述芯片皆设置于基板的同一表面上，所述芯片所布设的焊垫皆朝同一方向列置且设置于所述芯片中心部位；多条第一焊线，用以电性连接该第三芯片至该第一芯片与第二芯片；多条第二焊线，用以分别电性连接该第一芯片与第二芯片至该基板的下表面；多条第三焊线，用以电性连接该第三芯片至该基板的下表面；一第一封装胶体，形成在该基板的上表面上，用以包覆该第一芯片、第二芯片与第三芯片；一第二封装胶体，形成在该基板的下表面上并填充至该开孔及间隙中，用以包覆该第一焊线、第二焊线与第三焊线；以及多个焊球，植接在该基板的下表面上、不影响该第二封装胶体的区域。
上述封装结构，由于第一芯片、第二芯片与第三芯片均设置在基板的上表面上，且各芯片的作用表面上所布设的焊垫等供电性连接用的导电结构也都朝同一方向(即朝向基板的方向)列置，因此能缩短作为电性连接媒介的焊线的长度、增进芯片的电性传递速度，改善整个半导体封装件的电性及运行效率。再有，第一芯片、第二芯片与第三芯片的焊垫能够分别设置在各芯片的中心部位，该具有中心焊垫的芯片可以是动态随机存取内存(Dynamic Random Access Memory，DRAM)芯片，故上述封装结构能够达到同时堆栈三个具有中心焊垫的芯片在基板的同一表面(上表面)上的功能。
附图说明
为让本发明的上述及其它目的、特征以及优点能更明显易懂，将与较佳实施例，并配合附图，详细说明本发明的实施例，附图的内容简述如下：
图1是本发明的实施例1的半导体封装件的剖视图；
图2是本发明的实施例2的半导体封装件的剖视图；
图3是本发明的实施例3的半导体封装件的剖视图；
图4是美国专利第6,218,731号案的半导体封装件的剖视图；
图5是台湾专利公告第407354号案的半导体封装件的剖视图；以及
图6是美国专利第6,281,578号案的半导体封装件的剖视图。
具体实施方式
以下配合图1至图3详细说明本发明的开窗型多芯片半导体封装件的实施例。
实施例1
图1显示本发明的实施例1的半导体封装件2。如图所示，该半导体封装件2是一以基板20作为芯片承载件的封装结构，该基板20具有一上表面200及一相对的下表面201，并开设有至少一贯穿上、下表面200、201的开孔202。基板20主要由现有树脂材料如环氧树脂(EpoxyResin)、聚酰亚胺(Polyimide)、BT树脂、FR-4树脂等制成。
至少一第一芯片21及一第二芯片22各具有一布设有电子器件与电路(未图标)的作用表面210、220及一相对的非作用表面211、221。第一芯片21与第二芯片22的作用表面210、220是分别接置在基板20的上表面200上，且第一芯片21与第二芯片22分别部分地自基板20的开孔202相对的两侧突伸在该开孔202中，以使第一芯片21与第二芯片22间形成有一间隙G，令布设在第一芯片21与第二芯片22的作用表面210、220上的焊垫(Bond Pad)212、222，可借该开孔202外露以进行后续焊线(Wire-Bonding)作业。如图1所示，第一芯片21与第二芯片22的焊垫212、222分别设置在芯片中心部位，该具有中心焊垫212、222的第一芯片21与第二芯片22可以是动态随机存取内存(Dynamic Random Access Memory，DRAM)芯片；第一芯片21的厚度与该第二芯片22的厚度相同时效果较好。
至少一第三芯片23具有一作用表面230及一相对的非作用表面231。第三芯片23是堆栈在第一芯片21与第二芯片22上，使第三芯片23的作用表面230接置在第一芯片21与第二芯片22的非作用表面211、221上，并遮盖第一芯片21与第二芯片22之间的间隙G。令布设在第三芯片23的作用表面230上的焊垫232，可借由该间隙G外露以进行后续焊线作业。如图1所示，第三芯片23可为动态随机存取内存芯片，使其焊垫232能够设置在芯片中心部位。
多条第一焊线24，例如金线，是安置在第一芯片21与第二芯片22之间的间隙G及基板20的开孔202中，并焊接至第三芯片23的焊垫232及第一芯片21与第二芯片22的焊垫212、222，令第三芯片23能够借第一焊线24电性连接至第一芯片21与第二芯片22。
多条第二焊线25，例如金线，是安置在基板20的开孔202中，并焊接至第一芯片21与第二芯片22的焊垫212、222及布设在基板20的下表面201上的焊指(Bond Finger)203上，令第一芯片21与第二芯片22能够分别借第二焊线25电性连接至基板20的下表面201。
多条第三焊线26，例如金线，是安置在第一芯片21与第二芯片22之间的间隙G及基板20的开孔202中，并焊接至第三芯片23的焊垫232及布设在基板20的下表面201上的焊指203上，令第三芯片23能够借第三焊线26电性连接至基板20的下表面201。
一第一封装胶体27是以模压(Molding)等方式形成在基板20的上表面200上，用来包覆并保护第一芯片21、第二芯片22与第三芯片23免受外界水气及污染物侵害。
一第二封装胶体28是以印刷(Printing)等方式形成在基板20的下表面201上，并填充至基板20的开孔202及第一芯片21与第二芯片22之间的间隙G中，用来包覆第一焊线24、第二焊线25与第三焊线26。用于第二封装胶体28的树脂材料可以不同于形成第一封装胶体27的树脂材料。
多个焊球29是植接在基板20的下表面201上、不影响第二封装胶体28的区域，且焊球29的高度H大于第二封装胶体28突出基板20的下表面201的厚度T。焊球29是作为半导体封装件2的输出/输入(Input/Output，I/O)端，使第一芯片21、第二芯片22与第三芯片23能够借助焊球29与外界装置如印刷电路板(Printed Circuit Board，未图标)电性连接。
上述封装结构，由于第一芯片21、第二芯片22与第三芯片23都设置在基板20的上表面200上，且各芯片21、22、23的作用表面210、220、230上所布设的焊垫212、222、232等供电性连接用的导电结构，也都朝同一方向，即均朝向基板20的方向(如图1所示)列置，因此能够缩短作为电性连接媒介的焊线24、25、26的长度，增进芯片21、22、23的电性传递速度，改善整体半导体封装件1的电性及运行效率。再有，第一芯片21、第二芯片22与第三芯片23可以是动态随机存取内存芯片，各具有设置在芯片中心部位的焊垫212、222、232，因此上述封装结构还可达成同时堆栈三个具有中心焊垫的芯片在基板20的同一表面(上表面200)上的功能。
实施例2
图2显示本发明的实施例2的半导体封装件2′。如图所示，此半导体封装件2′与上述半导体封装件2的结构大致相同，其不同处仅在于半导体封装件2′的第一芯片21与第二芯片22的焊垫212、222设置在芯片周边部位、并外露在基板20的开孔202中，可以与第一焊线24及第二焊线25焊接。这样做，可增加本发明封装结构所适用的芯片种类，而不仅限于上述的具有中心焊垫的动态随机存取内存芯片。
实施例3
图3显示本发明的实施例3的半导体封装件2＂。如图所示，此半导体封装件2＂与上述半导体封装件2的结构大致相同，其不同之处仅在于半导体封装件2＂的第三芯片23的非作用表面231外露出包覆第一芯片21、第二芯片22与第三芯片23的第一封装胶体27，使芯片21、22、23运行时产生的热量，可借助该外露的非作用表面231更有效地散逸至外界，因而进一步增进半导体封装件2＂的散热效率。

Claims (11)

1.一种开窗型多芯片半导体封装件，其特征在于，该封装件包括：
一基板，具有一上表面及一相对的下表面，该基板开设有至少一贯穿该上、下表面的开孔；
至少一第一芯片及一第二芯片，各该芯片具有一作用表面及一相对的非作用表面，使该第一芯片与第二芯片的作用表面分别接置在该基板的上表面上，并使该第一芯片与第二芯片分别部分地自该开孔相对的两侧突伸在该开孔中，且该第一芯片与第二芯片间形成有一间隙，令布设在该第一芯片与第二芯片的作用表面上的焊垫借助基板的开孔外露；
至少一第三芯片，具有一作用表面及一相对的非作用表面，使该第三芯片的作用表面接置在该第一芯片与第二芯片的非作用表面上，并遮盖该间隙，令布设在该第三芯片的作用表面上的焊垫借助该间隙外露；
所述芯片皆设置于基板的同一表面上，所述芯片所布设的焊垫皆朝同一方向列置且设置于所述芯片中心部位；
多条第一焊线，用以电性连接该第三芯片至该第一芯片与第二芯片；
多条第二焊线，用以分别电性连接该第一芯片与第二芯片至该基板的下表面；
多条第三焊线，用以电性连接该第三芯片至该基板的下表面；
一第一封装胶体，形成在该基板的上表面上，用以包覆该第一芯片、第二芯片与第三芯片；
一第二封装胶体，形成在该基板的下表面上并填充至该开孔及间隙中，用以包覆该第一焊线、第二焊线与第三焊线；以及
多个焊球，植接在该基板的下表面上、不影响该第二封装胶体的区域。
2.如权利要求1所述的半导体封装件，其特征在于，该第一芯片的厚度与该第二芯片的厚度相同。
3.如权利要求1所述的半导体封装件，其特征在于，该第一焊线是焊接至该第三芯片的焊垫及该第一芯片与第二芯片的焊垫。
4.如权利要求1所述的半导体封装件，其特征在于，该第二焊线是焊接至该第一芯片与第二芯片的焊垫及布设在该基板的下表面上的焊指上。
5.如权利要求1所述的半导体封装件，其特征在于，该第三焊线是焊接至该第三芯片的焊垫及布设在该基板的下表面上的焊指上。
6.如权利要求1所述的半导体封装件，其特征在于，该第一焊线、第二焊线与第三焊线是金线。
7.如权利要求1所述的半导体封装件，其特征在于，该第一封装胶体是以模压方式形成的。
8.如权利要求1所述的半导体封装件，其特征在于，该第二封装胶体是以印刷方式形成的。
9.如权利要求1所述的半导体封装件，其特征在于，该第一封装胶体与第二封装胶体是分别以不同树脂材料制成的。
10.如权利要求1所述的半导体封装件，其特征在于，该第三芯片的非作用表面是外露出该第一封装胶体。
11.如权利要求1所述的半导体封装件，其特征在于，该焊球的高度是大于该第二封装胶体突出该基板下表面的厚度。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998050954A1 (en) * 1997-05-09 1998-11-12 Formfactor, Inc. Stacked semiconductor devices, particularly memory chips
US6091138A (en) * 1998-02-27 2000-07-18 Advanced Micro Devices, Inc. Multi-chip packaging using bump technology
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6281578B1 (en) * 2000-04-28 2001-08-28 Siliconware Precision Industries, Co., Ltd. Multi-chip module package structure
JP2002076252A (ja) * 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998050954A1 (en) * 1997-05-09 1998-11-12 Formfactor, Inc. Stacked semiconductor devices, particularly memory chips
US6091138A (en) * 1998-02-27 2000-07-18 Advanced Micro Devices, Inc. Multi-chip packaging using bump technology
US6218731B1 (en) * 1999-05-21 2001-04-17 Siliconware Precision Industries Co., Ltd. Tiny ball grid array package
US6281578B1 (en) * 2000-04-28 2001-08-28 Siliconware Precision Industries, Co., Ltd. Multi-chip module package structure
JP2002076252A (ja) * 2000-08-31 2002-03-15 Nec Kyushu Ltd 半導体装置

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