CN103531581B - 多芯片模块 - Google Patents

多芯片模块 Download PDF

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CN103531581B
CN103531581B CN201310319901.2A CN201310319901A CN103531581B CN 103531581 B CN103531581 B CN 103531581B CN 201310319901 A CN201310319901 A CN 201310319901A CN 103531581 B CN103531581 B CN 103531581B
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semiconductor chip
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CN103531581A (zh
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Y·L·方
C·S·纪
L·H·李
M·S·宾阿布-哈桑
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Cypress Semiconductor Corp
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Abstract

一种多芯片模块。本发明揭露了一种多芯片模块，其可缓和引线的破损。第一半导体芯片接置并引线接合在支撑衬底。间隔件连接至该第一半导体芯片。支撑材料配置在该间隔件上，而第二半导体芯片定位在该支撑材料上。该第二半导体芯片被压入该支撑材料内，并挤压该支撑材料进入邻近该间隔件且介于第一半导体芯片与第二半导体芯片之间的区域。或者，该支撑材料配置在该第一导体芯片上，而晶粒附着材料配置在该间隔件上。该第二半导体芯片被压入该晶粒附着材料与支撑材料内，并挤压支撑材料的部分至该间隔件边缘上。在该支撑衬底与该第一半导体芯片和第二半导体芯片之间形成引线接合件。

Description

多芯片模块
本申请是申请号为200680015142.9，申请日为2006年4月26日，发明名称为“多芯片模块及制造方法”的中国专利申请的分案申请。
技术领域
一般来说，本发明是有关于半导体组件，且尤关于包括多芯片模块的半导体组件。
背景技术
想要有更快、更便宜以及更有效率的半导体组件一直是促使半导体组件制造业者将半导体芯片中所制造的装置尺寸缩小以及将多个半导体芯片置入单一封装件（典型上称为多芯片模块）的动机。在多芯片模块中的半导体芯片可以放置成水平的方向（也就是在彼此的旁边）或是放置成垂直的方向（也就是垂直地堆栈在彼此的顶端）。在传统的垂直堆栈多芯片模块中，是藉由在利用黏着接合（adhesive bonding）方式使第一半导体芯片附着于电路板之后，利用引线接合（wirebonding）方式将位在半导体芯片上的接合垫（bonding pad）与位在电路板上对应的接合垫接合。将间隔件（spacer）形成在第一半导体芯片上或是附着于第一半导体芯片，以及将第二半导体芯片附着在间隔件。然后利用如引线接合程序将位在第二半导体芯片上的接合垫连接至位在电路板上对应的接合垫。间隔件必须小于第一半导体芯片以适合引线接合程序。此外，典型上间隔件是小于第二半导体芯片。这种型态结构的缺点是突出间隔件的第二半导体芯片的部分是易曲折的（pliable）或是有弹力的。因此，当利用引线接合方式将位在第二半导体芯片之突出部分上的接合垫与位在电路板上对应的接合垫接合时，第二半导体芯片之突出部分的易曲折性（pliability）使得形成在第二半导体芯片上的接合垫的接合件（bond）弱化（weaken）。此接合件弱化会造成悲惨的装置故障。
因此，将会有利的是有一种多芯片模块与一种用于制造该多芯片模块的方法，其不会降低形成在接合垫之接合件的完整性。这种方法与结构将更有利的是符合成本效益并且适于与种种多芯片模块程序整合。
发明内容
本发明藉由提供一种多芯片模块以满足前述的需求。依照一个实施例，本发明的多芯片模块包括：支撑衬底，具有芯片接收区与多个接合垫；第一半导体芯片，具有多个接合垫，该第一半导体芯片接置在该芯片接收区；间隔件，具有第一边缘与相对的第二边缘，该间隔件连接至该第一半导体芯片；支撑材料，与该间隔件接触；以及第二半导体芯片，连接至该间隔件，其中该支撑材料的一部分定位在该第一半导体芯片与该第二半导体芯片之间，且该支撑材料的一部分定位在该间隔件与该第二半导体芯片之间，以及，该支撑材料覆盖该多个接合垫。
该支撑材料与该第一半导体芯片和该第二半导体芯片接触。
附图说明
藉由阅读下列详细的描述与伴随的图式可更加了解本发明，其中图式中相似的组件符号代表相似的组件，且其中：
图1系依照本发明实施例的多芯片模块在开始的制造阶段的侧面截面图；
图2系图1的多芯片模块在后来的制造阶段且沿着图3的截面线2-2所截取的侧面截面图；
图3系图2的多芯片模块的俯视图；
图4系图2至3的多芯片模块在后来的制造阶段的侧面截面图；
图5系图4的多芯片模块在后来的制造阶段的侧面截面图；
图6系依照本发明另一个实施例的多芯片模块在开始的制造阶段且沿着图7的截面线6-6所截取的侧面截面图；
图7系图6的多芯片模块的俯视图；
图8系图6至7的多芯片模块在后来的制造阶段的侧面截面图；以及
图9系图8的多芯片模块在后来的制造阶段的侧面截面图。
具体实施方式
一般来说，本发明提供一种多芯片模块与一种用于制造多芯片模块的方法，其中该多芯片模块的半导体芯片是垂直堆栈的。在垂直堆栈该多芯片模块的半导体芯片时，间隔件系插入在该半导体芯片之间以提供引线接合件（wirebond）的空隙（clearance）。定位在该间隔件之上的该半导体芯片的一部分系突出于该间隔件的边缘。突出该间隔件之半导体芯片的部分是易曲折的。虽然一般来说，易曲折性增加了半导体芯片的易碎性（fragility），但增加的易碎性在具有小于约0.6毫米（mm）厚度的半导体芯片中较为显著。此易曲折性允许半导体芯片在引线接合程序期间振动，使连接至该半导体芯片上之接合垫的引线断裂。依照本发明，藉由形成在突出该间隔件的该第二半导体芯片之该部分之下的支撑材料而减缓振动。该支撑材料对该半导体芯片提供额外的坚硬度（rigidity），减少了该半导体芯片之该突出部分的振动与增进了引线接合件的可靠性。
图1系依照本发明实施例在中间的制造阶段的多芯片模块10的部分的侧面截面图。图1所显示的是各自具有顶部表面14与底部表面16之球形数组（Ball Grid Array，简称为BGA）支撑结构12。BGA支撑衬底12是由树脂所形成，例如环氧树脂（epoxy resin）、聚醯亚胺树脂（polyimide resin）、三嗪树脂（triazine resin）或是石碳酸树脂（phenolicresin）。较佳地，BGA支撑衬底12的树脂材料是三氮杂苯双马来醯胺（bismaleimidetriazine，简称BT）树脂。用于支撑衬底12的其它合适的材料包括环氧玻璃合成物（epoxy-glass composite）、FR-4、陶瓷（ceramic）以及其它相似物。须了解衬底12不限定为BGA衬底，而也可以是针栅数组（Pin Grid Array，简称为PGA）衬底、陶瓷衬底、印刷电路板（printed circuit board）或其它相似物。接合垫18A、18B与接合垫20A、20B形成在顶部表面14上。多个接合垫22形成在底部表面16上。接合垫18A、18B、20A、20B系分别经由延伸穿透BGA支撑衬底12的电性互连组件28、30、26、32而电性连接至位于底部表面16上之接合垫22B、22C、22A、22D。为了要清楚呈现的理由，在图1中只有显示四个互连组件延伸穿透BGA支撑衬底12。然而，须了解，所有或是几乎所有在支撑衬底（例如支撑衬底12）顶部表面上的接合垫，都连接至在该支撑衬底底部表面上的接合垫。须更进一步了解，接合垫18A、18B是形成在顶部表面14上的多个接合垫18的其中两个。同样地，接合垫20A、20B是形成在顶部表面14上的多个接合垫20的其中两个。（在图3中，会进一步说明与讨论多个接合垫18与20）。锡球34（solder balls）附着于接合垫22。
仍然参考图1，晶粒附着材料36系分配至半导体芯片接收区38，而且半导体芯片或晶粒40系放置在晶粒附着材料36上。半导体芯片40具有底部表面42与顶部表面44。多个接合垫46系设置围绕在顶部表面44的周围。半导体芯片或晶粒40的底部表面42是置于晶粒附着材料36上。虽然只有接合垫46A、46B显示于图中，但必须要了解接合垫46A、46B是多个接合垫46的部分，多个接合垫会进一步在图3显示与讨论。将衬底12、半导体芯片40与晶粒附着材料36的组合放置在硬化炉（curing oven）中而硬化晶粒附着材料36。经由实施例说明，藉由在约5分钟至约60分钟之间的时间将温度加热至介于约摄氏100度到约摄氏175度之间，硬化晶粒附着材料36。合适的晶粒附着材料包括填银环氧树脂（silver filled epoxy）、填硅环氧树脂混合物（silica filled epoxy blend）以及填充有有机材料的环氧薄膜（epoxyfilm）、或其它相似物。
在硬化晶粒附着材料36后，将晶粒附着材料48配置在顶部表面44的中央部份，而且将间隔件50置于晶粒附着材料48上。间隔件50分别具有顶部52与底部表面54以及边缘53、55。间隔件50可为电介质（dielectric）材料或是半导体材料（例如硅）、另一个半导体芯片、或是其它相似物。虽然间隔件50显示为具有正方形形状，但其形状并非本发明之限制。例如，间隔件50具有长方形形状、圆形形状、三角形形状等。藉由在约5分钟至约60分钟之间的时间将温度加热至介于约摄氏100度到约摄氏175度之间，硬化晶粒附着材料48。合适的晶粒附着材料包括填银环氧树脂、填硅环氧树脂混合物以及填充有有机材料的环氧薄膜、或其它相似物。
仍然参考图1，使用像是引线接合程序，将在半导体芯片40上的接合垫46电性连接至在BGA衬底12上对应的接合垫18。图1所显示的是接合垫46A藉由互连引线56A连接至接合垫18A，以及接合垫46B藉由互连引线56B连接至接合垫18B。虽然只有两个互连引线显示在图1中，但须了解多个互连组件56通常包含多于两个的互连引线。（在图3中，会进一步说明与讨论多个互连引线56）。
现在参考图2，说明更进一步沿着制造程序的多芯片模块10的侧面截面图。显示在图2中的是配置在半导体芯片40之表面44上的支撑材料60与配置在间隔件50之表面52上的晶粒附着材料62。较佳地，支撑材料60是环氧膏（epoxy paste），其中环氧膏是热的导体与电的绝缘体。由环氧膏组成之支撑材料60的例子包括填充有以铁氟龙（Teflon，Teflon是E.I.Du Pont De Demours and Company Corp.的商标）商标贩售之聚四氟乙烯（polytetrafluoroethylene）的环氧材料）、填充有无机材料的非导电性膏（像是二氧化硅（silica））、填充有以铁氟龙商标贩售的聚四氟乙烯的双马来醯亚胺（bismaleimide）材料、与其它相似物。合适的晶粒附着材料62包括填银环氧树脂、填硅环氧树脂混合物以及填充有有机材料的环氧薄膜、或其它相似物。
现在参考图3，显示多芯片模块10的俯视图，其中该俯视图说明与图2一样的制造阶段。换句话说，图2是沿着图3的截面线2-2所截取的侧面截面图。图3更进一步说明多个接合垫18、多个接合垫20、多个接合垫46、多个引线互连组件56和显示于图2之个别的接合垫18A、18B、20A、20B以及个别的互连组件56A、56B。此外，图3说明了支撑材料60与晶粒附着材料62。虽然支撑材料60显示为双Y（double-Y）或狗骨头形状，但其形状并非本发明之限制。例如，支撑材料60可以形成为具有圆形形状、三角形形状、四边形形状、五边形形状、与其它多边形形状。
现在参考图4，说明更进一步沿着制造程序之多芯片模块10的侧面截面图。半导体芯片64置于晶粒附着材料62上。更具体而言，半导体芯片64具有背侧（backside）66和前侧（front side）68，背侧66系置于晶粒附着材料62上，前侧68具有形成于其上的多个接合垫70。施加压力至半导体芯片64以使其定位于晶粒附着材料62中并在横向（lateral）的方向挤压（squeeze）支撑材料60以使其大致填满在表面44、66间的区域。在这个区域中，半导体芯片64的周边部分65系突出于间隔件50。藉由在约5分钟至约60分钟之间的时间将温度加热至介于约摄氏100度到约摄氏175度之间，硬化支撑材料60与晶粒附着材料62。因为支撑材料60系大致填满在表面44、66间的区域，所以半导体芯片64的周边部分65不会无拘束地突出于边缘53、55，但会由支撑材料60所支撑。因此，在后续的引线接合步骤期间，周边部分65不会显著的弹起。在表面44、66间放置支撑材料60的优点是它能增进形成在多芯片模块中之引线接合件的可制造性与可靠性。
使用像是引线接合程序，将多个接合垫70电性连接到多个接合垫20之对应的接合垫。更具体而言，接合垫70A藉由互连引线74A电性连接至接合垫20A，以及接合垫70B藉由互连引线74B电性连接至接合垫20B。互连引线74A、74B是多个互连引线74的其中两个互连引线。
现在参考图5，保护罩（protective covering）78系形成覆盖在半导体芯片64、互连引线56和74、与BGA衬底12上。图5说明的保护罩是一种覆顶式液状封装材料（glob top material）。然而，须了解保护罩的型态不限于覆顶式液状封装（glob top）材料。举例来说，保护罩78可以是盖状物（lid）或是帽状物（cap）。
图6系说明依照本发明另一个实施例的多芯片模块100。多芯片模块100在制造程序中开始的步骤和多芯片模块10的制造程序是一样的。因此，图6的描述延续自图1。支撑材料102配置在间隔件表面52的中央部分。较佳地，支撑材料102是环氧膏，其中环氧膏是热的导体与电的非导体（也就是电的绝缘体）。作为支撑材料102合适的环氧膏包括填充有以铁氟龙商标贩售的聚四氟乙烯的环氧材料、填充有无机材料的非导电性膏（像是二氧化硅）、填充有以铁氟龙商标贩售的聚四氟乙烯的双马来醯亚胺材料、与其它相似物。支撑材料102也可当作晶粒附着材料。
现在参考图7，显示多芯片模块100的俯视图，其中该俯视图说明与图6一样的制造阶段。换句话说，图6是沿着图7的截面线6-6所截取的侧面截面图。如同图3，图7更进一步说明多个接合垫18、多个接合垫20、多个接合垫46、多个引线互连组件56和显示于图2、6的个别的接合垫18A、18B、20A、20B以及个别的互连组件56A、56B。此外，图7说明了支撑材料102。虽然支撑材料102显示为双Y或狗骨头形状，但形状并非本发明之限制。例如，支撑材料102可以形成为具有圆形形状、三角形形状、四边形形状、五边形形状、与其它多边形形状。
现在参考图8，说明更进一步沿着制造程序之多芯片模块100的侧面截面图。半导体芯片104置于支撑材料102上。更具体而言，半导体芯片104具有背侧106和前侧108，背侧106系置于支撑材料102上，前侧108具有形成于其上的多个接合垫110。施加压力至半导体芯片104，以使其定位于支撑材料102中，并促使支撑材料102覆盖在间隔件50的边缘53、55上并进入表面44、106间的区域。一部分的支撑材料102留在间隔件50上，而一部分的支撑材料102大致填满表面44、106间的区域。因为支撑材料102大致填满表面44、106间的区域，所以半导体芯片104的周边部分112不会无拘束地突出，而是会被支撑的。因此，在后续的引线接合步骤期间，周边部分112不会显著的弹起。藉由在约5分钟至约60分钟之间的时间将温度加热至约摄氏100度到约摄氏175度之间，硬化支撑材料102。在表面44、106间放置支撑材料102的优点是它能增进形成在多层半导体封装结构中之引线接合件的可制造性与可靠性。
使用像是引线接合程序，将多个接合垫110电性连接到多个接合垫20之对应的接合垫。更具体而言，接合垫110A藉由互连引线114A电性连接至接合垫20A，以及接合垫110B藉由互连引线114B电性连接至接合垫20B。为了要清楚的描述，在图8中只有显示多个互连引线中的两个互连引线（也就是互连引线114A、114B）。
现在参考图9，保护罩116系形成覆盖在半导体芯片104、互连引线56A、56B、114A、与114B、以及BGA支撑衬底12上。图9说明的保护罩116是一个盖状物，藉由盖状物附着材料118固着于BGA支撑衬底12。须了解，保护罩的型态不限于盖状物。举例来说，保护罩114可以是覆顶式液状封装（glob top）材料或是其它适合的保护材料。
至此，应了解本发明提供了一种具有垂直堆栈半导体芯片的多芯片模块与一种用于制造多芯片模块的方法。根据本发明之多芯片模块的优点是它提供了一种在引线接合程序的期间用来减少半导体芯片区域的振动或反弹的方法。这增进了引线接合件的可靠性与减少了悲惨的装置故障。本发明的另一个优点是它增加了能连结到间隔件之半导体芯片尺寸的种类。因为支撑材料提供了额外的支撑予半导体芯片，更大的芯片可以固定在间隔件上。此外，这个方法能以有成本时间效益的方式，容易地整合于多芯片模块的程序流程内。
虽然本文中揭露一些较佳的实施例与方法，但是很明显地，经由上述揭露的技术，本领域熟知此项技术之人士可以在不脱离本发明的精神与范围下制造出像这样实施例与方法的变化型与修改物。举例来说，支撑材料可以配置在间隔件与第一半导体芯片上。或者，可以使用胶黏剂膜连接半导体芯片64至间隔件50，而不是使用晶粒附着材料（例如晶粒附着材料48）。使用胶黏剂材料的一个优点是胶黏剂材料不需要硬化。本发明系意指仅限制于附加的权利要求书所请求的范围以及准据法之规则与法条。

Claims (2)

1.一种多芯片模块(10)，包括：
支撑衬底(12)，具有芯片接收区(38)与多个接合垫(18、20)；
第一半导体芯片(40)，具有多个第一接合垫(46)，该第一半导体芯片(40)接置在该芯片接收区(38)；
间隔件(50)，具有第一边缘(53)与相对的第二边缘(55)，该间隔件(50)连接至该第一半导体芯片(40)；
支撑材料(60)，与该间隔件(50)接触；以及
第二半导体芯片(64)，具有位于所述第二半导体芯片(64)的周边区域(65)上的多个第二芯片接合垫(70)，所述第二半导体芯片(64)的周边区域(65)突出于该间隔件(50)，该第二半导体芯片(64)被使用晶粒附着材料(62)连接至该间隔件(50)，
其中该支撑材料(60)的一部分定位在该第一半导体芯片(40)与该第二半导体芯片(64)之间并且与该第一半导体芯片(40)和该第二半导体芯片(64)接触，且
该支撑材料(60)定位在所述周边区域(65)的下方，从而在接合期间对所述多个第二芯片接合垫(70)提供支撑。
2.如权利要求1所述的多芯片模块(10)，其中该支撑材料(60)大致填满在该第一半导体芯片(40)和该第二半导体芯片(64)之间的区域。
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JP2011205116A (ja) 2011-10-13
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US8586413B2 (en) 2013-11-19
US20060249826A1 (en) 2006-11-09
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CN103531581A (zh) 2014-01-22
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TW200717770A (en) 2007-05-01
CN101171683A (zh) 2008-04-30
WO2006118994A2 (en) 2006-11-09
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CN101171683B (zh) 2014-02-12

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