US20140061895A1 - Multi-Chip Module and Method of Manufacture - Google Patents
Multi-Chip Module and Method of Manufacture Download PDFInfo
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- US20140061895A1 US20140061895A1 US14/076,706 US201314076706A US2014061895A1 US 20140061895 A1 US20140061895 A1 US 20140061895A1 US 201314076706 A US201314076706 A US 201314076706A US 2014061895 A1 US2014061895 A1 US 2014061895A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
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Definitions
- the present invention relates, in general, to semiconductor components and, more particularly, to semiconductor components comprising multi-chip modules.
- a multi-chip module The desire for faster, cheaper, and more efficient semiconductor components has motivated semiconductor component manufacturers to shrink the sizes of the devices fabricated in a semiconductor chip and place multiple semiconductor chips in a single package typically referred to as a multi-chip module.
- the semiconductor chips in a multi-chip module can be placed either in a horizontal orientation, i.e., beside each other, or in a vertical orientation, i.e., vertically stacked on top of each other.
- a first semiconductor chip is attached to a circuit board by adhesive bonding followed by wirebonding bonding pads located on the semiconductor chip to corresponding bonding pads located on the circuit board.
- a spacer is formed on or attached to the first semiconductor chip and a second semiconductor chip is attached to the spacer.
- bonding pads located on the second semiconductor chip are coupled to corresponding bonding pads located on the circuit board using, for example, a wirebonding process.
- the spacer must be smaller than the first semiconductor chip to accommodate the wirebonding process. What's more, the spacer is typically smaller than the second semiconductor chip.
- a drawback with this type of structure is that the portions of the second semiconductor chip that overhang the spacer are pliable or springy.
- the pliability of the overhanging portions of the second semiconductor chip weakens the bonds formed to bonding pads on the second semiconductor chip. This bond weakening causes catastrophic device failure.
- the present invention satisfies the foregoing need by providing a multi-chip module and a method for manufacturing the multi-chip module.
- the present invention includes providing a support substrate having first and second major surfaces, wherein the support substrate has a chip receiving area and a plurality of bonding pads.
- a first semiconductor chip is coupled to the chip receiving area, wherein the first semiconductor chip has a plurality of bonding pads.
- a first bonding pad of the first semiconductor chip is coupled to a first bonding pad of the support substrate.
- a spacer is coupled to a portion of the first semiconductor chip.
- a support material is disposed on at least one of the spacer or the first semiconductor chip.
- a second semiconductor chip is positioned on the support material, wherein the second semiconductor chip has a first major surface and a plurality of bonding pads.
- a first bonding pad of the second semiconductor chip is coupled to a second bonding pad of the support substrate.
- the present invention comprises a method for manufacturing a multi-chip module that includes providing a support substrate having, a first semiconductor chip mounted to a chip or die receiving area on the support substrate.
- the support substrate has a plurality of bonding pads and the first semiconductor chip has a plurality of bonding pads.
- a spacer is coupled to the first semiconductor chip and a support material is disposed on one of the spacer or the first semiconductor chip.
- a semiconductor chip is coupled to the spacer such that the support material, becomes positioned between the first semiconductor chip and the second semiconductor chip thereby providing support for the second semiconductor chip.
- the present invention comprises a multi-chip module having a support substrate that has a chip receiving area and a plurality of bonding pads.
- a first semiconductor chip having a plurality of bonding pads is mounted to the chip receiving area.
- a spacer having first and second opposing edges is coupled to the first semiconductor chip.
- a support material is in contact with the spacer.
- a second semiconductor chip is coupled to the spacer, wherein a portion of the support material is positioned between the first semiconductor chip and the second semiconductor chip.
- FIG. 1 is a cross-sectional side view of a multi-chip module at a beginning stage of manufacture in accordance with an embodiment of the present invention
- FIG. 2 is a cross-sectional side view of the multi-chip module of FIG. 1 at a later stage of manufacture and taken along section line 2 - 2 of FIG. 3 ;
- FIG. 3 is a top view of the multi-chip module of FIG. 2 ;
- FIG. 4 is a cross-sectional side view of the multi-chip module of FIGS. 2 and 3 at a later stage of manufacture
- FIG. 5 is a cross-sectional side view of the multi-chip module of FIG. 4 at a later stage of manufacture
- FIG. 6 is a cross-sectional side view of a multi-chip module at a beginning stage of manufacture in accordance with another embodiment of the present invention and taken along section line 6 - 6 of FIG. 7 ;
- FIG. 7 is a top view of the multi-chip module of FIG. 6 ;
- FIG. 8 is a cross-sectional side view of the multi-chip module of FIGS. 6 and 7 at a later stage of manufacture.
- FIG. 9 is a cross-sectional side view of the multi-chip module of FIG. 8 at a later stage of manufacture.
- the present invention provides a multi-chip module and a method for manufacturing the multi-chip module, wherein the semiconductor chips of the multi-chip module are vertically stacked.
- a spacer is inserted between the semiconductor chips to allow clearance for the wirebonds.
- a portion of the semiconductor chip positioned above the spacer overhangs the edges of the spacer.
- the portions of a semiconductor chip overhanging the spacer are pliable.
- the vibration is mitigated by forming a support material under the portion of the second semiconductor chip that overhangs the spacer.
- the support material provides additional rigidity to the semiconductor chip, which decreases the vibrations of the overhanging portions of the semiconductor chip and improves the reliability of the wirebond.
- FIG. 1 is cross-sectional side view of a portion of a multi-chip module 10 at an intermediate stage of manufacture in accordance with an embodiment of the present invention.
- BGA support structure 12 is formed from a resin such as an epoxy resin, a polyimide resin, a triazine resin, or a phenolic resin.
- the resin material of BGA support substrate 12 is bisrnaleimidetriazine (BT) resin.
- BT bisrnaleimidetriazine
- Other suitable materials for support substrate 12 include epoxy-glass composites, FR-4, ceramics, and the like.
- substrate 12 is not limited to being a BGA substrate but may also be a Pin Grid Array (PGA) substrate, a ceramic substrate, a printed circuit board, or the like.
- Bonding pads 18 A and 18 B and bonding pads 20 A and 20 B are formed on top surface 14 .
- a plurality of bonding pads 22 are formed on bottom surface 16 .
- Bonding pads 18 A, 18 B, 20 A, and 20 B are electrically connected to bonding pads 22 B, 22 C, 22 A, and 22 D, respectively, on bottom surface 16 through electrical interconnects 28 , 30 , 26 , and 32 that extend through BGA support substrate 12 .
- electrical interconnects 28 , 30 , 26 , and 32 that extend through BGA support substrate 12 .
- only four interconnects are shown as extending through BGA support substrate 12 in FIG. 1 .
- bonding pads 18 A and 18 B are two of a plurality of bonding pads 18 that are formed on top surface 14 .
- bonding pads 20 A and 20 B are two of a plurality of bonding pads 20 that are formed on top surface 14 .
- the pluralities of bonding pads 18 and 20 are further illustrated and discussed with reference to in FIG. 3 ).
- Solder balls 34 are attached to bonding pads 22 .
- a die attach material 36 is dispensed on a semiconductor chip receiving area 38 and a semiconductor chip or die 40 is placed on die attach material 36 .
- Semiconductor chip 40 has a bottom surface 42 and a top surface 44 .
- a plurality of bonding pads 46 is disposed around the periphery of top surface 44 .
- Bottom surface 42 of a semiconductor chip or die 40 is placed on die attach material 36 .
- bonding pads 46 A and 46 B are shown, it should be understood that bonding pads 46 A and 46 B are part of plurality of bonding pads 46 , which plurality is further shown and described with reference to FIG. 3 .
- die attach material 36 is cured by heating to a temperature ranging from about 100 degrees Celsius (° C.) to about 175° C. for a time ranging from about 5 minutes to about 60 minutes.
- Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.
- a die attach material 48 is disposed on a central portion of top surface 44 and a spacer 50 is placed on die attach material 48 .
- Spacer 50 has top and bottom surfaces 52 and 54 , respectively, and edges 53 and 55 .
- Spacer 50 may be a dielectric material, a semiconductor material such as, for example, silicon, another semiconductor chip, or the like.
- spacer 50 is shown as having a square shape, its shape is not a limitation of the present invention. For example, spacer 50 have a rectangular shape, a round shape, a triangular shape, etc.
- Die attach material 48 is cured by heating it to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.
- bonding pads 46 on semiconductor chip 40 are electrically connected to corresponding bonding pads 18 on BGA substrate 12 using, for example, a wirebonding process. What is shown in FIG. 1 is bonding pad 46 A coupled to bonding pad 18 A by an interconnect wire 56 A and bonding pad 46 B coupled to bonding pad 18 B by an interconnect wire 56 B. Although only two interconnect wires are shown in FIG. 1 , it should be understood that typically plurality of interconnects 56 comprises more than two interconnect wires. (The plurality of interconnect wires 56 is further illustrated and discussed with reference to in FIG. 3 ).
- support material 60 is an epoxy paste that is a thermal conductor and an electrical insulator.
- examples of the epoxy paste comprising support material 60 include an epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon (Teflon is a trademark of E.I.
- a nonconductive paste e.g., silica
- an inorganic material bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like.
- Suitable materials for die attach material 62 include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like.
- FIG. 3 a top view of multi-chip module 10 is shown, wherein the top view illustrates the same stage of manufacture as that shown in FIG. 2 .
- FIG. 2 is a cross-sectional side view taken along section line 2 - 2 of FIG. 3 .
- FIG. 3 further illustrates the plurality of bonding pads 18 , the plurality of bonding pads 20 , the plurality of bonding pads 46 , the plurality of wire interconnects 56 , as well as the individual bonding pads 18 A, 18 B, 20 A, and 20 B and the individual interconnects 56 A and 56 B shown in FIG. 2 .
- FIG. 3 illustrates support material 60 and die attach material 62 .
- support material 60 is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention.
- support material 60 can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, as well as other polygonal shapes.
- FIG. 4 a cross-sectional side view of multi-chip module 10 further along in manufacture is illustrated.
- a semiconductor chip 64 is placed on die attach material 62 . More particularly, semiconductor chip 64 has a backside 66 that is placed on die attach material 62 and a front side 68 that has a plurality of bonding pads 70 formed thereon. Pressure is applied to semiconductor chip 64 to position it in die attach material 62 and to squeeze support material 60 in a lateral direction so that it substantially fills the region between surfaces 44 and 66 . In this region, peripheral portions 65 of semiconductor chip 64 overhang spacer 50 . Support material 60 and die attach material 62 are cured by being heated to a temperature ranging from about 100° C. to about 175° C.
- support material 60 substantially fills the region between surfaces 44 and 66 , the peripheral portions 65 of semiconductor chip 64 do not freely overhang edges 53 and 54 , but are supported by support material 60 . Thus, peripheral portions 65 do not bounce significantly during a subsequent wirebonding step.
- An advantage of placing support material 60 between surfaces 44 and 66 is that it improves the manufacturability and reliability of wirebonds formed in multi-chip modules,
- a plurality of bonding pads 70 are electrically connected to corresponding bonding pads of plurality of bonding pads 20 using, for example, a wirebonding process. More particularly, bonding pad 70 A is electrically connected to bonding pad 20 A by an interconnect wire 74 A and bonding pad 70 B is electrically connected to bonding pad 20 B by an interconnect wire 74 B. Interconnect wires 74 A and 74 B are two interconnect wires of plurality of interconnect wires 74 .
- a protective covering 78 is formed over semiconductor chip 64 , interconnect wires 56 and 74 , and 130 A substrate 12 .
- the protective covering illustrated in FIG. 5 is a glob top material.
- the type of protective material is not limited to being a glob top material.
- protective covering 78 may be a lid or cap.
- FIG. 6 illustrates a multi-chip module 100 in accordance with another embodiment of the present invention.
- the beginning steps in the manufacture of multi chip module 100 are the same as those for the manufacture of multi-chip module 10 .
- a support material 102 is disposed on a central portion of spacer surface 52 .
- support material 102 is an epoxy paste that is thermally conductive and electrical non-conductive, i.e. it is an electrical insulator.
- Suitable epoxy pastes for support material include epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon, nonconductive paste (e.g., silica) filled with an inorganic material, bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like.
- Support material 102 also serves as a die attach material.
- FIG. 7 a top view of multi-chip module 100 is shown wherein the top view illustrates the same stage of manufacture as that shown in FIG. 6 .
- FIG. 6 is a cross-sectional side view taken along section line 6 - 6 of FIG. 7 .
- FIG. 7 further illustrates the plurality of bonding pads 18 , the plurality of bonding pads 20 , the plurality of bonding pads 46 , the plurality of wire interconnects 56 , as well as the individual bonding pads 18 A, 18 B, 20 A, and 20 B and the individual interconnects 56 A and 56 B shown in FIGS. 2 and 6 .
- FIG. 7 illustrates support material 102 .
- support material 102 is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention.
- support material 102 can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, and other polygonal shapes.
- FIG. 8 a cross-sectional side view of multi-chip module 100 further along in manufacture is illustrated.
- a semiconductor chip 104 is placed on support material 102 . More particularly, semiconductor chip 104 has a backside 106 that is placed on support material 102 and a front side 108 that has a plurality of bonding pads 110 formed thereon. Pressure is applied to semiconductor chip 104 to position it in support material 102 and to urge support material 102 over edges 53 and 55 of spacer 50 and into the region between surfaces 44 and 106 . A portion of support material 102 remains on spacer 50 and a portion of support material 102 substantially fills the region between surfaces 44 and 106 .
- support material 102 substantially fills the region between surfaces 44 and 106 , the peripheral portions 112 of semiconductor chip 104 do not overhang freely, but are supported. Thus, peripheral portions 112 do not significantly during a subsequent wirebonding step.
- Support material 102 is cured by being to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes.
- a plurality of bonding pads 110 are electrically connected to corresponding bonding pads of plurality of bonding pads 20 using, for example, a wirebonding process. More particularly, bonding pad 110 A is electrically connected to bonding pad 20 A by an interconnect wire 114 A and bonding pad 110 B is electrically connected to bonding pad 20 B by an interconnect wire 114 B. For clarity of description, only two interconnect wires, i.e., interconnect wires 114 A and 114 B, of a plurality of interconnect wires are shown in FIG. 8 .
- a protective covering 116 is formed over semiconductor chip 104 , interconnect wires 56 A, 56 B, 114 A, and 114 B, and BGA support substrate 12 .
- Protective covering 116 illustrated in FIG. 9 is a lid secured to BGA support substrate 12 by a lid attach material 118 . It should be understood that the type of protective covering is not limited to being a lid.
- protective covering 114 may be a glob top material or other suitable protective material.
- multi-chip modules having vertically stacked semiconductor chips and a method for manufacturing the multi-chip module been provided.
- An advantage of multi-chip modules in accordance with the present invention is that it provides a means for decreasing vibration or bounce of regions of a semiconductor chip during a wirebonding process. This improves the reliability of the wirebonds and decreases catastrophic device failure.
- Another advantage of the present invention is that it increases the variety in the sizes of the semiconductor chips that can be bonded to a spacer. Because the support material provides additional support for the semiconductor chip, larger chips can be mounted to the spacer.
- the method is readily integrable into multi-chip module processing flows in a cost and time efficient manner.
- the support material may be disposed on the spacer and the first semiconductor chip.
- an adhesive film can be used to couple semiconductor chip 64 to spacer 50 rather than using a die attach material such as the attach material 48 .
- An advantage of using an adhesive material is that an adhesive material does not have to be cured. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
Description
- This application is a divisional of U.S. Non-Provisional Application No. 11/125,396, filed May 4, 2005, to issue as U.S. Pat. No. 8,586,413, which is incorporated herein by reference in its entirety.
- The present invention relates, in general, to semiconductor components and, more particularly, to semiconductor components comprising multi-chip modules.
- The desire for faster, cheaper, and more efficient semiconductor components has motivated semiconductor component manufacturers to shrink the sizes of the devices fabricated in a semiconductor chip and place multiple semiconductor chips in a single package typically referred to as a multi-chip module. The semiconductor chips in a multi-chip module can be placed either in a horizontal orientation, i.e., beside each other, or in a vertical orientation, i.e., vertically stacked on top of each other. In a conventional vertically stacked multi-chip module, a first semiconductor chip is attached to a circuit board by adhesive bonding followed by wirebonding bonding pads located on the semiconductor chip to corresponding bonding pads located on the circuit board. A spacer is formed on or attached to the first semiconductor chip and a second semiconductor chip is attached to the spacer. Then bonding pads located on the second semiconductor chip are coupled to corresponding bonding pads located on the circuit board using, for example, a wirebonding process. The spacer must be smaller than the first semiconductor chip to accommodate the wirebonding process. What's more, the spacer is typically smaller than the second semiconductor chip. A drawback with this type of structure is that the portions of the second semiconductor chip that overhang the spacer are pliable or springy. Thus, when the bonding pads located on the overhanging portion of the second semiconductor chip are wirebonded to the corresponding bonding pads located on the circuit board, the pliability of the overhanging portions of the second semiconductor chip weakens the bonds formed to bonding pads on the second semiconductor chip. This bond weakening causes catastrophic device failure.
- Accordingly, it would be advantageous to have a multi-chip module and a method for manufacturing the multi-chip module that does not degrade the integrity of the bonds formed to the bonding pads. It would be of further advantage for the method and structure to be cost efficient and suitable for integration with a variety of multi-chip module processes.
- The present invention satisfies the foregoing need by providing a multi-chip module and a method for manufacturing the multi-chip module. In accordance with one embodiment, the present invention includes providing a support substrate having first and second major surfaces, wherein the support substrate has a chip receiving area and a plurality of bonding pads. A first semiconductor chip is coupled to the chip receiving area, wherein the first semiconductor chip has a plurality of bonding pads. A first bonding pad of the first semiconductor chip is coupled to a first bonding pad of the support substrate. A spacer is coupled to a portion of the first semiconductor chip. A support material is disposed on at least one of the spacer or the first semiconductor chip. A second semiconductor chip is positioned on the support material, wherein the second semiconductor chip has a first major surface and a plurality of bonding pads. A first bonding pad of the second semiconductor chip is coupled to a second bonding pad of the support substrate.
- In accordance with another embodiment, the present invention comprises a method for manufacturing a multi-chip module that includes providing a support substrate having, a first semiconductor chip mounted to a chip or die receiving area on the support substrate. The support substrate has a plurality of bonding pads and the first semiconductor chip has a plurality of bonding pads. A spacer is coupled to the first semiconductor chip and a support material is disposed on one of the spacer or the first semiconductor chip. A semiconductor chip is coupled to the spacer such that the support material, becomes positioned between the first semiconductor chip and the second semiconductor chip thereby providing support for the second semiconductor chip.
- In accordance with yet another embodiment, the present invention comprises a multi-chip module having a support substrate that has a chip receiving area and a plurality of bonding pads. A first semiconductor chip having a plurality of bonding pads is mounted to the chip receiving area. A spacer having first and second opposing edges is coupled to the first semiconductor chip. A support material is in contact with the spacer. A second semiconductor chip is coupled to the spacer, wherein a portion of the support material is positioned between the first semiconductor chip and the second semiconductor chip.
- The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference numbers designate like elements and in which:
-
FIG. 1 is a cross-sectional side view of a multi-chip module at a beginning stage of manufacture in accordance with an embodiment of the present invention; -
FIG. 2 is a cross-sectional side view of the multi-chip module ofFIG. 1 at a later stage of manufacture and taken along section line 2-2 ofFIG. 3 ; -
FIG. 3 is a top view of the multi-chip module ofFIG. 2 ; -
FIG. 4 is a cross-sectional side view of the multi-chip module ofFIGS. 2 and 3 at a later stage of manufacture; -
FIG. 5 is a cross-sectional side view of the multi-chip module ofFIG. 4 at a later stage of manufacture; -
FIG. 6 is a cross-sectional side view of a multi-chip module at a beginning stage of manufacture in accordance with another embodiment of the present invention and taken along section line 6-6 ofFIG. 7 ; -
FIG. 7 is a top view of the multi-chip module ofFIG. 6 ; -
FIG. 8 is a cross-sectional side view of the multi-chip module ofFIGS. 6 and 7 at a later stage of manufacture; and -
FIG. 9 is a cross-sectional side view of the multi-chip module ofFIG. 8 at a later stage of manufacture. - Generally, the present invention provides a multi-chip module and a method for manufacturing the multi-chip module, wherein the semiconductor chips of the multi-chip module are vertically stacked. In vertically stacking the semiconductor chips of a multi-chip module, a spacer is inserted between the semiconductor chips to allow clearance for the wirebonds. A portion of the semiconductor chip positioned above the spacer overhangs the edges of the spacer. The portions of a semiconductor chip overhanging the spacer are pliable. Although the pliability increases the fragility of semiconductor chips in general, the increased fragility is more pronounced in semiconductor chips having thicknesses of less than about 0.6 millimeters (mm). This pliability allows the semiconductor chip to vibrate during the wirebonding process, which breaks the wires being bonded to bonding pads on the semiconductor chip. In accordance with the present invention, the vibration is mitigated by forming a support material under the portion of the second semiconductor chip that overhangs the spacer. The support material provides additional rigidity to the semiconductor chip, which decreases the vibrations of the overhanging portions of the semiconductor chip and improves the reliability of the wirebond.
-
FIG. 1 is cross-sectional side view of a portion of amulti-chip module 10 at an intermediate stage of manufacture in accordance with an embodiment of the present invention. What is shown inFIG. 1 is a Ball Grid Array (BGA)support structure 12 having top andbottom surfaces BGA support substrate 12 is formed from a resin such as an epoxy resin, a polyimide resin, a triazine resin, or a phenolic resin. Preferably, the resin material ofBGA support substrate 12 is bisrnaleimidetriazine (BT) resin. Other suitable materials forsupport substrate 12 include epoxy-glass composites, FR-4, ceramics, and the like. It should be understood thatsubstrate 12 is not limited to being a BGA substrate but may also be a Pin Grid Array (PGA) substrate, a ceramic substrate, a printed circuit board, or the like.Bonding pads pads top surface 14. A plurality ofbonding pads 22 are formed onbottom surface 16.Bonding pads pads bottom surface 16 throughelectrical interconnects BGA support substrate 12. For the sake of clarity, only four interconnects are shown as extending throughBGA support substrate 12 inFIG. 1 . However, it should be understood that all or nearly all of the bonding pads on the top surface of a support substrate such as support substrate are coupled to bonding pads on the bottom surface of the support substrate. It should be further understood thatbonding pads bonding pads 18 that are formed ontop surface 14. Similarly,bonding pads bonding pads 20 that are formed ontop surface 14. (The pluralities ofbonding pads FIG. 3 ).Solder balls 34 are attached tobonding pads 22. - Still referring to
FIG. 1 , a die attachmaterial 36 is dispensed on a semiconductorchip receiving area 38 and a semiconductor chip or die 40 is placed on die attachmaterial 36.Semiconductor chip 40 has abottom surface 42 and atop surface 44. A plurality ofbonding pads 46 is disposed around the periphery oftop surface 44.Bottom surface 42 of a semiconductor chip or die 40 is placed on die attachmaterial 36. Although only bondingpads bonding pads bonding pads 46, which plurality is further shown and described with reference toFIG. 3 . The combination ofsubstrate 12,semiconductor chip 40, and die attachmaterial 36 is placed in a curing oven and die attachmaterial 36 is cured. By way of example, die attachmaterial 36 is cured by heating to a temperature ranging from about 100 degrees Celsius (° C.) to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like. - After curing die attach
material 36, a die attachmaterial 48 is disposed on a central portion oftop surface 44 and aspacer 50 is placed on die attachmaterial 48.Spacer 50 has top andbottom surfaces Spacer 50 may be a dielectric material, a semiconductor material such as, for example, silicon, another semiconductor chip, or the like. Althoughspacer 50 is shown as having a square shape, its shape is not a limitation of the present invention. For example,spacer 50 have a rectangular shape, a round shape, a triangular shape, etc. Die attachmaterial 48 is cured by heating it to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Suitable die attach materials include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like. - Still referring to
FIG. 1 ,bonding pads 46 onsemiconductor chip 40 are electrically connected tocorresponding bonding pads 18 onBGA substrate 12 using, for example, a wirebonding process. What is shown inFIG. 1 is bondingpad 46A coupled tobonding pad 18A by aninterconnect wire 56A andbonding pad 46B coupled tobonding pad 18B by aninterconnect wire 56B. Although only two interconnect wires are shown inFIG. 1 , it should be understood that typically plurality ofinterconnects 56 comprises more than two interconnect wires. (The plurality ofinterconnect wires 56 is further illustrated and discussed with reference to inFIG. 3 ). - Referring now to
FIG. 2 , a cross-sectional side view ofmulti-chip module 10 further along in manufacture is illustrated. What is shown inFIG. 2 is asupport material 60 disposed onsurface 44 ofsemiconductor chip 40 and a die attachmaterial 62 disposed onsurface 52 ofspacer 50. Preferably,support material 60 is an epoxy paste that is a thermal conductor and an electrical insulator. Examples of the epoxy paste comprisingsupport material 60 include an epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon (Teflon is a trademark of E.I. DuPont De Demours and Company Corp.), a nonconductive paste (e.g., silica) filled with an inorganic material, bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like. Suitable materials for die attachmaterial 62 include silver filled epoxy, silica filled epoxy blend, an epoxy film filled with an organic material, and the like. - Referring now to
FIG. 3 , a top view ofmulti-chip module 10 is shown, wherein the top view illustrates the same stage of manufacture as that shown inFIG. 2 . In other words,FIG. 2 is a cross-sectional side view taken along section line 2-2 ofFIG. 3 .FIG. 3 further illustrates the plurality ofbonding pads 18, the plurality ofbonding pads 20, the plurality ofbonding pads 46, the plurality of wire interconnects 56, as well as theindividual bonding pads individual interconnects FIG. 2 . In addition,FIG. 3 illustratessupport material 60 and die attachmaterial 62. Althoughsupport material 60 is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention. For example,support material 60 can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, as well as other polygonal shapes. - Retelling now to
FIG. 4 , a cross-sectional side view ofmulti-chip module 10 further along in manufacture is illustrated. Asemiconductor chip 64 is placed on die attachmaterial 62. More particularly,semiconductor chip 64 has abackside 66 that is placed on die attachmaterial 62 and afront side 68 that has a plurality ofbonding pads 70 formed thereon. Pressure is applied tosemiconductor chip 64 to position it in die attachmaterial 62 and to squeezesupport material 60 in a lateral direction so that it substantially fills the region betweensurfaces peripheral portions 65 ofsemiconductor chip 64overhang spacer 50.Support material 60 and die attachmaterial 62 are cured by being heated to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. Becausesupport material 60 substantially fills the region betweensurfaces peripheral portions 65 ofsemiconductor chip 64 do not freely overhang edges 53 and 54, but are supported bysupport material 60. Thus,peripheral portions 65 do not bounce significantly during a subsequent wirebonding step. An advantage of placingsupport material 60 betweensurfaces - A plurality of
bonding pads 70 are electrically connected to corresponding bonding pads of plurality ofbonding pads 20 using, for example, a wirebonding process. More particularly,bonding pad 70A is electrically connected tobonding pad 20A by aninterconnect wire 74A and bonding pad 70B is electrically connected tobonding pad 20B by an interconnect wire 74B.Interconnect wires 74A and 74B are two interconnect wires of plurality ofinterconnect wires 74. - Referring now to FIG, 5, a
protective covering 78 is formed oversemiconductor chip 64,interconnect wires 130 A substrate 12. The protective covering illustrated inFIG. 5 is a glob top material. However, it should be understood that the type of protective material is not limited to being a glob top material. For example,protective covering 78 may be a lid or cap. -
FIG. 6 illustrates amulti-chip module 100 in accordance with another embodiment of the present invention. The beginning steps in the manufacture ofmulti chip module 100 are the same as those for the manufacture ofmulti-chip module 10. - Thus, the description of
FIG. 6 continues from that ofFIG. 1 . Asupport material 102 is disposed on a central portion ofspacer surface 52. Preferably,support material 102 is an epoxy paste that is thermally conductive and electrical non-conductive, i.e. it is an electrical insulator. Suitable epoxy pastes for support material include epoxy material filled with polytetrafluoroethylene sold under the trademark Teflon, nonconductive paste (e.g., silica) filled with an inorganic material, bismaleimide material filled with polytetrafluoroethylene sold under the trademark Teflon, and the like.Support material 102 also serves as a die attach material. - Referring now to
FIG. 7 , a top view ofmulti-chip module 100 is shown wherein the top view illustrates the same stage of manufacture as that shown inFIG. 6 . In other words,FIG. 6 is a cross-sectional side view taken along section line 6-6 ofFIG. 7 . LikeFIG. 3 ,FIG. 7 further illustrates the plurality ofbonding pads 18, the plurality ofbonding pads 20, the plurality ofbonding pads 46, the plurality of wire interconnects 56, as well as theindividual bonding pads individual interconnects FIGS. 2 and 6 . In addition,FIG. 7 illustratessupport material 102. Althoughsupport material 102 is shown as having a double-Y or dogbone shape, this is not a limitation of the present invention. For example,support material 102 can be formed to have circular shapes, triangular shapes, quadrilateral shapes, pentagonal shapes, and other polygonal shapes. - Referring now to
FIG. 8 , a cross-sectional side view ofmulti-chip module 100 further along in manufacture is illustrated. Asemiconductor chip 104 is placed onsupport material 102. More particularly,semiconductor chip 104 has abackside 106 that is placed onsupport material 102 and afront side 108 that has a plurality ofbonding pads 110 formed thereon. Pressure is applied tosemiconductor chip 104 to position it insupport material 102 and to urgesupport material 102 overedges spacer 50 and into the region betweensurfaces support material 102 remains onspacer 50 and a portion ofsupport material 102 substantially fills the region betweensurfaces support material 102 substantially fills the region betweensurfaces peripheral portions 112 ofsemiconductor chip 104 do not overhang freely, but are supported. Thus,peripheral portions 112 do not significantly during a subsequent wirebonding step.Support material 102 is cured by being to a temperature ranging from about 100° C. to about 175° C. for a time ranging from about 5 minutes to about 60 minutes. An advantage of placingsupport material 102 betweensurfaces - A plurality of
bonding pads 110 are electrically connected to corresponding bonding pads of plurality ofbonding pads 20 using, for example, a wirebonding process. More particularly,bonding pad 110A is electrically connected tobonding pad 20A by aninterconnect wire 114A andbonding pad 110B is electrically connected tobonding pad 20B by aninterconnect wire 114B. For clarity of description, only two interconnect wires, i.e.,interconnect wires FIG. 8 . - Referring now to
FIG. 9 , aprotective covering 116 is formed oversemiconductor chip 104,interconnect wires BGA support substrate 12.Protective covering 116 illustrated inFIG. 9 is a lid secured toBGA support substrate 12 by a lid attachmaterial 118. It should be understood that the type of protective covering is not limited to being a lid. For example, protective covering 114 may be a glob top material or other suitable protective material. - By now it should be appreciated that a multi-chip module having vertically stacked semiconductor chips and a method for manufacturing the multi-chip module been provided. An advantage of multi-chip modules in accordance with the present invention is that it provides a means for decreasing vibration or bounce of regions of a semiconductor chip during a wirebonding process. This improves the reliability of the wirebonds and decreases catastrophic device failure. Another advantage of the present invention is that it increases the variety in the sizes of the semiconductor chips that can be bonded to a spacer. Because the support material provides additional support for the semiconductor chip, larger chips can be mounted to the spacer. In addition, the method is readily integrable into multi-chip module processing flows in a cost and time efficient manner.
- Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. For example, the support material may be disposed on the spacer and the first semiconductor chip. Alternatively, an adhesive film can be used to couple
semiconductor chip 64 to spacer 50 rather than using a die attach material such as the attachmaterial 48. An advantage of using an adhesive material is that an adhesive material does not have to be cured. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.
Claims (20)
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US14/076,706 US20140061895A1 (en) | 2005-05-04 | 2013-11-11 | Multi-Chip Module and Method of Manufacture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/125,396 US8586413B2 (en) | 2005-05-04 | 2005-05-04 | Multi-chip module having a support structure and method of manufacture |
US14/076,706 US20140061895A1 (en) | 2005-05-04 | 2013-11-11 | Multi-Chip Module and Method of Manufacture |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/125,396 Division US8586413B2 (en) | 2005-05-04 | 2005-05-04 | Multi-chip module having a support structure and method of manufacture |
Publications (1)
Publication Number | Publication Date |
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US20140061895A1 true US20140061895A1 (en) | 2014-03-06 |
Family
ID=36677176
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/125,396 Active 2028-04-19 US8586413B2 (en) | 2005-05-04 | 2005-05-04 | Multi-chip module having a support structure and method of manufacture |
US14/076,706 Abandoned US20140061895A1 (en) | 2005-05-04 | 2013-11-11 | Multi-Chip Module and Method of Manufacture |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US11/125,396 Active 2028-04-19 US8586413B2 (en) | 2005-05-04 | 2005-05-04 | Multi-chip module having a support structure and method of manufacture |
Country Status (7)
Country | Link |
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US (2) | US8586413B2 (en) |
EP (1) | EP1878049A2 (en) |
JP (2) | JP4785917B2 (en) |
KR (1) | KR20080003864A (en) |
CN (2) | CN103531581B (en) |
TW (1) | TW200717770A (en) |
WO (1) | WO2006118994A2 (en) |
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US11088087B2 (en) * | 2018-07-25 | 2021-08-10 | Stmicroelectronics, Inc. | Micro module with a support structure |
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US8183687B2 (en) * | 2007-02-16 | 2012-05-22 | Broadcom Corporation | Interposer for die stacking in semiconductor packages and the method of making the same |
US8421214B2 (en) * | 2007-10-10 | 2013-04-16 | Vishay General Semiconductor Llc | Semiconductor device and method for manufacturing a semiconductor device |
KR101406223B1 (en) * | 2007-10-25 | 2014-06-30 | 삼성전자주식회사 | Method for manufacturing a chip on chip semiconductor device |
TWI415201B (en) * | 2007-11-30 | 2013-11-11 | 矽品精密工業股份有限公司 | Multiple chips stack structure and method for fabricating the same |
TWI468088B (en) * | 2013-05-28 | 2015-01-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of manufacture |
JP6478449B2 (en) * | 2013-08-21 | 2019-03-06 | キヤノン株式会社 | Device manufacturing method and device manufacturing method |
KR102116987B1 (en) | 2013-10-15 | 2020-05-29 | 삼성전자 주식회사 | Semiconductor package |
CN108807200A (en) * | 2014-09-26 | 2018-11-13 | 英特尔公司 | The integrated antenna package that Multi-core with wire bonding stacks |
US20170170108A1 (en) * | 2015-12-15 | 2017-06-15 | Intel Corporation | Chip carrier having variably-sized pads |
JP2021044362A (en) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | Semiconductor device |
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Also Published As
Publication number | Publication date |
---|---|
EP1878049A2 (en) | 2008-01-16 |
JP2011205116A (en) | 2011-10-13 |
JP2008541431A (en) | 2008-11-20 |
US8586413B2 (en) | 2013-11-19 |
US20060249826A1 (en) | 2006-11-09 |
KR20080003864A (en) | 2008-01-08 |
CN103531581A (en) | 2014-01-22 |
JP4785917B2 (en) | 2011-10-05 |
TW200717770A (en) | 2007-05-01 |
CN101171683A (en) | 2008-04-30 |
CN103531581B (en) | 2016-12-07 |
WO2006118994A2 (en) | 2006-11-09 |
WO2006118994A3 (en) | 2007-05-10 |
JP5518789B2 (en) | 2014-06-11 |
CN101171683B (en) | 2014-02-12 |
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