KR101184470B1 - 다이 소에서 적층 다이들의 층간접착강도의 향상 - Google Patents

다이 소에서 적층 다이들의 층간접착강도의 향상 Download PDF

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KR101184470B1
KR101184470B1 KR1020100086522A KR20100086522A KR101184470B1 KR 101184470 B1 KR101184470 B1 KR 101184470B1 KR 1020100086522 A KR1020100086522 A KR 1020100086522A KR 20100086522 A KR20100086522 A KR 20100086522A KR 101184470 B1 KR101184470 B1 KR 101184470B1
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die
molding compound
tsv
mounting material
molding
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KR1020100086522A
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KR20110028224A (ko
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보이 리
충딩 왕
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

집적회로구조는 TSV를 포함하는 제1다이; 상기 제1다이 위로 상기 제1다이와 접합되는 제2다이; 및 상기 제1다이와 제2다이 위의 부분을 포함하는 몰딩 컴파운드를 포함하며, 상기 제1다이는 상기 제2다이와 마주하는 표면을 가진다. 상기 몰딩 컴파운드는 상기 제2다이의 표면과 접촉한다. 또한, 상기 몰딩 컴파운드는 상기 제2다이의 상기 표면 아래로 연장되는 부분을 포함한다.

Description

다이 소에서 적층 다이들의 층간접착강도의 향상 {Improving the Delamination Resistance of Stacked Dies in Die Saw}
본 출원은 2009년 9월 11일에 미국에 출원된 미국 가출원 번호 No. 61/241,637(발명의 명칭 "다이 소에서 적층된 다이들의 층간접착강도)의 우선권 주장 출원으로서, 상기 가출원은 참조로서 본 출원에 통합된다.
본 발명은 일반적으로 직접회로에 관한 것이며, 상세하게는 다이들을 적층하는 방법에 관한 것이고, 더욱 상세하게는 적층된 다이들(stacked dies)을 포함하는 패키지 어셈블리(package assembly)와 이를 포장하는 방법에 관한 것이다.
직접회로의 제조가 시작된 이래로 반도체 산업은 다양한 전자부품들(예를 들면, 트랜지스터, 다이오드, 저항, 캐퍼시터 등)의 집적밀도의 계속적인 향상에 의해 급속한 성장을 끊임없이 경험하여 왔다. 대개는 집적밀도의 향상은 최소 피처 크기(feature size)의 반복된 감소에 기인하며, 이는 더 많은 부품이 주어진 영역에 집적될 수 있도록 한다.
집적된 부품들이 차지하는 체적은 본질적으로 반도체 웨이퍼의 표면이라는 점에서, 이와 같은 집적도의 향상은 성격상 본질적으로 2차원적이다. 리소그라피(lithography)의 극적인 향상이 2차원 집적회로 형성에 상당한 향상을 가져왔지만, 2차원에서 달성할 수 있는 밀도에는 물리적으로 한계가 있다. 이와 같은 한계 중의 하나는 이러한 부품들을 만들기 위해 필요한 최소 크기이다. 또한, 더 많은 소자를 한 개의 칩(chip)에 넣을 경우, 디자인이 더 복잡해진다.
추가적인 한계는 소자의 개수가 증가함에 따라 소자들 사이의 상호연결의 개수 및 길이가 현저하게 증가한다는 것이다. 상호연결의 개수 및 길이가 증가하면, 회로 RC 지연(circuit RC delay)과 전력소비가 둘 다 증가한다.
상기와 같은 한계를 해결하기 위한 노력들 중에서 3차원 집적회로(3D ICs)와 적층 다이(stacked dies)가 주로 사용된다. 관통-실리콘 비아(TSVs, through-silicon vias)가 다이들을 연결하기 위해 3차원 직접회로와 적층 다이에서 흔히 사용된다. 이경우에 TSV들은 다이 위의 집적회로를 다이 후면에 연결하기 위해 사용된다. 또한, TSV들은 집적회로의 그라운드(ground)를 다이 후면에 연결하기 위한 짧은 그라운드 경로를 제공하기 위해 사용된다. 다이 후면은 전형적으로 접지된 알루미늄 필름(grounded aluminum film)에 의해 덮여 있다. TSV들을 포함하는 다이의 적층을 향상하는 방법이 연구되어 진다.
본 실시예의 일 측면에 따르면, 집적회로구조는 적어도 한 개의 관통-실리콘 비아(TSV)를 포함하는 제1다이, 상기 제1다이는 제2다이와 마주하는 표면을 구비하며, 상기 제1다이 위로 결합된 제2다이, 및 상기 제1다이와 제2다이 상측으로 일부분을 포함하는 몰딩 컴파운드(molding compound)를 포함한다. 상기 몰딩 컴파운드는 상기 제2다이의 표면에 접촉한다. 또한, 상기 몰딩 컴파운드는 상기 제2다이의 표면 아래로 연장된 부분을 포함한다.
다른 실시예들 또한 개시된다.
본 발명과 그 이점들의 더 완전한 이해를 위해, 첨부된 도면과 함께 아래의 설명이 참조된다. 여기서,
도 1A 내지 도 8은 일 실시예에 따른 패키지 어셈블리의 제조에서 중간 단계들을 나타내는 사시도와 단면도들이고, 여기서 다이의 재분배선과 범프는 다이가 다른 다이와 결합되기 전에 형성된다.
도 9A 내지 도 17은 다른 실시예에 따른 패키지 어셈블리의 제조에서 중간 단계들을 나타내는 사시도와 단면도들이며, 여기서 다이의 재분배선과 범프는 다이가 다른 다이와 결합된 후에 형성된다.
실시예들을 만들고 사용하는 것은 아래에서 상세하게 설명한다. 그러나, 본 발명은 특정 내용의 다양한 변화로 구체화될 수 있는 많은 응용 가능한 발명 개념들을 제공한다는 것이 이해되어야 한다. 여기서 논의되는 특정한 실시예들은 단지 본 발명을 구현하고 사용할 수 있는 특정한 방법을 예시한 것이며 발명의 범위를 제한하는 것은 아니다.
관통-실리콘 비아(TSV)(관통-반도체 비아(through-semiconductor via) 또는 관통-기판 비아(through-substrate via)로도 알려짐)를 구비한 다이(die)를 포함하는 새로운 패키지 어셈블리(package assembly) 및 이를 형성하는 방법이 개시된다. 일 실시예를 제조하는 중간 단계들이 도시된다. 그리고, 상기 실시예의 변형들이 논의된다. 여러 도면과 실시예들에서 동일한 요소를 나타내기 위해 동일한 참조기호가 사용된다.
도 1a 및 도 1b는 각각 일 실시예의 초기 단계의 사시도와 단면도이다. 캐리어(4)가 제공되고 장착 물질(mounting material)(6)이 캐리어(4)의 일측에 적용되어 장착 물질(6)은 평평한 표면을 갖는다. 장착 물질(6)은 캐리어(4)에 액체 형태로 적용되고 그 후 경화(cure)될 수 있다. 일 실시예에서, 장착 물질(6)은 다음 공정 단계에서 제거되고, 왁스(wax), 접착제(glues), b-스테이지 물질들(b-stage materials) 등과 같은 재사용 가능한 물질들(reusable materials)을 포함할 수 있다. 재사용 가능 물질은 캐리어(4)로부터 제거된 후 수거될 수 있으며, 다른 캐리어들에 재사용될 수 있다. 따라서, 장착 물질(6)은 또한 재사용 물질(reusable material)(6)로 불리 운다.
그 안에 TSV(16)를 포함하는 TSV 다이(10; 예컨대 제1다이)는 장착 물질(6)에 설치된다. 일 실시예에서, TSV 다이(10)가 장착 물질(6)에 설치되기 전에, 재분배선(RDLs, redistribution lines)(12)과 범프들(bumps)(14)이 TSV 다이(10)의 전면(도 1B에서 아래를 향하는 면)에 미리 형성된다. TSV들(16)은 TSV 다이(10)에서 반도체 기판(예를 들면, 실리콘 기판)(미도시)에 형성된다. 일 실시예에서, 도 1b에 도시된 바와 같이, TSV들(16)은 구리 함유 범프(copper-containing bumps)의 형태(예를 들면, 구리 기둥)로 반도체 기판을 관통하여 TSV 다이(10)의 후면(도 1b에서 위를 향하는 면)으로부터 돌출된다. 다른 실시예에서, TSV들(16)은 TSV 다이(10)의 후면에 형성된 본드 패드(bond pads)(미도시)에 연결된다.
도 2a 및 도 2b를 참조하면, 상부 다이(20; 예컨대 제2다이)는 TSV 다이(10)에, 예를 들면, 플립 칩 본딩(flip-chip bonding)을 통해 결합된다. 상부 다이(20) 속의 회로들은 TSV 다이(10) 속의 TSV들(16)에 전기적으로 연결된다. 상부 다이(20)와 TSV 다이(10)는 그 안에 CMOS 트랜지스터(complementary metal-oxide-semiconductor transistors)와 같은 집적회로(미도시)를 포함할 수 있다. 상부 다이(20)는 TSV 다이(10)의 크기보다 작거나 동일한 크기를 가질 수 있다. 도 3에서, 언더필(underfill)(22)은 결합부를 보호하기 위해 상부 다이(20)와 TSV 다이(10)의 사이 공간에 실시된다. 그 후 언더필(22)이 경화된다.
각각 동일 구조의 사시도와 단면도인 도 4a 및 도 4b를 참조하면, 웨이퍼 레벨 몰딩이 수행되고, 몰딩 컴파운드(molding compound)(24)는 상부 다이(20)와 TSV 다이(10)를 덮도록 몰드된다. 경화된 후, 결과로 얻어진 몰딩 컴파운드(24)는 평평한 상면을 갖는다. 몰딩 컴파운드(24)는 적층된 구조(stacked structure)를 보호하고, 최종 구조에 남아 있다. 따라서, 몰딩 컴파운드(24)는 레진(resin)과 같은 일반적으로 사용되는 몰딩 컴파운드 물질을 사용할 수 있다. 도 4b는 TSV 다이(10)와 접촉 장착 물질(contacting mounting material)(6) 사이의 공간에 몰딩 컴파운드(24)가 채워진 것을 보여준다. 일 실시예에 따르면 TSV 다이(10)는 상부 다이(20)와 마주하는 제1표면을 포함하고 몰딩 컴파운드(24)는 TSV 다이(10)의 제1표면에 접촉할 수 있다. 몰딩 컴파운드(24)는 TSV 다이(10)의 제1표면 아래로 연장되는 제1부분을 포함할 수 있다. 몰딩 컴파운드(24)의 제1부분의 하면은 또한 TSV 다이(10)의 하면(예컨대 제2표면)들과 실질적으로 같은 높이에 있을 수 있다. 몰딩 컴파운드(24)는 TSV 다이(10)의 바로 위에 있는 제2부분을 더 포함할 수 있다. 따라서, 상부 다이들(20)은 몰딩 컴파운드(24)에 의해 서로 이격되어 있으며, TSV 다이들(10)은 몰딩 컴파운드(24)에 의해 서로 이격되어 있다.
도 5는 몰딩 컴파운드(24)에 장착되는 다이싱 테이프(dicing tape)(26)를 나타낸다. 다이싱 테이프(26)는 그 안에 다이싱 프레임(28)을 포함할 수 있다. 다이싱 테이프(26)가 장착된 후, 다이싱 테이프(26)는 몰딩 컴파운드(24)에 부착된다. 다음으로, 도 6a(사시도)와 도 6b(단면도)에 도시된 바와 같이, 캐리어(4)는 장착 물질(6)을 제거함으로써 몰딩 컴파운드(24)로부터 분리된다. 장착 물질(6)로 사용되는 물질에 따라, 물 또는 다른 용매를 사용하여 제거가 수행될 수 있다. 장착 물질(6)이 재사용될 수 있는 실시예들에서, 도 6a 및 도 6b에 도시된 바와 같은 단계가 수행된 후에 제거된 재사용 물질(6)은 수거되어 재사용될 수 있다. 재사용 물질의 재사용에 있어서, 도 1과 도 5에 도시된 공정 단계들이 반복되어 추가적인 상부 다이들을 추가적인 TSV 다이들에 부착하고, 다른 장착 물질(6)을 형성하기 위해 수거된 재사용 물질(6)이 가해질 수 있다(캐리어(4)와 유사한 다른 캐리어에). 이는 도 2에 도시된 것과 유사하다. 다른 실시예에서, 캐리어(4)는 TSV 다이(10)에 자외선 풀(ultra-violet(UV) glue)을 통해 부착된다. 그래서, 캐리어는 UV 풀을 UV 광에 노출시킴으로써 분리될 수 있다.
다음으로, 도 6a 및 도 6b에 도시된 것처럼, 상기 구조에 다이 소(die saw)가 수행된다. 결과로 얻어지는 한 조각의 적층 다이(이하, 웨이퍼 레벨 몰딩 유닛(30)이라 칭한다)의 단면도가 도 7에 도시되어 있다. 다이 소에서, 잘리는 선(25)은 TSV 다이의 가장자리(27)와 상부 다이(20)의 가장자리(29)로부터 이격되어 있다. 결과로 얻어진 웨이퍼 레벨 몰딩 유닛(30)에서, 상부 다이(20)과 TSV 다이(10)는 둘 다 몰딩 컴파운드(24)에 의해 덮여 있고, TSV 다이(10)의 가장자리(27)와 상부 다이(20)의 가장자리(29)는 몰딩 컴파운드(24)에 의해 덮여 있다. 몰딩 컴파운드(24)가 표면(32)(상부 다이(20)를 마주하는 TSV 다이(10)의 후면) 아래로 연장되기 때문에 적층 구조의 절단(sawing) 중에 발생할 수 있는 디라미네이션(delamination)이 감소된다는 것이 관측된다. 결과적으로 얻어지는 패키지 어셈블리(package assembly)의 신뢰성 시험(reliability test) 결과도 향상된다.
도 8을 참조하면, 웨이퍼 레벨 몰딩 유닛(30)은 범프(bumps)(14)를 통해 패키지 기판(package substrate)(36)에 접착된다. 다른 실시예에서, 웨이퍼 레벨 몰딩 유닛(30)은 와이어 본딩(wire bonding)(미도시)을 통해 패키지 기판(36)에 접착될 수 있다. 언더필(38)은 또한 웨이퍼 레벨 몰딩 유닛(30)과 패키지 기판(36) 사이에 실시된다. 볼 그리드 어레이(BGA: ball-grid-array) 볼(40)은 솔더 볼(solder ball)이며, 패키지 기판(36)에 장착될 수 있다.
도 9a 내지 도 17은 다른 실시예를 나타낸다. 이 실시예에서, RDLs(12)와 범프들(14)(도 15 참조)은, TSV 다이(10)가 장착 물질(6)에 장착되기 전에 미리 형성되는 대신에, 캐리어(4)의 접착이 분리된 후에 형성된다. 특정하지 않는 한, 본 실시예에서 사용되는 동일한 참조번호는 앞의 실시예에서 사용된 구성요소와 동일한 구성요소를 나타낸다. 본 실시예의 재료와 공정의 상세는 도 1a 내지 도 8에 도시된 실시예를 참조함으로써 알 수 있다. 각각 동일한 구조의 사시도와 단면도인 도 9a 및 도 9b를 참조하면, TSV 다이(10)는 장착 물질(6)에 장착되고, 장착 물질(6)은 캐리어(4)에 인가된다. TSV 다이(10)의 전면(도 9b에서 아래를 향하는 면)에는 RDL과 범프가 형성되지 않는다.
도 10a 내지 도 15에 도시된 공정 단계들은 도 2 내지 도 6에 도시된 단계들과 본질적으로 동일하다. 도 10a 및 도 10b에서, 상부 다이(20)는 TSV 다이(10)에 접착된다. 그 후, 언더필(22)은 도 11a 및 도 11b에 도시된 바와 같이 상부 다이(20)와 TSV 다이(10) 사이에 실시된다. 도 12a 및 도 12b를 참조하면, 웨이퍼 레벨 몰딩은 몰딩 컴파운드(24)로 상부 다이(20)와 TSV 다이(10)를 덮도록 수행된다. 도 13에서, 다이싱 테이프(26)는 몰딩 컴파운드(24)에 장착되고, 다음으로 도 14a 및 도 14b에 도시된 바와 같이 캐리어(4)가 디본딩(de-bonding)된다.
다음으로, 도 15에 도시된 바와 같이, RDL들(12)과 범프들(14)이 형성된다. RDL들(12)과 범프들(14) 형성의 상세한 내용은 공지 기술이므로 여기서는 논의하지 않는다. 다음, 도 15에 도시된 바와 같이, 다이 소가 상기 구조에 대해 수행된다. 결과로서 얻어진 웨이퍼 레벨 몰딩 유닛(30)의 한 개가 도 16에 도시되어 있다. 다시, 다이 소 중에 절단되는 선은 상부 다이(20)와 TSV 다이(10)의 가장자리로부터 이격되어 있으므로, 상부 다이(20)와 TSV 다이(10)의 가장자리는 노출되지 않는다. 도 17은 웨이퍼 레벨 몰딩 유닛(30)을 패키지 기판(36)에 접착한 것을 나타낸다.
상기 실시예들은 몇 가지 유리한 특징이 있다. 몰딩 컴파운드가 상부 다이(20)를 마주하는 TSV 다이(10)의 표면 아래로 연장될 수 있도록 함으로써, 다이 소 공정(die saw process)에서 디라미네이션(적층 분리)과 크래킹(cracking)이 발생할 가능성이 줄어든다. 그래서, 결과로 얻어지는 패키지 어셈블리의 신뢰성이 향상된다.
실시예들과 그 이점이 상세하게 설명되었으나, 첨부된 청구항에 의해 정의된 본 개시내용의 정신과 범위를 벗어남 없이 다양한 변경, 치환, 교체가 행해질 수 있다는 것을 이해해야 한다. 더욱이, 본 출원의 범위는 상세한 설명에서 기술한 공정, 기계, 제조, 및 재질, 수단, 방법, 및 단계들의 조합인 특정한 실시예에 한정되는 것은 아니다. 당해 기술분야의 통상의 기술을 가진자는 본 발명의 설명으로부터, 여기에서 설명된 대응되는 실시예가 본 발명에 따라 사용될 때 실질적으로 동일한 기능을 수행하거나 또는 실질적으로 동일한 결과를 얻을 수 있는, 현재 존재하거나 후에 개발될, 공정, 기계, 제조, 물질의 조합, 수단, 방법, 또는 단계들을 쉽게 이해할 것이다. 따라서, 첨부된 청구항은 그러한 공정, 기계, 제조, 물질의 조합, 수단, 방법, 또는 단계들을 그 범위에 포함한다. 또한, 각 청구항은 별개의 실시예를 구성하며, 여러 청구항과 실시예들의 조합은 실시예의 범위에 속한다.

Claims (10)

  1. 장착 물질;
    상기 장착 물질에 놓이고 적어도 한 개의 관통-기판 비아(TSV,trough-substrate via)를 포함하는 제1다이;
    상기 제1다이 위로 상기 제1다이와 접합되는 제2다이; 및
    상기 제1다이와 상기 제2다이 상측의 일 부분을 포함하는 몰딩 컴파운드;를 포함하며,
    상기 제1다이는 상기 제2다이와 마주하는 제1표면을 포함하고,
    상기 몰딩 컴파운드는 상기 제1다이의 상기 제1표면과 접촉하며,
    상기 몰딩 컴파운드는 상기 제1다이의 상기 제1표면 아래로 상기 장착 물질의 상면까지 연장되는 제1부분을 포함하고, 상기 장착 물질은 상기 제1다이를 캐리어상에 장착하도록 구성되고 제거 가능한 것인 집적회로구조.
  2. 제 1 항에 있어서,
    상기 제1다이의 아래에 있으며, 상기 제1다이에 접착되는 패키지 기판을 더 포함하는 것인 집적회로구조.
  3. 제 1 항에 있어서,
    상기 몰딩 컴파운드는 상기 제1다이의 바로 위에 있는 제2부분을 더 포함하며,
    상기 제1부분과 상기 제2부분은 동일한 물질로 형성된 것인 집적회로구조.
  4. 제 1 항에 있어서,
    상기 제2다이는 상기 제1다이내의 상기 TSV에 접착되고, 상기 제2다이는 상기 제1다이보다 작은 크기를 갖는 것인 집적회로구조.
  5. 제 1 항에 있어서,
    상기 몰딩 컴파운드는 상기 제1다이의 제2표면과 실질적으로 동일한 높이의 하부 표면을 포함하며,
    상기 제1다이의 제2표면은 상기 제1표면에 대해 상기 제1다이의 반대 측에 있는 것인 집적회로구조.
  6. 삭제
  7. 관통-기판 비아(TSV)를 포함하는 하부 다이를 제공하는 단계;
    하부 다이 위에 상부 다이를 접착하는 단계; 및
    상기 하부 다이와 상기 상부 다이상에 몰딩 컴파운드를 몰딩하는 단계;를 포함하며,
    상기 하부 다이는 상기 상부 다이를 마주하는 표면을 포함하며,
    상기 몰딩 컴파운드는 상기 상부 다이의 표면에 접촉하며,
    상기 몰딩 컴파운드는 상기 상부 다이의 표면 아래로 연장되는 부분을 포함하고,
    상기 상부 다이를 상기 하부 다이 위에 접착하는 단계 전에,
    캐리어상에 장착 물질을 액체 형태로 장착하는 단계;
    상기 장착 물질을 경화하는 단계; 및
    상기 하부 다이를 상기 장착 물질 위에 놓는 단계;를 더 포함하는 것인 집적회로구조 형성방법.
  8. 삭제
  9. 제 7 항에 있어서,
    상기 상부 다이를 상기 하부 다이에 접착하는 단계 전에, 상기 하부 다이상에 재분배선과 범프를 형성하는 단계를 더 포함하는 것인 집적회로구조 형성방법.
  10. 제 7 항에 있어서,
    상기 몰딩 컴파운드를 몰딩하는 단계 후에, 상기 하부 다이상에 재분배선과 범프를 형성하는 단계를 더 포함하는 것인 집적회로구조 형성방법.
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JP2011061205A (ja) 2011-03-24
TW201110319A (en) 2011-03-16
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KR20110028224A (ko) 2011-03-17
US20110062592A1 (en) 2011-03-17

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