JP2011061205A - 集積回路構造及びその形成方法 - Google Patents

集積回路構造及びその形成方法 Download PDF

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Publication number
JP2011061205A
JP2011061205A JP2010202746A JP2010202746A JP2011061205A JP 2011061205 A JP2011061205 A JP 2011061205A JP 2010202746 A JP2010202746 A JP 2010202746A JP 2010202746 A JP2010202746 A JP 2010202746A JP 2011061205 A JP2011061205 A JP 2011061205A
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die
integrated circuit
circuit structure
tsv
molding compound
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JP5135400B2 (ja
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Bo-I Lee
柏毅 李
Tsung-Ding Wang
宗鼎 王
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

【課題】ダイ切断におけるスタックダイの剥離抵抗性を改善した集積回路構造及びその形成方法を提供する。
【解決手段】集積回路構造は、TSV（スルーシリコンビア）を含む第１のダイ１０と、第１のダイ１０上に接合される第２のダイ２０であって、第１のダイ１０が、第２のダイ２０に対面する表面を有する第２のダイ２０と、一部が第１のダイ１０と第２のダイ２０上に位置する成形合成物２４材料と、からなる。成形合成物２４は第２のダイ２０の表面に接触する。更に、成形合成物２４が第２のダイ２０の表面下方に延伸する。
【選択図】図８

Description

本発明は、集積回路に関するものであって、特に、ダイをスタックする方法に関し、更に、特に、スタックダイを含むパッケージアセンブリとそれをパッケージする方法に関するものである。
各種電子素子（例えば、トランジスタ、ダイオード、レジスタ、キャパシタ等）において、集積密度（integration density）上の継続した改善により、集積回路の製造、及び、半導体産業は、急速な成長を続けている。集積密度の改善は、多くが、最小特徴寸法の繰り返し縮減によるもので、更に多くの素子を与えられた面積内に集積することができる。
これらの集積化の改善は、本来、実質的に二次元（two-dimensional、２D）でなされ、集積素子が占める体積は、実質上、半導体ウェハの表面上である。リソグラフィの劇的な改善は、既に、二次元の集積回路形成において大幅な改善をもたらしているが、二次元で達成できる集積密度には、物理的限界がある。これらの限界の一つは、これらの素子の製造に必要な最小寸法である。また、更に多くの装置を一チップ内に配置する時に、更に複雑な設計が必要になる。
もう一つの限界は、装置数量の増加に伴い、装置間の相互接続（interconnection）の数量と長さが大幅に増加することである。相互接続の数量と長さが増加する時、回路のRC遅延、及び、電力消費も増加する。
上述の限界を解決する方法として、通常、３次元の集積回路（three-dimensional integrated circuits 、3D ICs)、及び、スタックダイを用いる。３次元の集積回路とスタックダイにおいては、ダイを接続するために、しばしばスルーシリコンビア（Through-silicon vias、TSVs)を使用する。この場合、TSVを使用して、一ダイ上の集積回路をこのダイの背面に接続する。加えて、TSVは、集積回路中のグランドをこのダイの背面に接続するための短い接地経路を提供するために使用され、それは、通常、接地されたアルミニウム膜により被覆される。よって、TSVを含むダイのスタックを増加させる方法が必要である。
本発明は、スタックダイを含むパッケージアセンブリとそのパッケージ方法を提供し、上述の問題を解決することを目的とする。
本発明のある態様によると、集積回路構造は、少なくとも１つのTSVを含む第１のダイと、第１のダイ上に接合される第２のダイであって、第１のダイは、第２のダイに対面する表面を有する、第２のダイと、一部が第１のダイと第２のダイ上に位置する成形合成物と、からなる。成形合成物は第２のダイの表面に接触する。更に、成形合成物の一部が第２のダイの表面下方に延伸する。
別の実施の形態も開示される。
ダイ切断プロセス中の層間剥離とクラッキングの可能性を減少させ、パッケージアセンブリの信頼度が改善する。
第１の実施の形態によるパッケージアセンブリの初期段階の斜視図である。 第１の実施の形態によるパッケージアセンブリの初期段階の断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、頂部ダイがフリップチップ接合によってＴＳＶダイに接合された状態を示す斜視図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、頂部ダイがフリップチップ接合によってＴＳＶダイに接合された状態を示す断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、アンダーフィルが頂部ダイとＴＳＶダイとの間の空間に投与された状態を示す断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形が実行された構造の斜視図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形が実行された構造の断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、ダイシングテープが成形合成物に取り付けられる状態を示す斜視図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、取り付け用材料の除去により、キャリアが成形合成物から剥離された状態を示す斜視図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、取り付け用材料の除去により、キャリアが成形合成物から剥離された状態を示す断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において得られたスタックダイ（ウェハレベルの成形ユニット）の一片の断面図である。 第１の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形ユニットがバンプを介してパッケージ基板に接合された状態を示す断面図である。 第２の実施の形態によるパッケージアセンブリの初期段階の斜視図である。 第２の実施の形態によるパッケージアセンブリの初期段階の断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、頂部ダイがフリップチップ接合によってＴＳＶダイに接合された状態を示す斜視図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、頂部ダイがフリップチップ接合によってＴＳＶダイに接合された状態を示す断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、アンダーフィルが頂部ダイとＴＳＶダイとの間の空間に投与された状態を示す斜視図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、アンダーフィルが頂部ダイとＴＳＶダイとの間の空間に投与された状態を示す断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形が実行された構造の斜視図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形が実行された構造の断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、ダイシングテープが成形合成物に取り付けられる状態を示す斜視図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、取り付け用材料の除去により、キャリアが成形合成物から剥離された状態を示す斜視図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、取り付け用材料の除去により、キャリアが成形合成物から剥離された状態を示す断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、再分配線とバンプが形成された状態を示す断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において得られたウェハレベルの成形ユニットの一片の断面図である。 第２の実施の形態によるパッケージアセンブリの中間段階において、ウェハレベルの成形ユニットのパッケージ基板への接合を示す断面図である。
実施の形態の製造および使用について、以下詳細に説明する。しかしながら、これら実施の形態は、特殊な状況の広い多様性において実施され得る、多くの応用可能な発明の概念を提供している、と理解されるべきである。述べられた特殊な実施の形態は、単に、実施の形態を製造および使用するための特殊な方法を示しているに過ぎず、実施の形態の範囲に制限されない。
スルーシリコンビア（TSV）（スルー半導体ビア、或いは、スルー基板ビアとして知られている）を有するダイ（die）からなる新しいパッケージアセンブリ、及び、それを形成する方法を提示する。実施の形態を製造する中間段階を説明する。その後、実施の形態の各種変形を討論する。図示された実施の形態と各種図面中、同じ符号は同じ素子を示す。
図１Aおよび図１Bは、それぞれ、実施の形態による初期段階の斜視図および断面図である。キャリア（Carrier）４が提供され、取り付け用材料（mounting material）６がキャリア４の一方の側に塗布され、取り付け用材料６は平坦な表面を有する。取り付け用材料６は、液体の形で、キャリア４に塗布され、その後、硬化されてよい。一実施の形態において、取り付け用材料６は後続の処理工程で除去され、取り付け用材料６は、ワックス、接着剤（ゲル）、ｂ段階材料（b-stage materials）等の再利用可能な材料（reusable material）から成ってよい。再利用可能な材料は、キャリア４から除去された後、収集されてよく、他のキャリア上に再利用されてよい。従って、取り付け用材料６は、また再利用可能な材料６と称される。
内部にTSV１６を含むTSVダイ１０は、取り付け用材料６上に取り付けられる。一実施の形態において、TSVダイ１０が取り付け用材料６上に取り付けられる前、再分配線（RDL）１２とバンプ１４（図１B）がTSVダイ１０の正面（正面は、図１Bで示される下向きの面）上に予め形成される。TSV１６は、TSVダイ１０の半導体基板（例えば、シリコン基板）（図示しない）に形成される。一実施の形態において、図１Bで示されるように、TSV１６は、半導体基板を貫通し、且つ、銅含有バンプ（例えば、銅ポスト）の形でTSVダイ１０の背面（背面は、図１Bで示される上向きの面）から突出している。別の実施の形態において、TSV１６は、ボンドパッド（図示しない）に接続され、ボンドパッドは、TSVダイ１０の背面上に形成される。
図２Aおよび図２Bを参照すると、頂部ダイ（top die）２０は、例えば、フィリップチップ接合により、TSVダイ１０に接合される。頂部ダイ２０中の回路は、TSVダイ１０中のTSV１６に電気的に接続される。頂部ダイ２０とTSVダイ１０は、その内部に相補型MOS（complementary metal-oxide-semiconductor 、CMOS)トランジスタ等の集積回路（図示しない）を含んでよい。頂部ダイ２０の寸法は、TSVダイ１０に等しいか、それより小さい。図３において、アンダーフィル（underfill）２２が頂部ダイ２０とTSVダイ１０間の空間に投与されて、接合構造を保護する。アンダーフィル２２は、その後、硬化される。
同一構造の、それぞれ、斜視図および断面図である、図４Aおよび図４Bを参照すると、ウェハレベル（wafer-level）の成形が実行され、成形合成物（molding compound）２４が成形されて、頂部ダイ２０とTSVダイ１０を被覆する。硬化後、得られた成形合成物２４は平坦な頂部表面を持つ。成形合成物２４はスタック構造を保護し、最終構造で残される。従って、成形合成物２４は、樹脂のような常用の成形合成材料を用いることができる。図４Bは、成形合成物２４が、TSVダイ１０と接触する取り付け用材料６間の空間に充填されることを示す。成形合成物２４の底部表面も、TSVダイ１０の底部表面とほぼ同じ水平面であってよい。従って、頂部ダイ２０は、成形合成物２４により互いに離され、TSVダイ１０も、成形合成物２４により互いに離される。
図５は、成形合成物２４上に取り付けられたダイシングテープ（dicing tape）２６を示す。ダイシングテープ２６は、その中にダイシングフレーム（dicing frame）２８を含んでよい。取り付け後、ダイシングテープ２６は成形合成物料２４に付着される。次に、図６A（斜視図）と図６B（断面図）で示されるように、取り付け用材料６の除去により、キャリア４が、成形合成物２４から剥離（de-bonded）される。取り付け用材料６に用いられる材料によるが、水かほかの溶剤を用いて、除去が実行されてよい。取り付け用材料６が再利用可能である実施の形態において、図６Aと図６Bで示される工程が実行された後、除去された再利用可能な材料６は、収集され、再利用されてよい。再利用可能な材料の再利用において、図１と図５で示される処理工程が繰り返されて、その他の頂部ダイをその他のTSVダイに接合すると共に、収集された再利用可能な材料６を（キャリア４と同様の別のキャリア上に）塗布して、別の取り付け用材料６を形成してよく、それは図２で示されるものと同様である。他の実施の形態において、キャリア４は、紫外線（UV）ゲルを介してTSVダイ１０に付着され、UVゲルをUV光に露光することにより、キャリア４を剥離してよい。
次に、図６Aおよび図６Bで示される構造に、ダイ切断が実行される。得られたスタックダイ（以後、「ウェハレベルの成形ユニット３０」と称する。）の一片の断面図が図７で示される。ダイ切断において、切り口線（kerf line）２５は、TSVダイの辺縁２７と頂部ダイ２０の辺縁２９から隔てられる。得られたウェハレベルの成形鋳造ユニット３０において、頂部ダイ２０とTSVダイ１０は、成形合成物２４により被覆され、TSVダイ１０の辺縁２７と頂部ダイ２０の辺縁２９も、成形合成物２４により被覆される。成形合成物２４は、表面３２（TSVダイ１０の背面は、頂部ダイ２０に面する）下方に延伸するので、スタック構造の切断において発生する層間剥離が減少する。得られたパッケージアセンブリの信頼性試験結果も改善される。
図８を参照すると、ウェハレベルの成形ユニット３０が、バンプ１４を介してパッケージ基板３６上に接合される。他の実施の形態において、ウェハレベルの成形ユニット３０は、ワイヤボンディング（図示しない）を介してパッケージ基板３６に接合されてもよい。アンダーフィル３８が、ウェハレベルの成形ユニット３０とパッケージ基板３６と間にも投与される。ソルダーボール（solder ball）であるボールグリッドアレイ（Ball-grid-array、BGA）ボール４０も、パッケージ基板３６上に取り付けられてよい。
図９A〜図１７は、別の実施の形態を示す。この実施の形態において、RDL１２とバンプ１４（図１５を参照）は、TSVダイ１０が取り付け用材料６に取り付けられる前に予め形成される代わり、キャリア４が剥離された後に形成される。特に定めのない限り、本実施の形態で用いられる同様の参照符号は、前述の実施の形態中で用いられる同様の素子を表す。本実施の形態の材料と詳細な処理も、図１A〜図８で示される実施の形態を参照することにより理解できるだろう。それぞれ、同一構造の斜視図および断面図である、図９Aおよび図９Bを参照すると、TSVダイ１０は、取り付け用材料６上に取り付けられされ、取り付け用材料６は、更に、キャリア４上に塗布される。TSVダイ１０の正面（正面は、図９B中で示される下向きの面）上に形成されるRDLとバンプがない。
図１０A〜図１５で示される処理工程は、実質上、図２〜図６と同じである。図１０Aおよび図１０Bにおいて、頂部ダイ２０はTSVダイ１０に接合される。その後、図１１Aおよび図１１Bで示されるように、アンダーフィル２２が、頂部ダイ２０とTSVダイ１０と間に投与される。図１２Aおよび図１２Bを参照すると、ウェハレベルの成形が実行されて、成形合成物２４で頂部ダイ２０とTSVダイ１０を被覆する。図１３において、ダイシングテープ２６が成形合成物２４上に取り付けられて、図１４Aと図１４Bで示されるように、キャリア４を剥離する。
次に、図１５に示されるように、RDL１２とバンプ１４が形成される。RDL１２とバンプ１４の形成の詳細はこの技術分野において知られており、ここで討論しない。次に、図１５で示されるように、ダイ切断が基板上で実行され、得られたウェハレベルの成形ユニット３０の一つが図１６で示される。再び、ダイ切断の間、切り口線が、頂部ダイ２０とTSVダイ１０の辺縁から隔てられ、頂部ダイ２０とTSVダイ１０の辺縁が露出しない。図１７は、ウェハレベルの成形ユニット３０のパッケージ基板３６への接合を示す。
実施の形態は幾つかの長所を有する。成形合成物を、頂部ダイ２０に面するTSVダイ１０表面下方に延伸させることにより、ダイ切断処理中の層間剥離とクラッキングの可能性が減少される。これにより、得られたパッケージアセンブリの信頼度が改善される。
実施の形態とその利点について詳細に説明したが、添付の特許請求の範囲によって規定されたような開示の精神と範囲を脱しないで、各種の変更、代替、および改変がなされ得ると理解されるべきである。更に、本発明の保護範囲は、明細書中に記載された、処理、機械、製造、および物質の組成、手段、方法および工程の特定の実施の形態に限定されることを意図していない。当業者は、この開示から、ここに存在し又は後で開発される、処理、機械、製造、物質の組成、手段、方法又は工程を容易に理解できるであろうし、ここに記載された対応する実施の形態が開示に従って使用されたとき、実質的に同じ機能を実行し又は同じ結果を達成する。従って、添付の特許請求の範囲は、その保護範囲内で、そのような処理、機械、製造、物質の組成、手段、方法、又は工程を含むのを意図している。加えて、各請求項は、別々の実施の形態を構成し、種々の請求項と実施の形態の組み合わせは、実施の形態の範囲内にある。
４ キャリア
６ 取り付け用材料
１０ TSVダイ
１２ 再分配線（RDL）
１４ バンプ
１６ TSV
２０ 頂部ダイ
２２、３８ アンダーフィル
２４ 成形合成物
２５ 切り口線
２６ ダイシングテープ
２７ TSVダイの辺縁
２８ ダイシングフレーム
２９ 頂部ダイの辺縁
３０ ウェハレベルの成形ユニット
３２ TSVダイが頂部ダイに対面する表面
３６ パッケージ基板
４０ ボールグリッドアレイボール

Claims (10)

  1. 少なくとも一つのスルー基板ビア（TSV）を含む第１のダイと、
    前記第１のダイ上に接合される第２のダイであって、前記第１のダイは前記第２のダイに対面する第１の表面を有する、第２のダイと、
    一部が前記第１のダイと前記第２のダイ上に位置する成形合成物と、
    からなる集積回路構造であって、前記成形合成物は、前記第１のダイの前記第１の表面に接触し、かつ、前記成形合成物は、前記第１のダイの前記第１の表面下方に延伸する第１の部分を有することを特徴とする集積回路構造。
  2. 更に、前記第１のダイ底下に接合するパッケージ基板を含むことを特徴とする請求項１に記載の集積回路構造。
  3. 前記成形合成物は、更に、直接、前記第１のダイ上にある第２の部分を有し、前記第１の部分と前記第２の部分は同一の材料からなることを特徴とする請求項１に記載の集積回路構造。
  4. 前記第２のダイは、前記第１のダイ中の前記TSVに接合され、前記第２のダイの寸法は、前記第１のダイより小さいことを特徴とする請求項１に記載の集積回路構造。
  5. 前記成形合成物は、前記第１のダイの第２の表面とほぼ同じレベルの底部表面を含み、前記第１のダイの前記第２の表面は、前記第１の表面より前記第１のダイの反対側にあることを特徴とする請求項１に記載の集積回路構造。
  6. 更に、前記第１のダイ底下に接合するパッケージ基板を含むことを特徴とする請求項４に記載の集積回路構造。
  7. 集積回路構造を形成する方法であって、
    スルー基板コンビア（ＴＳＶ）を含む底部ダイを提供するステップと、
    前記底部ダイ上に頂部ダイを接合するステップであって、前記底部ダイは、前記頂部ダイに対面する表面を有するステップと、
    前記底部ダイと前記頂部ダイとの上に、成形合成物を成形するステップであって、前記成形合成物は、前記頂部ダイの前記表面と接触し、かつ、前記成形合成物は、前記頂部ダイの前記表面下方に延伸する一部を有するステップと、
    を含むことを特徴とする集積回路構造の形成方法。
  8. 更に、前記底部ダイ上に、前記頂部ダイを接合するステップの前に、
    液体の形状態で、取り付け用材料をキャリアに取り付けるステップと、
    前記取り付け用材料を硬化するステップと、
    前記取り付け用材料上に、前記底部ダイを置くステップと、
    を含むことを特徴とする請求項７に記載の集積回路構造の形成方法。
  9. 更に、前記頂部ダイを前記底部ダイに接合するステップの前に、
    前記底部ダイ上に、再分配線とバンプを形成するステップを含むことを特徴とする請求項７に記載の集積回路構造の形成方法。
  10. 更に、前記成形合成物を成形するステップの後に、前記底部ダイ上に、再分配線とバンプを形成するステップを含むことを特徴とする請求項７に記載の集積回路構造の形成方法。
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