CN110071048B - 半导体封装以及制造该半导体封装的方法 - Google Patents

半导体封装以及制造该半导体封装的方法 Download PDF

Info

Publication number
CN110071048B
CN110071048B CN201910030665.XA CN201910030665A CN110071048B CN 110071048 B CN110071048 B CN 110071048B CN 201910030665 A CN201910030665 A CN 201910030665A CN 110071048 B CN110071048 B CN 110071048B
Authority
CN
China
Prior art keywords
semiconductor chip
trench
section
carrier substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910030665.XA
Other languages
English (en)
Other versions
CN110071048A (zh
Inventor
金兑炯
金泳龙
南杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN110071048A publication Critical patent/CN110071048A/zh
Application granted granted Critical
Publication of CN110071048B publication Critical patent/CN110071048B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

公开了半导体封装以及制造该半导体封装的方法。制造半导体封装的方法可以包括：提供载体基板，该载体基板具有形成在载体基板的第一顶表面上的沟槽；在载体基板上提供第一半导体芯片；将至少一个第二半导体芯片安装在第一半导体芯片的第二顶表面上；涂覆模构件以围绕第一半导体芯片的第一侧表面和所述至少一个第二半导体芯片的第二侧表面；以及固化模构件以形成模层。该沟槽可以沿着第一半导体芯片的第一边缘提供。该模构件可以覆盖第一半导体芯片的底表面的第二边缘。

Description

半导体封装以及制造该半导体封装的方法
技术领域
与示例实施方式一致的装置和方法涉及一种半导体封装以及制造该半导体封装的方法。
背景技术
电子产业已经兑现了提供具有诸如重量轻、尺寸紧凑、高速度和高性能的特性的廉价电子产品的承诺。半导体封装被提供来实现用于电子产品的集成电路芯片。需要各种研究来提高半导体封装的性能。特别地，已经提出贯穿硅通路(TSV)技术作为满足半导体封装中需要的高性能的要求的解决方案，在该半导体封装中传统地使用引线接合技术。
电子产品倾向于在集成电路封装中需要更多的集成电路，同时具有讽刺意味的是，为增加的集成电路容量提供系统中的更少的物理空间。于是，一些技术集中在将这样的集成电路堆叠到单个封装中。半导体封装的其它方法堆叠多个集成电路管芯、提供封装内封装(PIP)或其组合。
发明内容
一些示例实施方式提供一种具有改善的结构稳定性的半导体封装。
一些示例实施方式提供一种制造半导体封装的方法，在该方法中失败率降低。
根据示例实施方式的一方面，一种制造半导体封装的方法可以包括：提供载体基板，该载体基板具有形成在载体基板的第一顶表面上的沟槽；在载体基板上提供第一半导体芯片；将至少一个第二半导体芯片安装在第一半导体芯片的第二顶表面上；涂覆模构件以围绕第一半导体芯片的第一侧表面和所述至少一个第二半导体芯片的第二侧表面；以及固化模构件以形成模层。该沟槽可以沿着第一半导体芯片的第一边缘提供。该模构件可以覆盖第一半导体芯片的底表面的第二边缘。
根据示例实施方式的一方面，一种半导体封装可以包括：芯片堆叠，包括第一半导体芯片、安装在第一半导体芯片的顶表面上的至少一个第二半导体芯片以及设置在第一半导体芯片下面的多个连接端子；和围绕芯片堆叠的第一侧表面的模层。该模层可以包括：第一区段，围绕第一半导体芯片的第二侧表面和所述至少一个第二半导体芯片的第三侧表面；以及第二区段，从第一区段的第一底端延伸并覆盖第一半导体芯片的底表面的边缘。
附图说明
从以下结合附图对示例实施方式的描述，以上和/或其它的方面将变得明显并更易于理解，附图中：
图1示出剖视图，示出根据一示例实施方式的半导体封装；
图2和图3示出平面图，示出模层；
图4示出剖视图，示出模层的第二区段；
图5至图10示出剖视图，示出根据一示例实施方式的制造半导体封装的方法；
图11示出剖视图，示出沟槽；
图12和图13示出平面图，示出第一载体基板；以及
图14至图16示出剖视图，示出制造半导体封装的方法，该方法使用不具有沟槽的载体基板。
具体实施方式
现在将参照附图详细地参考示例实施方式。在附图中，省略与描述无关的部分以清楚地描述示例实施方式，并且在整个说明书中，相同的附图标记指代相同的元件。在这方面，本示例实施方式可以具有不同的形式，而不应被解释为限于这里阐述的描述。
在整个说明书中，当描述某个元件“连接”到另一元件时，应当理解，所述某个元件可以“直接连接”到另一元件或者经由在中间的另一元件“电连接”到另一元件。此外，当一部件“包括”一元件时，除非存在另一与其相反的描述，否则应当理解，该部件不排除另一元件，而是还可以包括另一元件。
在下文，参照附图详细描述本公开。
图1示出剖视图，示出根据一示例实施方式的半导体封装。图2和图3示出平面图，其示出模层，图1对应于沿着图2或图3的线I-I'截取的剖视图。
可以提供芯片堆叠S。芯片堆叠S可以包括第一半导体芯片100、一个或更多个第二半导体芯片200、以及第三半导体芯片300。
第一半导体芯片100可以包括第一电路层110和第一贯穿电极120。第一电路层110可以包括存储电路。第一贯穿电极120可以垂直地穿透第一半导体芯片100。第一贯穿电极120和第一电路层110可以彼此电连接。第一半导体芯片100的底表面100a可以是有源表面。例如，连接端子130可以提供在第一半导体芯片100的底表面100a上。
一个或更多个第二半导体芯片200可以安装在第一半导体芯片100上。每个第二半导体芯片200可以包括第二电路层210和第二贯穿电极220。第二电路层210可以包括存储电路。第二贯穿电极220可以垂直地穿透第二半导体芯片200。第二贯穿电极220和第二电路层210可以彼此电连接。第二半导体芯片200的底表面可以是有源表面。第一凸块322可以提供在第二半导体芯片200中的最下面一个和第一半导体芯片100之间，将第一半导体芯片100和最下面的第二半导体芯片200彼此电连接。第二凸块324可以提供在相邻的第二半导体芯片200之间，将相邻的第二半导体芯片200彼此电连接。
第三半导体芯片300可以安装在第二半导体芯片200中的最上面的一个上。例如，第三半导体芯片300可以是安装在包括第一至第三半导体芯片100、200和300的芯片堆叠S的顶部处的最上面的芯片。第三半导体芯片300可以包括第三电路层310。第三电路层310可以包括存储电路。第三半导体芯片300的底表面可以是有源表面。第三凸块326可以提供在第三半导体芯片300和最上面的第二半导体芯片200之间，将第三半导体芯片300和最上面的第二半导体芯片200彼此电连接。在某些实施方式中，第三半导体芯片300可以被省略或不形成。
底填充层330可以提供在第一至第三半导体芯片100、200和300中的相邻的半导体芯片之间。底填充层330可以插设在第一至第三凸块322、324和326中的相邻的凸块之间，因此可以防止第一凸块322之间、第二凸块324之间和第三凸块326之间的电短路。底填充层330可以包括环氧基树脂或无机填充剂。
模层400可以设置在芯片堆叠S的一侧上。模层400可以覆盖芯片堆叠S的侧表面以及芯片堆叠S的底表面的一部分，该底表面可以例如与第一半导体芯片100的底表面100a基本上相同。相同的附图标记100a可以用于指代芯片堆叠S的底表面和第一半导体芯片100的底表面两者。例如，模层400可以包括在第一至第三半导体芯片100、200和300的侧表面上的第一区段410和在第一半导体芯片100的底表面100a上的第二区段420。当在平面图中观看时，第一区段410可以沿着芯片堆叠S的侧表面延伸。第一区段410可以具有在与芯片堆叠S的顶端的水平面相同的水平面处(例如，齐平、相同的高度等)的顶端410a以及在与芯片堆叠S的底端的水平面相同的水平面处的底端410b，芯片堆叠S的该底端可以例如与第一半导体芯片100的底表面100a共平面。第二区段420可以从第一区段410的底端410b延伸到第一半导体芯片100的底表面100a上。当在平面图中观看时，第二区段420可以与第一区段410的至少一部分和第一半导体芯片100的一部分重叠。然后，模层400可以覆盖芯片堆叠S的底部拐角Sa。芯片堆叠S的底部拐角Sa可以表示芯片堆叠S的每个侧表面与芯片堆叠S的底表面100a相遇的点。如图2所示，第二区段420可以覆盖第一半导体芯片100的底表面100a的边缘并暴露第一半导体芯片100的底表面100a的中心。第二区段420可以暴露连接端子130，同时与连接端子130间隔开。第二区段420的平面形状可以是基本上对应于第一半导体芯片100的平面形状的环形。在一些实施方式中，第二区段420可以在平面图中具有四边形环形状(例如，中间掏空的四边形)。例如，第一半导体芯片100的底表面100a可以在通过第二区段420暴露的部分处具有四边形形状。或者，如图3所示，第一半导体芯片100的底表面100a可以在通过第二区段420暴露的部分处具有八边形形状。在这种情况下，第一区段410的底端410b可以被部分地暴露。
从第一半导体芯片100的底表面100a到连接端子130的底端的第一长度L1可以大于从第一半导体芯片100的底表面100a到第二区段420的底端的第二长度L2。例如，第二长度L2可以是第一长度L1的约0.1至0.5倍。如果第一长度L1小于第二长度L2，则当半导体封装10安装在模块基板上时，第二区段420会防止连接端子130与模块基板接触。例如，当安装半导体封装10时，连接端子130可能熔化以在高度上降低。在这种情况下，当第二长度L2大于第一长度L1的约0.5倍时，第二区段420会防止连接端子130联接到模块基板。为了在安装半导体封装10时可靠地获得最小底填充间隙，第一长度L1和第二长度L2之间的差异可以大于约4μm。模层400可以包括环氧模塑化合物(EMC)。
图1示出模层400，其第二区段420完全覆盖第一区段410的底端410b，但是本公开不限于此。图4示出模层的第二区段的放大剖视图，部分地示出半导体封装。如图4所示，第二区段420可以设置在第一区段410和第一半导体芯片100之间的边界上。当在平面图中观看时，第二区段420可以覆盖第一区段410的底端410b的一部分和第一半导体芯片100的一部分，同时暴露第一区段410的底端410b的其它部分。
根据一示例实施方式，模层400可以从芯片堆叠S的侧表面形成到芯片堆叠S的底表面100a。模层400可以保护芯片堆叠S的底部拐角Sa，该底部拐角Sa可能对机械冲击敏感，因此半导体封装10可以在结构稳定性上提高。
图5至图10示出剖视图，示出根据一示例实施方式的制造半导体封装的方法。图11示出剖视图，其示出沟槽。图12和图13示出平面图，示出第一载体基板，图5至图10示出沿着图12或图13的线II-II'截取的剖视图。在随后的示例实施方式中，与参照图1至图3讨论的部件基本上相同的部件被分配与其相同的附图标记，并且为了便于描述，将省略或缩短其重复描述。
参照图5，可以在第一载体基板500上形成沟槽T。第一载体基板500可以包括硅晶片或绝缘基板诸如玻璃或陶瓷。沟槽T可以通过部分地去除第一载体基板500的上部形成。例如，沟槽T可以通过执行去除工艺诸如钻孔、激光烧蚀或激光切割而形成。沟槽T可以从第一载体基板500的顶表面500a朝向第一载体基板500的内部延伸。例如，当在剖面中观看时，沟槽T可以具有四边形形状。或者，当在如图11所示的剖面中观看时，沟槽T可以具有半圆形和三角形中的一种，每种形状具有从第一载体基板500的顶表面500a朝向第一载体基板500的内部减小的宽度。
参照图5和图12，沟槽T可以限定芯片安装区域CA，第一半导体芯片(见图8的100)在随后的工艺中安装在芯片安装区域CA中。当在平面图中观看时，芯片安装区域CA可以被沟槽T围绕。例如，当在平面图中观看时，沟槽T可以沿着芯片安装区域CA的边缘形成。沟槽T可以具有与芯片安装区域CA的边缘重叠的第一区域Ta和在芯片安装区域CA外部的第二区域Tb。当在如图12所示的平面图中观看时，沟槽T可以具有网格形状。例如，沟槽T可以包括在第一方向DR1上延伸的第一沟槽T1和在与第一方向DR1交叉的第二方向DR2上延伸的第二沟槽T2。第一沟槽T1和第二沟槽T2可以限定每个具有四边形形状(诸如矩形或正方形形状)的区域。或者，如图13所示，沟槽T还可以包括在第一沟槽T1和第二沟槽T2的交叉点附近的第三沟槽T3，该交叉点的附近可以对应于例如芯片安装区域CA的拐角。第三沟槽T3可以与芯片安装区域CA的拐角重叠。第一沟槽T1、第二沟槽T2和第三沟槽T3可以限定每个具有八边形形状的区域。
在一些示例实施方式中，当同时制造多个半导体封装时，第一沟槽T1和第二沟槽T2可以限定彼此分开的多个区域，这些区域可以被定义为其上形成芯片堆叠(见图9的S)的多个芯片安装区域CA。为了便于描述，以下的说明集中在包括单个芯片安装区域CA的示例上。
参照图6，可以在第一载体基板500上形成第一载体粘合层510。第一载体粘合层510可以包括与沟槽T垂直地重叠的凹入部分C。例如，粘合剂构件可以涂覆在第一载体基板500上。当粘合剂构件是流体时，作用在粘合剂构件上的重力可以大于粘合剂构件的表面张力。于是，粘合剂构件可以具有向下移动(例如，下沉)到沟槽T中的部分，如图6中示出的箭头所指示的。对于沟槽T上的粘合剂构件，表面张力可以使顶表面510a具有圆化形状，而与沟槽T的形状无关。如上所述，凹入部分C可以形成在第一载体粘合层510的上部上。沟槽T可以具有大于凹入部分C的第二深度D2的第一深度D1。凹入部分C可以具有与芯片安装区域CA的边缘重叠的第三区域Ca和在芯片安装区域CA外部的第四区域Cb。
或者，第一载体粘合层510可以使用包括绝缘材料的非导电膜(NCF)形成。如图7所示，NCF可以是包括绝缘材料的聚合物带。例如，NCF可以粘附到第一载体基板500上。NCF可以具有规则的(例如，均一的)厚度，并且重力可以使NCF在沟槽T上向下移动，如图7中示出的箭头所指示的。第一载体粘合层510可以不完全地填充沟槽T。如上所述，凹入部分C可以形成在第一载体粘合层510的上部上。
参照图8，第一半导体芯片100可以粘附到第一载体基板500上。第一载体粘合层510可以将第一半导体芯片100粘附到芯片安装区域CA上。连接端子130可以提供在第一半导体芯片100的底表面100a上。第一半导体芯片100的底表面100a可以与第一载体粘合层510接触。由于形成在第一载体粘合层510上的凹入部分C的第三区域Ca与芯片安装区域CA的边缘重叠，所以第一半导体芯片100的底表面100a的边缘可以位于凹入部分C上。例如，第一半导体芯片100的底表面100a可以具有与第一载体粘合层510接触的中心以及与第一载体粘合层510间隔开的边缘。连接端子130可以埋入在第一载体粘合层510中并与凹入部分C间隔开。从第一半导体芯片100的底表面100a到连接端子130的底端的第一长度L1可以大于从第一半导体芯片100的底表面100a到凹入部分C的底端的第三长度L3。例如，第三长度L3可以是第一长度L1的约0.1至0.5倍。当第三长度L3小于第一长度L1的约0.1倍时，模构件(见图10的430)会难以在随后的工艺中被引入到凹入部分C中。为了在安装稍后将制造的半导体封装(见图1中的10)时可靠地获得最小的底填充间隙，第一长度L1和第三长度L3之间的差异可以大于约4μm。底表面100a可以是第一半导体芯片100的有源表面。
参照图9，第二半导体芯片200可以安装在第一半导体芯片100上。至少一个第二半导体芯片200可以堆叠在第一半导体芯片100上。例如，焊球和底填充层330可以粘附到第二半导体芯片200的底表面(例如有源表面)上，并且第二半导体芯片200可以面朝下，以此方式使得第二半导体芯片200的底表面设置在第一半导体芯片100的顶表面(例如无源表面)上。焊球可以回流以形成第一凸块322。第一半导体芯片100和第二半导体芯片200可以在其间提供有底填充层330，以防止第一凸块322之间的电短路。底填充层330可以包括环氧基树脂或无机填料。
以类似或相同的方式，另一第二半导体芯片200可以安装在现有的第二半导体芯片200的顶表面(例如无源表面)上。例如，第二凸块324可以形成在相邻的第二半导体芯片200之间，将相邻的第二半导体芯片200彼此电连接。相邻的第二半导体芯片200可以在其间提供有另一个底填充层330，以防止第二凸块324之间的电短路。尽管图9示出多个第二半导体芯片200，但是仅一个第二半导体芯片200可以安装在第一半导体芯片100上，或者第二半导体芯片200可以都不安装在第一半导体芯片100上。
第三半导体芯片300可以安装在第二半导体芯片200中的最上面的一个上，从而形成芯片堆叠S。第三半导体芯片300可以是安装在包括第一至第三半导体芯片100、200和300的芯片堆叠S的顶部处的最上面的芯片。例如，焊球和底填充层330可以粘附到最上面的第二半导体芯片200的底表面(例如有源表面)上，并且第三半导体芯片300可以面朝下，以此方式使得第三半导体芯片300的底表面(例如有源表面)位于最上面的第二半导体芯片200的顶表面(无源表面)上。焊球可以回流以形成第三凸块326。最上面的第二半导体芯片200和第三半导体芯片300可以在其间提供有底填充层330，以防止第三凸块326之间的电短路。
参照图10，可以涂覆模构件430以围绕第一至第三半导体芯片100、200和300的侧表面。模构件430可以填充沟槽T上的凹入部分C，同时覆盖第一至第三半导体芯片100、200和300的侧表面。由于第一载体粘合层510的凹入部分C具有与芯片安装区域CA的边缘重叠的部分(例如图8的第三区域Ca)，所以模构件430可以覆盖第一半导体芯片100的底表面100a的边缘。模构件430可以与连接端子130间隔开。模构件430可以包括绝缘聚合物材料。例如，模构件430可以包括环氧模塑化合物(EMC)。
返回参照图1，可以固化模构件(见图10的430)以形成模层400。模层400可以从芯片堆叠S的侧表面形成到底表面100a。模层400可以覆盖并保护芯片堆叠S的底部拐角Sa。
在一些示例实施方式中，当提供大量的模构件430以涂覆芯片堆叠S时，模构件430可以在芯片堆叠S的侧表面上涂覆得厚，因此，如参照图4所讨论地，模层400可以形成为具有第一区段410和部分地暴露第一区段410的底端410b的第二区段420。
第一载体基板500可以被去除以制造半导体封装10。第一载体粘合层510也可以被去除。
相反，如下面讨论地，当载体基板没有沟槽时，芯片堆叠会在其底表面和侧表面上部分地暴露。
图14至图16示出剖视图，示出一种制造半导体封装的方法，该方法使用不具有沟槽的载体基板。
参照图14，可以提供第二载体基板530。第二载体基板530可以具有平坦的顶表面530a。可以在第二载体基板530上形成第二载体粘合层540。例如，第二载体基板530可以在其上提供有粘合剂构件或NCF。第二载体粘合层540可以具有平坦的顶表面540a。第一半导体芯片100可以粘附到第二载体基板530上。连接端子130可以提供在第一半导体芯片100的底表面100a上。当第一半导体芯片100在朝向第二载体基板530的方向上被挤压时，第二载体粘合层540可以在连接端子130移动到第二载体粘合层540中的时间期间突出或溢出到第一半导体芯片100的侧表面之外。此时，第二载体粘合层540的一部分可以沿着第一半导体芯片100的侧表面在垂直于第二载体基板530的顶表面530a的方向上突出，第二载体粘合层540的突出部分可以转变成突起542。
参照图15，第二半导体芯片200可以安装在第一半导体芯片100上。至少一个第二半导体芯片200可以堆叠在第一半导体芯片100上。第三半导体芯片300可以安装在第二半导体芯片200中的最上面的一个上，该步骤可以形成芯片堆叠S。
芯片堆叠S的侧表面可以在其上提供有模层，这将在下面讨论。例如，模构件430可以涂覆在第一至第三半导体芯片100、200和300的侧表面上。模构件430可以覆盖第一半导体芯片100的侧表面上的突起542，同时覆盖第一至第三半导体芯片100、200和300的侧表面。突起542可以位于模构件430与第一半导体芯片100的侧表面之间。
参照图16，可以固化模构件430以形成模层400。模层400可以与第一半导体芯片100的侧表面的一部分间隔开，同时覆盖芯片堆叠S的侧表面。
第二载体基板530可以被去除。第二载体粘合层540也可以被去除以暴露芯片堆叠S的底部拐角Sa。芯片堆叠S的底部拐角Sa可能对机械冲击敏感，并且当芯片堆叠S的底部拐角Sa暴露时，半导体封装会在结构稳定性上降低。
在根据一示例实施方式的制造半导体封装的方法中，第一载体基板500可以在芯片堆叠S的底部拐角Sa附近具有沟槽T。因此，即使当第一半导体芯片100在朝向第一载体基板500的方向上被挤压时，第一载体粘合层510也可以不突出到第一半导体芯片100的侧表面之外。模构件430可以在随后的工艺中完全覆盖第一半导体芯片100的侧表面。因此，该制造方法可以减少或抑制其中模层400暴露芯片堆叠S的侧表面的工艺失败的发生。此外，当形成模层400时，模构件430可以覆盖第一半导体芯片100的底表面100a的边缘。例如，模层400可以形成为保护芯片堆叠S的底部拐角Sa。
在根据一示例实施方式的半导体封装中，由于模层400保护芯片堆叠S的底部拐角Sa，所以结构稳定性可以提高。
尽管已经结合附图中示出的示例实施方式描述了本公开，但是本领域普通技术人员将理解，可以在其中进行形式和细节上的变化，而没有脱离示例实施方式的精神和特征。因此，以上公开的示例实施方式应当被认为是说明性的而不是限制性的。
本申请要求于2018年1月24日在韩国知识产权局提交的韩国专利申请第10-2018-0008670号的优先权，其公开内容通过引用整体地结合于此。

Claims (17)

1.一种制造半导体封装的方法，该方法包括：
提供载体基板，该载体基板具有形成在所述载体基板的第一顶表面上的沟槽；
在所述载体基板上提供第一半导体芯片；
将至少一个第二半导体芯片安装在所述第一半导体芯片的第二顶表面上；
涂覆模构件以围绕所述第一半导体芯片的第一侧表面和所述至少一个第二半导体芯片的第二侧表面；以及
固化所述模构件以形成模层，
其中所述沟槽沿着所述第一半导体芯片的第一边缘提供，并且
其中所述模构件覆盖所述第一半导体芯片的底表面的第二边缘部分，
其中所述沟槽包括：
第一沟槽，在平行于所述载体基板的所述第一顶表面的第一方向上延伸；
第二沟槽，在平行于所述载体基板的所述第一顶表面的第二方向上延伸，所述第二方向与所述第一方向交叉；以及
第三沟槽，与所述第一沟槽和所述第二沟槽的交叉点相邻，当在平面图中观看时，所述第三沟槽与所述第一半导体芯片的拐角重叠；
其中，当涂覆所述模构件时，所述模构件被朝向所述沟槽引入。
2.根据权利要求1所述的方法，其中所述沟槽的第一部分与所述第一半导体芯片的所述第一边缘重叠，并且
其中所述沟槽的第二部分位于所述第一半导体芯片的所述第一边缘之外。
3.根据权利要求1所述的方法，其中所述第一半导体芯片包括提供在所述第一半导体芯片的所述底表面上的多个连接端子，并且
其中所述第一半导体芯片通过提供在所述第一半导体芯片的所述底表面上的粘合层被粘附到所述载体基板。
4.根据权利要求3所述的方法，其中所述粘合层包括与所述沟槽垂直地重叠的凹入部分，并且
其中，当涂覆所述模构件时，所述模构件填充所述凹入部分。
5.根据权利要求4所述的方法，其中所述凹入部分的深度为所述多个连接端子的高度的0.1至0.5倍。
6.根据权利要求3所述的方法，其中所述模构件与所述多个连接端子间隔开。
7.根据权利要求1所述的方法，其中所述沟槽的截面具有四边形、半圆形和三角形中的至少一种，并且
其中所述半圆形和所述三角形具有从所述载体基板的所述第一顶表面朝向所述载体基板的内部减小的宽度。
8.根据权利要求1所述的方法，还包括在形成所述模层之后去除所述载体基板。
9.根据权利要求1所述的方法，其中所述模层包括：
第一区段，围绕所述第一半导体芯片的所述第一侧表面和所述至少一个第二半导体芯片的所述第二侧表面；和
第二区段，从所述第一区段的底端延伸并覆盖所述第一半导体芯片的所述底表面的所述第二边缘部分。
10.一种半导体封装，包括：
芯片堆叠，包括第一半导体芯片、安装在所述第一半导体芯片的顶表面上的至少一个第二半导体芯片以及设置在所述第一半导体芯片下面的多个连接端子；和
通过涂覆模构件而形成的模层，围绕所述芯片堆叠的第一侧表面，
其中所述模层包括：
第一区段，围绕所述第一半导体芯片的第二侧表面和所述至少一个第二半导体芯片的第三侧表面，和
第二区段，从所述第一区段的第一底端延伸并覆盖所述第一半导体芯片的底表面的边缘部分；
其中所述第二区段形成在与可去除的载体基板的沟槽对应的位置；
其中所述沟槽被形成在所述载体基板的顶表面上，
其中所述沟槽包括：
第一沟槽，在平行于所述载体基板的所述顶表面的第一方向上延伸；
第二沟槽，在平行于所述载体基板的所述顶表面的第二方向上延伸，所述第二方向与所述第一方向交叉；以及
第三沟槽，与所述第一沟槽和所述第二沟槽的交叉点相邻，当在平面图中观看时，所述第三沟槽与所述第一半导体芯片的拐角重叠；
其中，当涂覆所述模构件时，所述模构件被朝向所述沟槽引入。
11.根据权利要求10所述的半导体封装，其中从所述第一半导体芯片的所述底表面到所述第二区段的第二底端的第一长度是从所述第一半导体芯片的所述底表面到所述多个连接端子的第三底端的第二长度的0.1至0.5倍。
12.根据权利要求10所述的半导体封装，其中，当在平面图中观看时，所述第二区段与所述第一区段的第一部分和所述第一半导体芯片的第二部分重叠。
13.根据权利要求10所述的半导体封装，其中所述第二区段与所述多个连接端子间隔开。
14.根据权利要求10所述的半导体封装，其中，当在平面图中观看时，所述第二区段具有环形状，所述环形状覆盖所述第一半导体芯片的所述底表面的所述边缘部分并暴露所述第一半导体芯片的所述底表面的中心。
15.根据权利要求14所述的半导体封装，其中所述第一半导体芯片的通过所述第二区段暴露的所述底表面具有四边形形状和八边形形状中的至少一种。
16.根据权利要求10所述的半导体封装，所述沟槽的截面具有四边形形状、半圆形形状和三角形形状中的至少一种，并且
其中所述半圆形形状和所述三角形形状具有随着与所述第一半导体芯片的所述底表面的距离的增大而减小的宽度。
17.根据权利要求10所述的半导体封装，其中所述第一区段的第一顶端和所述芯片堆叠的第二顶端彼此齐平，并且
其中所述第一区段的所述第一底端和所述芯片堆叠的第二底端彼此齐平。
CN201910030665.XA 2018-01-24 2019-01-14 半导体封装以及制造该半导体封装的方法 Active CN110071048B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0008670 2018-01-24
KR1020180008670A KR102503233B1 (ko) 2018-01-24 2018-01-24 반도체 패키지 및 그 제조 방법

Publications (2)

Publication Number Publication Date
CN110071048A CN110071048A (zh) 2019-07-30
CN110071048B true CN110071048B (zh) 2024-04-19

Family

ID=67300184

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910030665.XA Active CN110071048B (zh) 2018-01-24 2019-01-14 半导体封装以及制造该半导体封装的方法

Country Status (3)

Country Link
US (2) US10964670B2 (zh)
KR (1) KR102503233B1 (zh)
CN (1) CN110071048B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110459511A (zh) * 2019-07-08 2019-11-15 南通沃特光电科技有限公司 一种半导体器件叠置封装结构及其封装方法
US11742322B2 (en) * 2021-01-20 2023-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package having stress release structure
KR20220122155A (ko) * 2021-02-26 2022-09-02 삼성전자주식회사 더미 칩을 포함하는 반도체 패키지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130012500A (ko) * 2011-07-25 2013-02-04 삼성전자주식회사 칩 패키지 구조물 및 그 제조 방법

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003115563A (ja) 2001-10-04 2003-04-18 Toshiba Corp 電気部品とその製造方法
US6734039B2 (en) * 2002-09-06 2004-05-11 Advanpack Solutions Pte Ltd. Semiconductor chip grid array package design and method of manufacture
JP2006173416A (ja) 2004-12-17 2006-06-29 Matsushita Electric Ind Co Ltd 半導体装置
US8124459B2 (en) 2005-04-23 2012-02-28 Stats Chippac Ltd. Bump chip carrier semiconductor package system
US7838974B2 (en) 2007-09-13 2010-11-23 National Semiconductor Corporation Intergrated circuit packaging with improved die bonding
US8426960B2 (en) * 2007-12-21 2013-04-23 Alpha & Omega Semiconductor, Inc. Wafer level chip scale packaging
US7863109B2 (en) 2008-12-05 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof
KR20110123461A (ko) * 2010-05-07 2011-11-15 삼성전기주식회사 반도체 패키지
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR20130015885A (ko) * 2011-08-05 2013-02-14 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR101354894B1 (ko) 2011-10-27 2014-01-23 삼성전기주식회사 반도체 패키지, 그 제조방법 및 이를 포함하는 반도체 패키지 모듈
US9076882B2 (en) 2013-06-03 2015-07-07 Intel Corporation Methods for high precision microelectronic die integration
US9524942B2 (en) * 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9601463B2 (en) 2014-04-17 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) and the methods of making the same
US20170179049A1 (en) 2015-12-16 2017-06-22 Freescale Semiconductor, Inc. Power grid balancing apparatus, system and method
US9741694B2 (en) 2015-12-31 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method of manufacturing the same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130012500A (ko) * 2011-07-25 2013-02-04 삼성전자주식회사 칩 패키지 구조물 및 그 제조 방법

Also Published As

Publication number Publication date
US20190229091A1 (en) 2019-07-25
CN110071048A (zh) 2019-07-30
KR20190090162A (ko) 2019-08-01
US11705430B2 (en) 2023-07-18
KR102503233B1 (ko) 2023-02-24
US20210183821A1 (en) 2021-06-17
US10964670B2 (en) 2021-03-30

Similar Documents

Publication Publication Date Title
CN108091615B (zh) 半导体封装件
KR102605617B1 (ko) 적층 반도체 패키지
KR102649471B1 (ko) 반도체 패키지 및 그의 제조 방법
KR101096042B1 (ko) 반도체 패키지 및 그 제조방법
US8592952B2 (en) Semiconductor chip and semiconductor package with stack chip structure
KR101362715B1 (ko) 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
KR101236798B1 (ko) 웨이퍼 레벨 적층형 반도체 패키지 제조 방법
KR101078740B1 (ko) 스택 패키지 및 그의 제조방법
KR101376378B1 (ko) 반도체 장치와 그 제조 방법, 및 그것을 사용한 반도체 모듈
US11705430B2 (en) Semiconductor package including mold layer having curved cross-section shape
KR101368793B1 (ko) 반도체 패키지 및 그 제조 방법
KR20190025097A (ko) 반도체 패키지 및 그의 제조 방법
CN110581107A (zh) 半导体封装及其制造方法
KR20110105159A (ko) 적층 반도체 패키지 및 그 형성방법
CN112563215A (zh) 电子封装件及其制法
KR101573281B1 (ko) 재배선층을 이용한 적층형 반도체 패키지 및 이의 제조 방법
KR20200026344A (ko) 반도체 패키지
US10580742B2 (en) Wafer level fan-out package and method of manufacturing the same
CN112331645A (zh) 半导体封装装置
US20140099755A1 (en) Fabrication method of stacked package structure
US11495574B2 (en) Semiconductor package
CN115602640A (zh) 半导体封装
US10636760B2 (en) Semiconductor packages
KR102494595B1 (ko) 반도체 패키지
CN111403368B (zh) 半导体封装体

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant