CN112331645A - 半导体封装装置 - Google Patents

半导体封装装置 Download PDF

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Publication number
CN112331645A
CN112331645A CN202010756040.4A CN202010756040A CN112331645A CN 112331645 A CN112331645 A CN 112331645A CN 202010756040 A CN202010756040 A CN 202010756040A CN 112331645 A CN112331645 A CN 112331645A
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China
Prior art keywords
package
package substrate
preventing member
semiconductor
interposer
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CN202010756040.4A
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English (en)
Inventor
李章雨
沈钟辅
金知晃
孔永哲
金永培
金泰焕
马亨乐
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN112331645A publication Critical patent/CN112331645A/zh
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Abstract

一种半导体封装装置，可以包括第一封装衬底、位于第一封装衬底上的第一半导体芯片、位于第一半导体芯片上的插件、位于插件上的翘曲防止构件、位于插件和第一封装衬底上的模制构件以及位于模制构件上的第二封装衬底。模制构件的顶表面的至少一部分可以与第二封装衬底的底表面间隔开。

Description

半导体封装装置
相关申请的交叉引用
本申请要求于2019年8月5日在韩国知识产权局提交的韩国专利申请No.10-2019-0095025的优先权，该申请的全部公开内容以引用方式并入本文中。
技术领域
本公开涉及一种半导体封装装置，具体地，涉及一种包括插件的半导体封装装置。
背景技术
包括半导体芯片的半导体封装件可以允许半导体芯片用作电子产品的一部分。通常，半导体封装件可以包括印刷电路板(PCB)以及安装在PCB上并使用接合线或凸块电连接到PCB的半导体芯片。随着电子工业的发展，正在进行许多研究以改善半导体封装件的电学特性和操作可靠性。
发明内容
本发明构思的实施例提供了一种被配置为抑制翘曲问题并具有改善的热性能的半导体封装装置。
根据本发明构思的实施例，半导体封装装置可以包括：第一封装衬底；第一半导体芯片，其位于第一封装衬底上；插件，其位于第一半导体芯片上；翘曲防止构件，其位于插件上；模制构件，其位于插件和第一封装衬底上；以及第二封装衬底，其位于模制构件上。模制构件的顶表面的至少一部分可以与第二封装衬底的底表面间隔开。
根据本发明构思的实施例，半导体封装装置可以包括：第一封装衬底；第一半导体芯片，其位于第一封装衬底上；插件，其位于第一半导体芯片上；模制构件，其位于插件、第一半导体芯片和第一封装衬底上；位于插件上的翘曲防止构件和多个连接端子；以及第二封装衬底，其位于翘曲防止构件上并与多个连接端子电接触。模制构件的顶表面的至少一部分可以与第二封装衬底间隔开，并且在与第一封装衬底的顶表面垂直的方向上，连接端子的第一厚度可以大于翘曲防止构件的厚度。
根据本发明构思的实施例，半导体封装装置可以包括：第一封装件；第二封装件，其位于第一封装件上；以及多个连接端子，其将第一封装件电连接到第二封装件。第一封装件可以包括：第一封装衬底；第一半导体芯片，其位于第一封装衬底上；插件，其位于第一半导体芯片上；第一粘合层，其插设在第一半导体芯片与插件之间；翘曲防止构件，其位于插件上；第二粘合层，其位于翘曲防止构件与插件之间；以及第一模制构件，其位于插件和第一封装衬底上。第二封装件可以包括：第二封装衬底，其连接到多个连接端子；第二半导体芯片，其位于第二封装衬底上，并且第二半导体芯片彼此间隔开；以及第二模制构件，其位于第二半导体芯片之间的区域中以及第二半导体芯片的侧表面上。第一模制构件的上部分的至少一部分可以与第二封装衬底间隔开，并且翘曲防止构件的顶表面处可以不存在第一模制构件。翘曲防止构件可以具有在与第一封装衬底的顶表面垂直的方向上的厚度，并且翘曲防止构件的热膨胀系数大于插件的热膨胀系数。
附图说明
通过结合附图的以下简要描述，将更加清楚地理解示例实施例。附图代表如在此描述的非限制性的示例实施例。
图1A是示出了根据本发明构思的一些实施例的半导体封装装置的平面图。
图1B是沿图1A的线I-I'截取的截面图。
图2是示出根据本发明构思的一些实施例的半导体封装装置的截面图。
图3A至图3D是示出根据本发明构思的一些实施例的制造半导体封装装置的方法的截面图。
图4A是示出根据本发明构思的一些实施例的半导体封装装置的平面图。
图4B是图4A中示出的半导体封装装置的截面图。
图5A是示出根据本发明构思的一些实施例的半导体封装装置的平面图。
图5B是图5A中示出的半导体封装装置的截面图。
图6A是示出根据本发明构思的一些实施例的半导体封装装置的平面图。
图6B是图6A中示出的半导体封装装置的截面图。
图7A至图7D是示出根据本发明构思的一些实施例的制造半导体封装装置的方法的截面图。
应注意，这些附图旨在示出某些示例实施例中使用的方法、结构和/或材料的一般特性，并补充以下提供的书面描述。然而，这些附图不是按比例绘制的，并且可以不精确地反映任何给定实施例的精确结构或性能特性，并且不应被解释为限定或限制由示例实施例所涵盖的值或性能的范围。例如，为了清楚，可以减小或夸大分子、层、区域和/或结构元件的相对厚度和位置。各个附图中使用相似或相同的附图标记旨在指示相似或相同的元件或特征的存在。
具体实施方式
现在将参照其中示出了示例实施例的附图来更加充分地描述本发明构思的示例实施例。相同的附图标记或相同的附图标号可以在整个说明书中表示相同的元件或部件。
如在此使用的，术语“和/或”包括一个或多个相关所列项的任意组合和所有组合。将理解，当元件被称作“在”另一元件“上”、“附接”到另一元件、“连接”到另一元件、与另一元件“耦接”、“接触”另一元件等时，该元件可以直接在所述另一元件上、直接附接到所述另一元件、直接连接到所述另一元件、与所述另一元件直接耦接或直接接触所述另一元件，或者也可以存在中间元件。相反，例如，当元件被称作“直接在”另一元件“上”、“直接附接”到另一元件、“直接连接”到另一元件、与另一元件“直接耦接”或“直接接触”另一元件时，不存在中间元件。要注意，尽管未相对于一个实施例进行具体地描述，但是相对于所述一个实施例描述的各方面可以并入不同的实施例中。即，任何实施例的所有实施例和/或特征可以以任何方式和/或组合来结合。
图1A是示出了根据本发明构思的一些实施例的半导体封装装置的平面图。图1B是沿图1A的线I-I'截取的截面图。为了降低附图的复杂性，从图1A省略图1B中示出的一些元件。
参照图1A和图1B，根据本发明构思的一些实施例的半导体封装装置1000可以包括第一封装件PK1和位于第一封装件PK1上的第二封装件PK2。第一封装件PK1和第二封装件PK2可以通过插设于第一封装件PK1与第二封装件PK2之间的连接端子CT彼此电连接。
第一封装件PK1可以包括第一封装衬底101、第一半导体芯片102、插件103和翘曲防止构件104。
第一封装衬底101可以包括例如印刷电路板(PCB)衬底。多个焊球SB可以设置在第一封装衬底101的底表面上。焊球SB可以设置在第一封装衬底101的边缘部分中(即，如图1B的截面图中示出的封装衬底101的外部)。当半导体封装装置1000附接到母板时，焊球SB可以用作连接端子。
第一半导体芯片102可以包括例如应用处理器(AP)芯片。第一半导体芯片102可以通过附接到第一半导体芯片102的底表面的多个凸块BP电连接到第一封装衬底101。第一半导体芯片102的底表面可以用作有源表面。第一半导体芯片102的顶表面可以是无源表面。第一半导体芯片102可以以倒装芯片接合的方式安装在第一封装衬底101上。
底部填充层UF可以设置在第一半导体芯片102与第一封装衬底101之间的间隙中，以密封或封装凸块BP。底部填充层UF可以由绝缘聚合物材料(例如环氧树脂)形成或者包括绝缘聚合物材料(例如环氧树脂)。
插件103可以设置在第一半导体芯片102上。插件103可以是硅插件。插件103可以具有彼此相对的顶表面和底表面。如图1B的截面图中示出的，插件103的底表面可以面对第一半导体芯片102。
在一些实施例中，插件103的平面面积可以大于第一半导体芯片102的平面面积。当在平面图中观看时，插件103的边缘部分的至少一部分可以与第一半导体芯片102叠置。还如图1B中示出的，插件103的边缘部分的至少一部分可以在大体与第一封装衬底101的上表面垂直的竖直方向D2上不与第一半导体芯片102叠置。
第一粘合层AF1可以设置在第一半导体芯片102与插件103之间。第一粘合层AF1可以用于将插件103附接到第一半导体芯片102。第一粘合层AF1可以在如图1B中示出的D1方向上沿插件103的边缘部分的底表面(即，插件103的在D2方向上不与第一半导体芯片102叠置的部分)延伸。
再分布层(未示出)可以设置在插件103上。再分布层(未示出)可以包括绝缘层(未示出)和再分布图案CL。再分布图案CL可以包括过孔插塞(未示出)和互连线(未示出)。
多个第一焊盘PD1和多个第二焊盘PD2可以设置在插件103的顶表面上。与第一焊盘PD1相比，第二焊盘PD2可以设置在插件103在D1方向上的边缘附近。第一焊盘PD1可以是与连接端子CT接触的焊盘。连接端子CT可以竖直地(即，在D2方向上)连接到第一焊盘PD1。第一焊盘PD1可以通过再分布图案CL电连接到第二焊盘PD2。第二焊盘PD2可以通过第一接合线WL1电连接到第一封装衬底101。
翘曲防止构件104可以设置在插件103上。翘曲防止构件104可以由热膨胀系数(CTE)高于插件103的热膨胀系数的材料形成或者包括热膨胀系数(CTE)高于插件103的热膨胀系数的材料。另外，翘曲防止构件104可以被形成为热导率高于插件103的热导率。翘曲防止构件104可以包括例如铜带。
由第二封装件PK2安装在第一封装件PK1上或者半导体封装装置安装在母板上时提供的热量可能会导致翘曲问题。插件103的热膨胀系数可能小于第一封装衬底101的热膨胀系数，结果，会由于第一封装衬底101与插件103之间的热膨胀系数的这种差异而发生翘曲。因为具有较高热膨胀系数(CTE)的翘曲防止构件104设置在插件103上，所以还可以使插件103的上部分膨胀，并且这可以使得能够减少安装工艺中的翘曲问题。另外，因为翘曲防止构件104的热导率大于插件103的热导率，所以翘曲防止构件104可以将插件103的热量排出到外部(即，半导体封装装置的外部)，并且这可以使得能够抑制或防止半导体封装装置1000的内部温度升高至过高水平。另外，如以下将描述的，当将翘曲防止构件104设置为具有特定厚度时，可以通过翘曲防止构件104来实现前述效果。
翘曲防止构件104可以具有在与第一封装衬底101的顶表面平行的第一方向D1上的宽度Δ1041。插件103可以具有在第一方向D1上的宽度Δ1031。翘曲防止构件104在第一方向D1上的宽度Δ1041可以小于插件103在第一方向D1上的宽度Δ1031。翘曲防止构件104在第一方向D1上的宽度Δ1041可以大于或等于插件103在第一方向D1上的宽度Δ1031的0.3倍。翘曲防止构件104在第一方向D1上的宽度Δ1041可以为例如5mm。
翘曲防止构件104可以具有在与第一封装衬底101的顶表面垂直的第二方向D2上的厚度Δ1042。翘曲防止构件104在第二方向D2上的厚度Δ1042可以与翘曲防止构件104的厚度对应。翘曲防止构件104在第二方向D2上的厚度Δ1042可以大于插件103在第二方向D2上的厚度Δ1032。翘曲防止构件104在第二方向D2上的厚度Δ1042可以在100μm至150μm的范围内。
连接端子CT在第二方向D2上的厚度ΔCT可以等于或大于翘曲防止构件104在第二方向D2上的厚度Δ1042。连接端子CT在第二方向D2上的厚度ΔCT与翘曲防止构件104在第二方向D2上的厚度Δ1042之间的差可以小于或等于30μm。
第二粘合层AF2可以设置在翘曲防止构件104与插件103之间。第二粘合层AF2的顶表面和底表面中的每一个可以具有与翘曲防止构件104的底表面对应的面积。第二粘合层AF2可以在第二方向D2上与翘曲防止构件104叠置。第二粘合层AF2的厚度可以为例如10μm。
第一模制构件105可以被设置为至少部分地覆盖插件103、第一半导体芯片102和第一封装衬底101。第一模制构件105可以包括多个孔HL。孔HL可以被设置为至少部分地暴露插件103上的第一焊盘PD1。
第一模制构件105可以覆盖翘曲防止构件104的侧表面的至少一部分。第一模制构件105可以不覆盖翘曲防止构件104的顶表面或者不延伸到翘曲防止构件104的顶表面上。如第一封装衬底101用作最低参考层的图1B的截面图中示出的，翘曲防止构件104的顶表面104T可以设置在等于或高于第一模制构件105的顶表面105T的水平高度处。翘曲防止构件104的侧表面中的每一个的至少一部分可以被第一模制构件105暴露。
第一模制构件105的顶表面的至少一部分可以与以下将描述的第二封装衬底201的底表面间隔开。
翘曲防止构件104的顶表面104T的至少一部分可以与第二封装件PK2的底表面PK2L间隔开。翘曲防止构件104的顶表面104T与第二封装件PK2的底表面PK2L之间在第二方向D2上的距离ΔGP可以在10μm至30μm的范围内。在某些实施例中，翘曲防止构件104的顶表面104T的一部分可以与第二封装件PK2的底表面PK2L物理接触。
第二封装件PK2可以包括第二封装衬底201、多个第二半导体芯片202a和第二模制构件205。第二封装衬底201可以是例如PCB衬底。第二封装衬底201可以具有在第二方向D2上的厚度Δ201。第二封装衬底201在第二方向D2上的厚度Δ201可以小于第一封装衬底101在第二方向D2上的厚度Δ101。
各个第二半导体芯片202a可以设置在第二封装衬底201上，以便彼此间隔开。第二半导体芯片202a中的每一个可以包括例如存储器芯片。第二半导体芯片202a的顶表面可以用作有源表面。第二半导体芯片202a的底表面可以是无源表面。第二半导体芯片202a和第二封装衬底201可以通过第二接合线WL2彼此电连接，第二接合线WL2被设置为连接第二半导体芯片202a的顶表面和第二封装衬底201的顶表面。换言之，第二半导体芯片202a可以以引线接合方式安装在第二封装衬底201上。
第二封装件PK2还可以包括多个第三半导体芯片202b。第三半导体芯片202b中的每一个可以设置在第二半导体芯片202a上。第三半导体芯片202b可以各自包括例如存储器芯片。粘合膜(未示出)可以设置在第三半导体芯片202b和第二半导体芯片202a中的相应的半导体芯片之间。第三半导体芯片202b的顶表面可以用作有源表面。第三半导体芯片202b的底表面可以是无源表面。第三半导体芯片202b和第二封装衬底201可以通过第三接合线WL3彼此电连接，第三接合线WL3被设置为连接第三半导体芯片202b的顶表面和第二封装衬底201的顶表面。换言之，第三半导体芯片202b可以以引线接合方式安装在第二封装衬底201上。
第二模制构件205可以被设置为至少部分地覆盖第二封装衬底201、第二半导体芯片202a和第三半导体芯片202b。例如，第二模制构件205可以至少部分地覆盖第二半导体芯片202a之间的区域以及第二半导体芯片202a中的每一个的侧表面。第二模制构件205可以至少部分地覆盖第三半导体芯片202b之间的区域以及第三半导体芯片202b中的每一个的顶表面和侧表面。
图2是示出根据本发明构思的一些实施例的半导体封装装置1001的截面图。为了使描述简明，将通过相同的附图标记来标识先前参照图1A和图1B描述的元件，而不重复其描述。
参照图2，翘曲防止构件104可以包括硅。翘曲防止构件104可以是硅堆。可以使用硅代替铜带。因为硅可以将从第一半导体芯片102提供到插件103的热量有效地排出到半导体封装装置1001的外部，硅的使用可以改善半导体封装装置1001的散热特性。
图3A至图3D是示出根据本发明构思的一些实施例的制造半导体封装装置的方法的截面图。
参照图3A，可以准备其上安装有插件103和第一半导体芯片102的第一封装衬底101。可以在第一封装衬底101的底表面上设置焊球SB。可以在第一半导体芯片102与第一封装衬底101之间设置凸块BP。底部填充层UF可以被设置为填充凸块BP之间的间隙。插件103可以包括第一焊盘PD1、第二焊盘PD2和再分布图案CL。可以在插件103与第一半导体芯片102之间插设第一粘合层AF1。
可以通过第二粘合层AF2在插件103上安装翘曲防止构件104。翘曲防止构件104可以包括例如铜带。可以准备铜带，使得在第一方向D1上的宽度Δ1041为大约5mm。可以准备铜带，使得在第二方向D2上的厚度Δ1042在100μm至150μm的范围内。然而，本发明构思的实施例不限于该示例，铜带在第一方向D1上的宽度Δ1041和铜带在第二方向D2上的厚度Δ1042可以改变。
参照图3B，第一模制构件105可以被形成为至少部分地覆盖第一封装衬底101。
在第一模制构件105的形成期间，可以通过设置在翘曲防止构件104的顶表面上的掩模(未示出)来保护翘曲防止构件104的顶表面(即，与同第二粘合层AF2接合的表面相对的表面)。换言之，可以不在第一封装衬底101的设置有翘曲防止构件104的区域MSK上形成第一模制构件105。可以在第一封装衬底101的被掩模(未示出)暴露的区域OP上局部形成第一模制构件105。可以形成第一模制构件105，使得其顶表面105T的水平高度等于或低于翘曲防止构件104的顶表面104T的水平高度。可以在形成第一模制构件105之后去除掩模(未示出)。
参照图3C，可以在第一模制构件105中形成孔HL。可以通过激光钻孔工艺来形成孔HL。可以通过孔HL至少部分地暴露插件103的第一焊盘PD1。
参照图3D和图1B，可以在第一封装件PK1上安装第二封装件PK2。附接到第二封装件PK2的底表面的多个初始连接端子PCT可以与第一封装件PK1的第一焊盘PD1对准，并附接到第一封装件PK1的第一焊盘PD1。初始连接端子PCT可以通过回流焊工艺来形成附接到第一焊盘PD1的连接端子CT。第二封装件PK2的安装工艺可以包括压缩工艺PR。如图1B中示出的，即使当第二封装件PK2安装在第一封装件PK1上时，翘曲防止构件104的顶表面104T也可以与第二封装件PK2的底表面PK2L间隔开。在某些实施例中，在回流焊工艺期间，翘曲防止构件104的顶表面104T的一部分可以与第二封装件PK2的底表面PK2L物理接触。
图4A是示出根据本发明构思的一些实施例的半导体封装件装置2000的平面图。图4B是图4A中示出的半导体封装装置的截面图。为了降低附图的复杂性，从图4A省略图4B中示出的一些元件。为了使描述简明，将由相同的附图标记来标识先前参照图1A和图1B描述的元件，而不重复其描述。
参照图4A和图4B，第一模制构件105可以至少部分地覆盖插件103的顶表面。第一模制构件105的顶表面的至少一部分可以与第二封装衬底201的底表面间隔开。第一模制构件105可以被形成为具有限定在插件103上的凹槽gv。
翘曲防止构件104可以设置在凹槽gv中。例如，第一模制构件105的一部分可以插设在翘曲防止构件104与插件103之间。翘曲防止构件104可以与插件103间隔开，且第一模制构件105的一部分插设于翘曲防止构件104与插件103之间。翘曲防止构件104的底表面可以与第一模制构件105的一部分物理接触。翘曲防止构件104的侧表面的至少一部分可以被第一模制构件105包围。翘曲防止构件104的一部分可以从第一模制构件105的凹槽gv的侧表面延伸，以至少部分地覆盖第一模制构件105的顶表面的一部分。
翘曲防止构件104的顶表面104T可以与第二封装件PK2的底表面PK2L物理接触。翘曲防止构件104可以不与连接端子CT物理接触。当在平面图中观看时，翘曲防止构件104可以被连接端子CT部分包围或全部包围。
可以通过使液体非导电胶(NCP)凝固来形成翘曲防止构件104。非导电胶可以包括例如聚合物。凝固的非导电胶的热膨胀系数可以高于插件103的热膨胀系数。在一些实施例中，翘曲防止构件104也可以用作将第一封装件PK1附接到第二封装件PK2的粘合层。
翘曲防止构件104在第一方向D1上的宽度Δ1041可以大于插件103在第一方向D1上的宽度Δ1031的0.3倍。翘曲防止构件104在第二方向D2上的厚度Δ1042可以大于插件103在第二方向D2上的厚度Δ1032。翘曲防止构件104在第二方向D2上的厚度Δ1042可以在100μm至250μm的范围内。例如，翘曲防止构件104在第二方向D2上的厚度Δ1042可以为大约150μm。
凹槽gv可以具有在第一方向D1上的宽度ΔGV1，并且孔HL可以具有在第一方向D1上的宽度ΔHL1。凹槽gv在第一方向D1上的宽度ΔGV1可以大于孔HL在第一方向D1上的宽度ΔHL1。凹槽gv可以具有在第二方向D2上的深度ΔGV2，并且孔HL可以具有在第二方向D2上的深度ΔHL2。凹槽gv在第二方向D2上的深度ΔGV2可以小于孔HL在第二方向D2上的深度ΔHL2。
图5A和图5B是示出根据本发明构思的一些实施例的半导体封装装置2001的图。为了使描述简明，将由相同的附图标记来标识先前参照图4A和图4B描述的元件，而不重复其描述。
参照图5A和图5B，第一模制构件105可以包括多个第一凹槽gv1。第一翘曲防止构件104a可以设置在第一凹槽gv1中的每一个中。当在平面图中观看时，第一翘曲防止构件104a中的每一个可以具有圆形形状或像圆形的形状。当在平面图中观看时，第一翘曲防止构件104a可以二维布置在第一模制构件105上。
图6A和图6B是示出根据本发明构思的一些实施例的半导体封装装置2002的图。为了使描述简明，将由相同的附图标记标识先前参照图4A和图4B描述的元件，而不重复其描述。
参照图6A和图6B，第一模制构件105可以包括第一凹槽gv1和第二凹槽gv2。当在平面图中观看时，第二翘曲防止构件104b可以至少部分地包围第一翘曲防止构件104a。当在平面图中观看时，第二凹槽gv2可以具有环形、方形或矩形形状。
图7A至图7D是示出根据本发明构思的一些实施例的制造半导体封装装置的方法的截面图。
参照图7A，可以准备其上安装有插件103和第一半导体芯片102的第一封装衬底101。可以在第一封装衬底101的底表面上设置焊球SB。可以在第一半导体芯片102与第一封装衬底101之间设置凸块BP。底部填充层UF可以被设置为至少部分地填充凸块BP之间的间隙。插件103可以包括第一焊盘PD1、第二焊盘PD2和再分布图案CL。可以在第一焊盘PD1上设置第一初始连接端子PCT1。在一些实施例中，如图3A中示出的，可以省略第一初始连接端子PCT1。可以在插件103与第一半导体芯片102之间插设第一粘合层AF1。
第一模制构件105可以被形成为至少部分地覆盖第一封装衬底101。第一模制构件105可以至少部分地覆盖插件103的顶表面和侧表面。第一模制构件105的形成可以包括形成模制材料(未示出)以至少部分地覆盖第一封装衬底101以及固化该模制材料。
参照图7B，可以在第一模制构件105的上部分中形成凹槽gv和孔HL。可以通过激光钻孔工艺来形成凹槽gv和孔HL。
在某些实施例中，在固化模制材料(未示出)之前，可以通过使用额外的浇铸模具(未示出)来形成凹槽gv。孔HL可以被形成为使插件103的第一焊盘PD1暴露。
参照图7C，可以从放置在第一模制构件105上的源SC朝向凹槽gv分配液体翘曲防止材料P104。液体翘曲防止材料P104可以包括例如液体非导电胶(NCP)。可以形成液体翘曲防止材料P104以选择性地至少部分地填充凹槽gv。孔HL可以不用液体翘曲防止材料P104来填充(例如，可以不含液体翘曲防止材料P104)。
结合图7D参照图4B，可以在第一封装件PK1上安装第二封装件PK2。附接到第二封装件PK2的底表面的多个第二初始连接端子PCT2可以与第一封装件PK1的第一初始连接端子PCT1对准，然后可以通过回流焊工艺被回流焊以形成连接端子CT。第二封装件PK2的安装工艺可以包括压缩工艺PR。可以执行压缩工艺PR，以使液体翘曲防止材料P104与第二封装件PK2的底表面接触。在该工艺中，液体翘曲防止材料P104的一部分可以溢流到第一模制构件105的顶表面的凹槽gv附近的一部分，但是不会进入孔HL中。
在一些实施例中，在压缩工艺和回流焊工艺之后，还可以执行固化工艺。固化工艺可以是在比回流焊工艺中的温度低的温度下执行的热处理工艺。可以通过固化工艺使液体翘曲防止材料P104的未凝固部分凝固以形成翘曲防止构件104。
根据本发明构思的一些实施例，当硅插件用作用于半导体封装装置的插件的材料时，与使用由有机材料制成的衬底相比，能够改善半导体封装装置的散热特性。然而，使用硅插件会导致翘曲问题。通过将具有高热膨胀系数的材料放置在硅插件上，能够缓解翘曲问题。
另外，根据本发明构思的一些实施例，其中不设置连接端子的硅插件上的空间可以被设置为具有有效结构，并且翘曲防止构件可以附接到该空间。因此，能够有效地抑制翘曲问题。另外，翘曲防止构件可以被设置为具有特定材料和特定厚度，并且这可以使得能够更加有效地抑制翘曲问题。
根据本发明构思的一些实施例，能够抑制半导体封装装置的翘曲问题，并且改善半导体封装装置的热导率性质。
尽管已经具体示出并描述了本发明构思的示例实施例，但是本领域普通技术人员将理解，在不脱离所附权利要求的精神和范围的情况下，可以在此做出形式和细节上的变化。

Claims (20)

1.一种半导体封装装置，包括：
第一封装衬底；
第一半导体芯片，其位于所述第一封装衬底上；
插件，其位于所述第一半导体芯片上；
翘曲防止构件，其位于所述插件上；
模制构件，其位于所述插件和所述第一封装衬底上；以及
第二封装衬底，其位于所述模制构件上，
其中，所述模制构件的顶表面的至少一部分与所述第二封装衬底的底表面间隔开。
2.根据权利要求1所述的半导体封装装置，其中，所述翘曲防止构件的热膨胀系数高于所述插件的热膨胀系数。
3.根据权利要求1所述的半导体封装装置，其中，所述翘曲防止构件的热导率高于所述插件的热导率。
4.根据权利要求1所述的半导体封装装置，其中，所述翘曲防止构件包括铜或硅堆。
5.根据权利要求4所述的半导体封装装置，其中，在与其上具有所述第一半导体芯片的所述第一封装衬底的顶表面垂直的方向上，所述翘曲防止构件的厚度大于所述插件的厚度。
6.根据权利要求5所述的半导体封装装置，其中，在与所述第一封装衬底的顶表面平行的方向上，所述翘曲防止构件的宽度小于所述插件的宽度。
7.根据权利要求6所述的半导体封装装置，其中，所述翘曲防止构件的厚度在100μm至150μm的范围内。
8.根据权利要求1所述的半导体封装装置，还包括位于所述第二封装衬底上的第二半导体芯片，
其中，在与所述第一封装衬底的顶表面垂直的方向上，所述第一封装衬底的厚度大于所述第二封装衬底的厚度。
9.根据权利要求8所述的半导体封装装置，其中，所述插件包括第一焊盘、第二焊盘和将所述第一焊盘和所述第二焊盘彼此电连接的再分布图案，并且
其中，所述第二焊盘通过接合线电连接到所述第一封装衬底。
10.根据权利要求9所述的半导体封装装置，还包括连接到所述第一焊盘的连接端子，
其中，在与所述第一封装衬底的顶表面垂直的方向上，所述连接端子的第一厚度大于所述翘曲防止构件的厚度，并且
所述连接端子的第一厚度与所述翘曲防止构件的厚度之间的差小于或等于30μm。
11.根据权利要求1所述的半导体封装装置，其中，相对于作为基线水平高度的所述第一封装衬底的顶表面，所述翘曲防止构件的顶表面的水平高度等于或高于所述模制构件的顶表面的水平高度。
12.根据权利要求1所述的半导体封装装置，其中，所述翘曲防止构件的侧表面的至少一部分处不存在所述模制构件。
13.一种半导体封装装置，包括：
第一封装衬底；
第一半导体芯片，其位于所述第一封装衬底上；
插件，其位于所述第一半导体芯片上；
模制构件，其位于所述插件、所述第一半导体芯片和所述第一封装衬底上；
位于所述插件上的翘曲防止构件和多个连接端子；以及
第二封装衬底，其位于所述翘曲防止构件上，并与所述多个连接端子电接触，
其中，所述模制构件的顶表面的至少一部分与所述第二封装衬底间隔开，并且
在与所述第一封装衬底的顶表面垂直的方向上，所述连接端子的第一厚度大于所述翘曲防止构件的厚度。
14.根据权利要求13所述的半导体封装装置，其中，当在平面图中观看时，所述连接端子围绕所述翘曲防止构件。
15.根据权利要求14所述的半导体封装装置，其中，所述插件具有彼此相对的顶表面和底表面，
其中，所述插件还包括位于所述插件的顶表面上的焊盘和位于所述插件的底表面上的粘合层，并且
其中，所述焊盘中的一些焊盘在与所述第一封装衬底的顶表面垂直的方向上与所述连接端子叠置。
16.根据权利要求14所述的半导体封装装置，其中，所述模制构件包括凹槽和孔，
其中，所述翘曲防止构件位于所述凹槽中，
其中，所述连接端子中的每一个位于所述孔中，并且
其中，所述孔的深度大于所述凹槽的深度。
17.根据权利要求16所述的半导体封装装置，其中，所述模制构件的一部分插设在所述翘曲防止构件与所述插件之间。
18.根据权利要求13所述的半导体封装装置，其中，所述翘曲防止构件包括凝固的非导电胶。
19.根据权利要求13所述的半导体封装装置，其中，所述翘曲防止构件的厚度在100μm至150μm的范围内。
20.一种半导体封装装置，包括：
第一封装件；
第二封装件，其位于所述第一封装件上；以及
多个连接端子，其将所述第一封装件电连接到所述第二封装件，
其中，所述第一封装件包括：
第一封装衬底；
第一半导体芯片，其位于所述第一封装衬底上；
插件，其位于所述第一半导体芯片上；
第一粘合层，其插设在所述第一半导体芯片与所述插件之间；
翘曲防止构件，其位于所述插件上；
第二粘合层，其位于所述翘曲防止构件与所述插件之间；以及
第一模制构件，其位于所述插件和所述第一封装衬底上，
其中，所述第二封装件包括：
第二封装衬底，其连接到所述多个连接端子；
第二半导体芯片，其位于所述第二封装衬底上，并且所述第二半导体芯片彼此间隔开；以及
第二模制构件，其位于所述第二半导体芯片之间的区域中以及所述第二半导体芯片的侧表面上，
其中，所述第一模制构件的上部分的至少一部分与所述第二封装衬底间隔开，
其中，所述翘曲防止构件的顶表面处不存在所述第一模制构件，并且
其中，所述翘曲防止构件具有在与所述第一封装衬底的顶表面垂直的方向上的厚度，并且所述翘曲防止构件的热膨胀系数大于所述插件的热膨胀系数。
CN202010756040.4A 2019-08-05 2020-07-31 半导体封装装置 Pending CN112331645A (zh)

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Publication number Priority date Publication date Assignee Title
KR20200121126A (ko) * 2019-04-15 2020-10-23 삼성전자주식회사 반도체 패키지
US11527518B2 (en) * 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW579555B (en) 2000-03-13 2004-03-11 Ibm Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus
KR100702968B1 (ko) 2005-11-24 2007-04-03 삼성전자주식회사 플로팅된 히트 싱크를 갖는 반도체 패키지와, 그를 이용한적층 패키지 및 그의 제조 방법
JP4753725B2 (ja) * 2006-01-20 2011-08-24 エルピーダメモリ株式会社 積層型半導体装置
WO2008120755A1 (ja) * 2007-03-30 2008-10-09 Nec Corporation 機能素子内蔵回路基板及びその製造方法、並びに電子機器
JP5144222B2 (ja) * 2007-11-14 2013-02-13 新光電気工業株式会社 配線基板及びその製造方法
US8035210B2 (en) 2007-12-28 2011-10-11 Stats Chippac Ltd. Integrated circuit package system with interposer
US8270176B2 (en) 2008-08-08 2012-09-18 Stats Chippac Ltd. Exposed interconnect for a package on package system
US20100244212A1 (en) 2009-03-27 2010-09-30 Jong-Woo Ha Integrated circuit packaging system with post type interconnector and method of manufacture thereof
US8080446B2 (en) 2009-05-27 2011-12-20 Stats Chippac Ltd. Integrated circuit packaging system with interposer interconnections and method of manufacture thereof
JP2011061132A (ja) 2009-09-14 2011-03-24 Zycube:Kk インターポーザ
US8829342B2 (en) 2009-10-19 2014-09-09 The University Of Toledo Back contact buffer layer for thin-film solar cells
US8699232B2 (en) 2011-09-20 2014-04-15 Stats Chippac Ltd. Integrated circuit packaging system with interposer and method of manufacture thereof
US9748203B2 (en) 2011-12-15 2017-08-29 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
KR101874803B1 (ko) 2012-01-20 2018-08-03 삼성전자주식회사 패키지 온 패키지 구조체
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US8963311B2 (en) 2012-09-26 2015-02-24 Apple Inc. PoP structure with electrically insulating material between packages
KR102186203B1 (ko) 2014-01-23 2020-12-04 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
JP2016058627A (ja) 2014-09-11 2016-04-21 株式会社東芝 半導体装置
KR102243287B1 (ko) 2014-10-15 2021-04-23 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102372300B1 (ko) 2015-11-26 2022-03-08 삼성전자주식회사 스택 패키지 및 그 제조 방법
US10002857B2 (en) 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US10276536B2 (en) * 2017-04-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US10332862B2 (en) 2017-09-07 2019-06-25 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
KR101933425B1 (ko) 2017-11-30 2018-12-28 삼성전기 주식회사 반도체 패키지
KR102397905B1 (ko) * 2017-12-27 2022-05-13 삼성전자주식회사 인터포저 기판 및 반도체 패키지

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