CN114551369A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN114551369A
CN114551369A CN202011440595.4A CN202011440595A CN114551369A CN 114551369 A CN114551369 A CN 114551369A CN 202011440595 A CN202011440595 A CN 202011440595A CN 114551369 A CN114551369 A CN 114551369A
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electronic
electronic component
electronic element
carrier
package according
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许智勋
陈麒任
许习彰
许元鸿
戴瑞丰
江东昇
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Abstract

一种电子封装件及其制法，包括在一承载结构上于第一电子元件与第二电子元件之间配置有至少一防护结构，使形成于该承载结构上以包覆该防护结构并接触该第一与第二电子元件的填充材产生于该第一电子元件及第二电子元件的内部的应力得以减少，以避免该第一电子元件及第二电子元件发生破裂，提升该电子封装件的可靠度。

Description

电子封装件及其制法
技术领域
本发明有关一种电子封装件及其制法，尤指一种多芯片封装结构的电子封装件及其制法。
背景技术
随着科技的演进，电子产品需求趋势朝向异质整合迈进，为此，多芯片封装结构(MCM/MCP)逐渐兴起。
如图1所示的多芯片封装结构1，通过将多个半导体芯片11通过多个焊锡凸块13结合至一封装基板10上，再形成包覆该多个半导体芯片11的封装材料14。从而通过将多颗半导体芯片封装成单一芯片特性，使其具有较多的I/O数，且可以大幅增加处理器的运算能力，减少信号传递的延迟时间，以应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品。
然而，现有多芯片封装结构1于封装时，该封装材料14可能会形成于该半导体芯片11的角落处或非作用面11b的边缘，且该封装材料14相对杨氏系数(Young's modulus)大，使该半导体芯片11的内部应力增高，造成该半导体芯片11的应力集中，导致该封装材料14发生裂痕且延伸至该半导体芯片11而发生破裂，以致于该多芯片封装结构1的可靠度不佳。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其制法，以提高电子封装件的可靠度。
本发明的电子封装件包括：承载结构；第一电子元件与第二电子元件，其间隔设置于该承载结构上，以令该第一电子元件与该第二电子元件之间形成有一空间；防护结构，其设于该承载结构上且位于该第一电子元件与第二电子元件之间；以及填充材，其形成于该承载结构上并形成于该空间中且包覆该防护结构。
本发明还提供一种电子封装件的制法，包括：将第一电子元件及第二电子元件间隔设置于一具有防护结构的承载结构上，其中，该第一电子元件与该第二电子元件之间形成有一空间，且该防护结构位于该第一电子元件与第二电子元件之间；以及形成填充材于该承载结构上，以令该填充材包覆该防护结构，且令该填充材形成于该空间中。
前述的电子封装件及其制法中，该第一电子元件及第二电子元件电性连接该承载结构。
前述的电子封装件及其制法中，该防护结构为金属结构。
前述的电子封装件及其制法中，该防护结构为网状或挡块状。
前述的电子封装件及其制法中，该防护结构具有至少一外露该承载结构的镂空部。
前述的电子封装件及其制法中，该承载结构具有多个电性连接该第一电子元件及/或第二电子元件的电性接触垫，以令该电性接触垫相对于该承载结构表面的高度大于该防护结构相对于该承载结构表面的高度。
前述的电子封装件及其制法中，该承载结构定义有一置晶区及围绕该置晶区的外围区，以令该第一电子元件与第二电子元件位于该置晶区中，且该防护结构还配置于该外围区上。例如，该防护结构的布设区域的范围大于该第一电子元件垂直投影至该承载结构上的面积及/或该第二电子元件垂直投影至该承载结构上的面积。
前述的电子封装件及其制法中，还包括形成封装层于该承载结构上以包覆该第一电子元件与第二电子元件。例如，该第一电子元件及/或该第二电子元件外露于该封装层。
由上可知，本发明的电子封装件及其制法中，主要通过该承载结构于该第一电子元件与该第二电子元件之间配置有该防护结构，以分散应力分布，使该填充材产生于该第一电子元件及第二电子元件的内部的应力得以减少，故相比于现有技术，本发明可避免该第一电子元件及第二电子元件发生破裂，因而能提升该电子封装件的可靠度。
附图说明
图1为现有多芯片封装结构的剖视示意图。
图2A至图2D为本发明的电子封装件的制法的剖视示意图。
图2A’及图2A”为图2A的不同实施例的局部上视示意图。
图2C’及图2C”为图2C于覆晶回焊制程前的不同视野的局部放大剖视示意图。
图2D’为图2D的另一实施例的剖视示意图。
附图标记说明
1:多芯片封装结构
10:封装基板
11:半导体芯片
11b,21b,22b:非作用面
13:焊锡凸块
14:封装材料
2,2’:电子封装件
20:承载结构
200:电性接触垫
21:第一电子元件
21a,22a:作用面
21c,21c’,22c,22c’:侧面
210,220:电极垫
211,221:导电凸块
22:第二电子元件
23:填充材
24,24’:封装层
25,25’:防护结构
250:镂空部
A:置晶区
B:外围区
D:距离
h1,h2:高度
L:宽度
S:空间
t:高度差。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
请参阅图2A至图2D，为本发明的电子封装件2的制法的剖视示意图。
如图2A所示，提供一承载结构20，且于该承载结构20上配置至少一防护结构25,25’。
于本实施例中，该承载结构20为具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路构造。例如，该线路构造具有至少一介电层及形成于该介电层上的线路重布层(redistribution layer，简称RDL)，该线路重布层可采用铜材制作，且该介电层可采用如聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)、预浸材(Prepreg，简称PP)、封装胶体(molding compound)、感光型介电层或其它材质等以涂布方式形成的。然而，于其它实施例中，该承载结构20也可为半导体基板，其具有多个导电硅穿孔(Through-silicon via，简称TSV)，以作为硅中介板(Through Siliconinterposer，简称TSI)。应可理解地，该承载结构20也可为其它可供承载如芯片等电子元件的承载单元，例如导线架(lead frame)，并不限于上述。
此外，该承载结构20定义有一置晶区A及围绕该置晶区A的外围区B。例如，该置晶区A需布设有该线路重布层，且该线路重布层于该置晶区A表面形成有多个如微形垫(u-pad)态样的电性接触垫200，而该外围区B可依需求选择性配置或不配置电路。
另外，该防护结构25布设于该置晶区A中，且可依需求于该外围区B上配置该防护结构25’。例如，部分该防护结构25’可配置于该置晶区A的边缘内。换言之，该承载结构20除布设线路的区域以外皆可设置该防护结构25,25’，或者，仅于特定区域设置该防护结构25,25’。
另一方面，该防护结构25,25’为金属结构，其可为如图2A’所示的铜材网体(mesh)或如图2A”所示的多个间隔排设的铜材挡块(dam)状。
如图2B所示，于该承载结构20的置晶区A上间隔设置至少一第一电子元件21与至少一第二电子元件22，且于该第一电子元件21与该第二电子元件22之间形成(定义)有一空间S，以令该防护结构25位于该第一电子元件21与该第二电子元件22之间。
于本实施例中，该第一电子元件21为主动元件、被动元件、封装结构或其组合者，且该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。例如，该第一电子元件21为半导体芯片，其具有相对的作用面21a与非作用面21b，该作用面21a上具有多个电极垫210，并于该些电极垫210上形成导电凸块211，以令该第一电子元件21以覆晶方式通过该些导电凸块211结合及电性连接于该承载结构20的电性接触垫200上。
此外，该第二电子元件22为主动元件、被动元件、封装结构或其组合者，且该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。例如，该第二电子元件22为半导体芯片，其具有相对的作用面22a与非作用面22b，该作用面22a上具有多个电极垫220，并于该些电极垫220上形成导电凸块221，以令该第二电子元件22以覆晶方式通过该些导电凸块221结合及电性连接于该承载结构20的电性接触垫200上。应可理解地，该第一电子元件21与该第二电子元件22为相同类型的电子元件(即主动元件)，且两者的内部构造可相同或不相同。或者，该第一电子元件21与该第二电子元件22也可为不相同类型的电子元件。例如，该第一电子元件21为封装结构，且该第二电子元件22为主动元件。
另外，该防护结构25,25’可依需求布设于该第一电子元件21的作用面21a与该承载结构20之间及该第二电子元件22的作用面22a与该承载结构20之间。换言之，除了该承载结构20位于该空间S中设有该防护结构25以外，该第一或第二电子元件21,22与该承载结构20之间、及该承载结构20位于该外围区B也设有防护结构25’。
如图2C所示，形成填充材23于该承载结构20与该第一电子元件21之间及该承载结构20与该第二电子元件22之间，且令该填充材23包覆该些导电凸块211,221及防护结构25。
于本实施例中，该填充材23例如为底胶，其还形成于该第一电子元件21与该第二电子元件22之间的空间S中。具体地，该填充材23因毛细作用而延伸至该第一电子元件21对应该空间S的侧面21c与该第二电子元件22对应该空间S的侧面22c上。因此，该空间S的宽度L(即该第一电子元件21与该第二电子元件22之间的间距)愈小(或该间距越小)，该填充材23于该空间S中的毛细现象越明显。
此外，若该外围区B上配置有该防护结构25’，则该填充材23可包覆该外围区B的部分防护结构25’。
另外，如图2C’所示，该承载结构20的电性接触垫200相对于该承载结构20表面的高度h1大于该外围区B的防护结构25’相对于该承载结构20表面的高度h2，如高度差t为3微米(um)，以避免靠近该外围区B的多个导电凸块211,221于结合该电性接触垫200时接触该防护结构25’而发生短路(short)。应可理解地，该电性接触垫200相对于该承载结构20表面的高度h1也可大于对应位于该空间S处的防护结构25相对于该承载结构20表面的高度。
如图2D所示，形成一封装层24于该承载结构20上及该空间S中，以包覆该第一电子元件21与第二电子元件22。
于本实施例中，该封装层24可采用压合(lamination)或模压(molding)的方式填满该空间S。具体地，先将该封装层24覆盖该第一电子元件21的非作用面21b与该第二电子元件22的非作用面22b，并使该封装层24延伸填入于该空间S中，再以研磨或切割方式移除该封装层24的部分材质(可依需求移除该第一电子元件21的非作用面21b的部分材质与该第二电子元件22的非作用面22b的部分材质)，使该第一电子元件21的非作用面21b与该第二电子元件22的非作用面22b齐平该封装层24的上表面。
此外，该封装层24的杨氏系数小于该填充材23的杨氏系数。例如，该封装层24为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dry film)、环氧树脂(epoxy)、模封化合物(molding compound)、光阻材(photoresist)或防焊材(solder mask)。
于另一实施例中，如图2D’所示，该封装层24’也可覆盖该第一电子元件21的非作用面21b与该第二电子元件22的非作用面22b。
因此，本发明的制法通过该承载结构20于该第一电子元件21与该第二电子元件22之间配置有该防护结构25，以避免该填充材23因热膨胀系数(Coefficient of ThermalExpansion，简称CTE)不匹配而造成应力分布不均或应力集中的问题，例如，应力过大而产生的裂纹延伸至该承载结构20的线路重布层内的状况，故相比于现有技术，本发明能避免该电性接触垫200碎裂而导致该电子封装件2的终端产品电性失效。
此外，该防护结构25,25’具有至少一外露该承载结构20的镂空部250(如图2A’所示的网目或如图2A”所示的间隙)，以利于该填充材23接触结合该承载结构20，故可防止该防护结构25,25’与该承载结构20发生脱层。应可理解地，因该填充材23(底胶)与该承载结构20的介电层(如PI材)的结合力较佳，因而可避免该防护结构25,25’与该介电层(PI材)发生脱层。
另外，通过将该防护结构25’还布设于该外围区B，因而更可有效分散应力分布(通常应力最大处位在芯片角落处)，以避免应力集中于该置晶区A(如该第一电子元件21及/或该第二电子元件22)的角落处，故能防止该第一电子元件21及/或该第二电子元件22发生碎裂的问题。例如，该防护结构25’的布设区域与该第二电子元件22对应外围区B的侧面22c’(或该第一电子元件21对应外围区B的侧面21c’)相距的距离D至少25微米(um)，即D≧25微米。较佳地，该防护结构25,25’的布设区域的范围(其分布于该置晶区A与该外围区B)大于该第一电子元件21垂直投影至该承载结构20上的面积(如该作用面21a的面积，其仅分布于该置晶区A)及/或该第二电子元件22垂直投影至该承载结构20上的面积(如该作用面22a的面积，其仅分布于该置晶区A)。
本发明还提供一种电子封装件2,2’，包括：一承载结构20、第一电子元件21与第二电子元件22、防护结构25以及填充材23。
所述的第一电子元件21与第二电子元件22间隔设置于该承载结构20上，使该第一电子元件21与该第二电子元件22之间定义(形成)有一空间S。
所述的防护结构25设于该承载结构20上且位于该第一电子元件21与第二电子元件22之间。
所述的填充材23形成于该承载结构20上并形成于该空间S中且包覆该防护结构25。
于一实施例中，该第一电子元件21及第二电子元件22电性连接该承载结构20。
于一实施例中，该防护结构25为金属结构。
于一实施例中，该防护结构25为网状或挡块状。
于一实施例中，该防护结构25具有至少一外露该承载结构20的镂空部250。
于一实施例中，该承载结构20具有多个电性连接该第一电子元件21及/或第二电子元件22的电性接触垫200，以令该电性接触垫200相对于该承载结构20表面的高度h1大于该防护结构25,25’相对于该承载结构20表面的高度h2。
于一实施例中，该承载结构20定义有一置晶区A及围绕该置晶区A的外围区B，以令该第一电子元件21与第二电子元件22位于该置晶区A中，且该防护结构25’还配置于该外围区B上。例如，该防护结构25,25’的布设区域的范围大于该第一电子元件21垂直投影至该承载结构20上的面积及/或该第二电子元件22垂直投影至该承载结构20上的面积。
于一实施例中，所述的电子封装件2,2’还包括一形成于该承载结构20上以包覆该第一电子元件21与第二电子元件22的封装层24,24’。例如，该第一电子元件21及/或该第二电子元件22外露于该封装层24。
综上所述，本发明的电子封装件及其制法，通过该承载结构于该第一电子元件与该第二电子元件之间配置有该防护结构，以分散应力分布，使该填充材产生于该第一电子元件及第二电子元件的内部的应力得以减少，故本发明能避免该第一电子元件及第二电子元件发生破裂，因而能提升该电子封装件的可靠度。
上述实施例仅用以示例性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种电子封装件，其特征在于，包括：
承载结构；
第一电子元件与第二电子元件，其间隔设置于该承载结构上，以令该第一电子元件与该第二电子元件之间形成有一空间；
防护结构，其设于该承载结构上且位于该第一电子元件与第二电子元件之间；以及
填充材，其形成于该承载结构上并形成于该空间中且包覆该防护结构。
2.如权利要求1所述的电子封装件，其特征在于，该第一电子元件及第二电子元件电性连接该承载结构。
3.如权利要求1所述的电子封装件，其特征在于，该防护结构为金属结构。
4.如权利要求1所述的电子封装件，其特征在于，该防护结构为网状或挡块状。
5.如权利要求1所述的电子封装件，其特征在于，该防护结构具有至少一外露该承载结构的镂空部。
6.如权利要求1所述的电子封装件，其特征在于，该承载结构具有多个电性连接该第一电子元件及/或第二电子元件的电性接触垫，以令该电性接触垫相对于该承载结构的表面的高度大于该防护结构相对于该承载结构的表面的高度。
7.如权利要求1所述的电子封装件，其特征在于，该承载结构定义有一置晶区及围绕该置晶区的外围区，以令该第一电子元件与第二电子元件位于该置晶区中，且该防护结构还配置于该外围区上。
8.如权利要求7所述的电子封装件，其特征在于，该防护结构的布设区域的范围大于该第一电子元件垂直投影至该承载结构上的面积及/或该第二电子元件垂直投影至该承载结构上的面积。
9.如权利要求1所述的电子封装件，其特征在于，该电子封装件还包括形成于该承载结构上以包覆该第一电子元件与第二电子元件的封装层。
10.如权利要求9所述的电子封装件，其特征在于，该第一电子元件及/或该第二电子元件外露于该封装层。
11.一种电子封装件的制法，其特征在于，包括：
将第一电子元件及第二电子元件间隔设置于一具有防护结构的承载结构上，其中，该第一电子元件与该第二电子元件之间形成有一空间，且该防护结构位于该第一电子元件与第二电子元件之间；以及
形成填充材于该承载结构上，以令该填充材包覆该防护结构，且令该填充材形成于该空间中。
12.如权利要求11所述的电子封装件的制法，其特征在于，该第一电子元件及第二电子元件电性连接该承载结构。
13.如权利要求11所述的电子封装件的制法，其特征在于，该防护结构为金属结构。
14.如权利要求11所述的电子封装件的制法，其特征在于，该防护结构为网状或挡块状。
15.如权利要求11所述的电子封装件的制法，其特征在于，该防护结构具有至少一外露该承载结构的镂空部。
16.如权利要求11所述的电子封装件的制法，其特征在于，该承载结构具有多个电性连接该第一电子元件及/或第二电子元件的电性接触垫，以令该电性接触垫相对于该承载结构的表面的高度大于该防护结构相对于该承载结构的表面的高度。
17.如权利要求11所述的电子封装件的制法，其特征在于，该承载结构定义有一置晶区及围绕该置晶区的外围区，以令该第一电子元件与第二电子元件位于该置晶区中，且该防护结构还配置于该外围区上。
18.如权利要求17所述的电子封装件的制法，其特征在于，该防护结构的布设区域的范围大于该第一电子元件垂直投影至该承载结构上的面积及/或该第二电子元件垂直投影至该承载结构上的面积。
19.如权利要求11所述的电子封装件的制法，其特征在于，该制法还包括形成封装层于该承载结构上以包覆该第一电子元件与第二电子元件。
20.如权利要求19所述的电子封装件的制法，其特征在于，该第一电子元件及/或该第二电子元件外露于该封装层。
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