579555 A7 B7 五、發明説明（1 ) 發明領域 本發明有關半導體積體電路晶片包裝之領域’及特別有 關具有直接由該晶片至該包裝外蓋之熱傳導路徑之半導體 晶片包裝。 發明背景 裝 因半導體晶片之密度及功率規格穩定成長’能移去該晶 片所產生之熱量及將所產生之熱量傳送至該晶片包裝外側 之需求增加。現行晶片技術狀態中所產生之功率約50瓦， 而未來之需求預測約200瓦。由於穩定成長，現行包裝技術 傳送所產生之熱量、同時使局部區域過熱減至最小之能力 面臨挑戰。 於晶片包裝中，一目標是經由最簡單之包裝結構提供最 大之熱傳導。其簡單性係在結構及組裝二者。 在目前之技術狀態下’該半導體晶片包裝技術涉及相當 可觀之附加散熱結構，這增加其組裝之複雜性。 這包括一些例子。 線 吾人已使用一導熱液體，已將熱量由該積體電路晶片傳 導至該半導體包裝之外蓋。該導熱液體係包含於該晶片及 該外蓋間之一間隙中，及需要附加之結構以容納該液體及 保護該晶片。該技術之一例子係顯示在美國專利第 4,323,914 號中。 在組裝時，於該晶片及該外蓋之間使用熱機械式連接， 將經由熱連接構件之壓力而有永久之物理變形。該壓力在 該結構、特別是該晶片上之不利影響，及各機械接點之熱 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 579555 A7 __ B7 五、發明説明（2~~ " 變形阻抗係本技術之考量。一例子係顯示在美國專利第 5,786,635號中。 使用一定位及支撐諸如焊接劑之可熔解腳柱之聚合物薄 膜型結構元件，其定位在該晶片及該外蓋之間，而在組裝 之後保持位於適當位置。在組裝之後保留在該外蓋下方之 結構元件之存在係本技術之一項考量。一例子係顯示在 1991年 12月之研九公開（Research Disclosure)’’ 第 332號中。 使用一結合形狀之金屬外蓋可提供該熱傳導路徑中之壓 縮及氣冷之能力。一例子係顯示在1991年1月之，，研究公開 (Research Disclosure)’’第 321號中。 於該技藝中需要一無壓力之晶片包裝技術，其由該晶片 傳熱至该外蓋及周圍時具有低熱阻抗。 發明概要 本發明提供一種晶片包裝結構之原理，其中製成一由該 晶片之表面至一外蓋之直接熔合黏著熱傳導路徑。在該晶 片表面上之熱傳導路徑位置設有一熔合構件。該外蓋上之 熱傳導路彳至位置已附著至一低熱阻抗連接部份中，一高導 熱率路徑構件之外蓋接觸端設有一段長度，以致當該外蓋 位於該晶片上方之適當位置時，該高導熱率路徑構件之晶 片接觸端係與該晶片表面上之晶片接觸熔合構件接觸。然 後運作一低溫偏移及滞留，以熔合該熔合構件及所提供之 高導熱率構件之晶片接觸端，藉此由該晶片背面至該外蓋 形成有一低熱阻抗。如想要時可澱積盡量多之熱傳導路徑 溶合構件。該高導熱率構件可為諸如支柱或球之合適形狀 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 579555 A7 ______B7 五、發明説明~^ ，及以有利之傳導率選擇之。選擇該熔合構件之材料，以 在低溫具有良好之接合特性。藉著定位該熱傳導路徑及於 該晶片及孩外蓋之間使用一平衡應力構件，可減輕由於該 晶片中生熱所導致之應力。 圖面簡述 第1圖係本發明之一部份半導體晶片包裝之剖視圖，而在 該晶片之一表面及該外蓋之間設有熱傳導路徑。 第2圖係本發明之一部份半導體晶片包裝之透視圖，而在 該晶片之一表面及該外蓋之間設有熱傳導路徑。 第3圖係澱積在半導體晶片表面上之熔合構件襯墊之示範 架構圖’其架構對應於該晶片内之生熱位置。 第4圖係使用一層金屬球當作熱傳導路徑之半導體包裝之 剖視圖。 第5圖係該金屬球至第4圖包裝之晶片界面之放大剖視圖。 弟6圖係一熱傳導路徑至第4圖包裝之晶片界面之放大剖 視圖，其中支柱係用作熱傳導路徑。 第7圖係本發明包裝之一實施例，其中該熱傳導路徑在一 引線接合列陣區域内側接合該晶片。 第8圖係具有與該包裝外蓋一體成形之金屬腳柱之半導體 包裝實施例，該金屬腳柱具有熱傳導路徑構件之作用。 第9圖係本發明之半導體包裝之剖視圖，其中使用具有插 入件之二層金屬球以減少機械應力。 第10圖係第9圖熱傳界面之放大視圖’其使用以插入件分 開之二層金屬球。 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 579555 A7579555 A7 B7 V. Description of the Invention (1) Field of the Invention The present invention relates to the field of semiconductor integrated circuit chip packaging 'and particularly to a semiconductor chip package having a heat conduction path directly from the chip to the outer cover of the package. BACKGROUND OF THE INVENTION The need for a semiconductor wafer to grow steadily due to its density and power specifications can remove the heat generated by the wafer and transfer the generated heat to the outside of the wafer package. The power generated in the current state of the wafer technology is about 50 watts, and future demand is estimated at about 200 watts. Due to steady growth, the ability of current packaging technologies to transfer the heat generated while minimizing local overheating is challenging. In wafer packaging, one goal is to provide maximum heat transfer through the simplest packaging structure. Its simplicity lies in both structure and assembly. In the current state of technology, the semiconductor wafer packaging technology involves considerable additional heat dissipation structures, which increases the complexity of its assembly. This includes some examples. We have used a thermally conductive liquid to conduct heat from the integrated circuit chip to the cover of the semiconductor package. The thermal fluid system is contained in a gap between the wafer and the outer cover, and additional structures are needed to contain the liquid and protect the wafer. An example of this technique is shown in US Patent No. 4,323,914. During assembly, a thermo-mechanical connection is used between the chip and the outer cover, and there will be permanent physical deformation through the pressure of the thermal connection member. The adverse effects of the pressure on the structure, especially on the wafer, and the heat of the mechanical contacts -4- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 579555 A7 __ B7 V. Description of the Invention (2 ~~ " Deformation impedance is a consideration of this technology. An example is shown in US Patent No. 5,786,635. A polymer film-type structural element that positions and supports a fusible foot such as solder, which Positioned between the wafer and the cover, and kept in place after assembly. The presence of structural elements that remain under the cover after assembly is a consideration of this technology. An example is shown in December 1991 "Research Disclosure" No. 332. The use of a combined shape metal cover can provide compression and air cooling capabilities in the heat conduction path. An example is shown in January 1991, "Research Disclosure" No. 321. In this technique, a pressure-free wafer packaging technology is required, which has low thermal resistance when transferring heat from the wafer to the cover and the surroundings. SUMMARY OF THE INVENTION The present invention provides a principle of a wafer packaging structure, in which a direct fusion bonding heat conduction path is formed from the surface of the wafer to an outer cover. A fusion member is provided at the position of the heat conduction path on the surface of the wafer. The thermal conduction path of the high-thermal-conductivity path member has been attached to a low-thermal-resistance connection portion, and the contact end of the outer cover of the high-thermal-conductivity path member is provided with a length such that when the outer cover is located in a proper position above the chip, the high thermal conductivity The wafer contact end of the rate path member is in contact with the wafer contact fusion member on the surface of the wafer. Then, a low temperature offset and stagnation is operated to fuse the fusion contact member and the wafer contact end of the provided high thermal conductivity member, thereby A low thermal resistance is formed from the back of the wafer to the outer cover. If desired, as many heat-conducting path fusion members as possible can be deposited. The high-thermal-conductivity member can be a suitable shape such as a pillar or a ball. -5- This paper size is suitable for China National Standard (CNS) A4 specification (210 X 297 mm) 579555 A7 ______B7 V. Description of the invention ~ ^ and selection with favorable conductivity .Select the material of the fused member to have good bonding properties at low temperature. By positioning the heat conduction path and using a balanced stress member between the wafer and the outer cover, it can alleviate the heat caused by the wafer Brief Description of Drawings Figure 1 is a cross-sectional view of a part of a semiconductor wafer package according to the present invention, and a heat conduction path is provided between a surface of the wafer and the cover. Figure 2 is a part of the present invention A perspective view of a semiconductor wafer package with a heat conduction path between one surface of the wafer and the cover. Figure 3 is an exemplary architecture diagram of a fused member pad deposited on the surface of a semiconductor wafer. Its architecture corresponds to The location of heat generation within the wafer. Figure 4 is a cross-sectional view of a semiconductor package using a layer of metal balls as a heat conduction path. Figure 5 is an enlarged cross-sectional view of the wafer interface from the metal ball to the package of Figure 4. Figure 6 is an enlarged cross-sectional view of the heat conduction path to the wafer interface of the package in Figure 4, where the pillars are used as heat conduction paths. Fig. 7 is an embodiment of the package of the present invention, wherein the heat conduction path bonds the wafer inside a wire bonding array region. Fig. 8 is an embodiment of a semiconductor package having a metal leg integrated with the outer cover of the package, the metal leg having the function of a heat conduction path member. Fig. 9 is a cross-sectional view of a semiconductor package of the present invention in which a two-layer metal ball having an insert is used to reduce mechanical stress. Fig. 10 is an enlarged view of the heat transfer interface of Fig. 9 ', which uses two layers of metal balls separated by an insert. -6-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 579555 A7
發明之敘述 於積體電路晶片包裝中，該晶片不時增加其電路系統密 f ’即使個別裝置之尺寸及功率消&量小，整體功率消耗 量抵達相當大瓦特數，且該晶片之不同區域所產生之熱量 =同。於本發明中，提供一種晶片包裝結構之原理，其中 氣成一由該晶片背後表面至該晶片上方外蓋之直接熱傳導 路徑，以對在熱點之額外熱傳導路徑提供高熱傳導能力， 俾说控制其應力。 大致關於第1，2及3圖敘述本發明，其中第丨及2圖分別係 本發明所提供之一部分已覆蓋倒裝晶片之剖視圖及透視圖 ，且第3圖說明該晶片背面上之熱傳導路徑位置之配置範 例〇 參考第1及2圖，其為本發明之第一範例，並顯示應用於 孩倒裝晶片型技術，其中該晶片丨在其前表面3上具有電連 接球接觸構件2 ,並使該球接觸構件2支撐其上方之晶片}及 與基材5之上表面4分開，而依序具有電連接及支撐腳柱6。 未π出之電導體係藉著基材5及該球接觸構件2與腳柱6間之 電互連部份支撐。一外蓋7係定位在該晶片1及基材5組件上 方及以表面4密封在交又線。本發明涉及由該晶片丨之表面 (於本圖面中即指該後側表面9)指向該外蓋7提供一低熱阻抗 路徑8，並對該後側表面9提供一熔合熱連接，及為該晶片1 之熱點控制提供特製路徑8a及8b。該低熱阻抗路徑8在該後 側表面9上具有一熔合墊10，其具有與該低熱阻抗路徑之其 餘部份形成一熔合界面之作用。由該外蓋7底側沿著路徑8 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱） 裝 訂 線 579555 A7 B7 五、發明説明（5 ) 至該熔合墊1 0之距離係一段高導熱率構件11所組成，而取 代第1及2圖中之8，8a及8b。該高導熱率構件11之第一端點 12以一低熱阻抗連接部份附著至該外蓋7底側。 該高導熱率構件之長度係使得該外蓋7定位在該晶片1上 方位置時，讓該高導熱率構件11之晶片接觸端13與該晶片 後側表面9上之晶片接觸熔合墊1 〇接觸。然後運作一低溫偏 移及滞留，以熔合該熔合墊1 〇至該高導熱率構件11之晶片 接觸端13與該晶片後側表面9二者，藉此直接由該晶片1背 面9至該外蓋7提供一低熱阻抗。如想要時可在該晶片1之背 面9上澱積盡量多之熱傳導路徑熔合墊。該高導熱率構件n 可為諸如支柱或球之合適形狀，及以有利之傳導率選擇之 。選擇該熔合墊之材料，以在該晶片之操作溫度下具有良 好之接合特性。藉著定位該熱傳導路徑可減輕由於該晶片 中生;所導致之應力。將明顯的是提供由晶片上熱點至該 外盍及因此至周遭環境之熱傳導路徑的原理，可如第3圖中 所示於一較大及較小熔合墊10之配置之間，在該晶片之背面 (該晶片1之背面9)上藉著使用不同尺寸及密度之溶合塾完成。 將明顯的是該熔合墊可澱積在任何及盡量多之位置，只要其 為該晶片之電子工程所預期產生熱點處。該熔合塾1〇不須呈 格子圖樣，且其尺寸可改變以配合該半導體晶片丨之局部熱傳 需求。其可包括數層金屬，以增強濕潤及阻礙擴散作用。使 用二層··熔合至該半導體晶片1表面9之第一層可能是諸如鈦或 鉻之黏著促進劑，第二層可能是諸如鈀或鎳之普通金屬，且最 外層之第三層可能是黃金。The description of the invention is in the package of integrated circuit wafers, which from time to time increase the density of its circuit system. Even if the size and power consumption of individual devices are small, the overall power consumption reaches a considerable wattage, and the chip is different. Area of heat generated = the same. In the present invention, a principle of a wafer packaging structure is provided, in which a direct heat conduction path is formed from the back surface of the wafer to an outer cover above the wafer, so as to provide a high heat conduction capacity for an extra heat conduction path at a hot spot, let alone control its stress . The invention is described generally with respect to Figures 1, 2 and 3, wherein Figures 丨 and 2 are respectively a cross-sectional view and a perspective view of a part of a flip chip covered by the invention, and Figure 3 illustrates the heat conduction path on the back of the wafer An example of the position configuration. 0. Referring to FIGS. 1 and 2, this is a first example of the present invention, and is shown to be applied to a flip-chip type technology, in which the wafer has an electrical connection ball contact member 2 on its front surface 3, The ball contact member 2 supports the wafer above it} and is separated from the upper surface 4 of the base material 5, and sequentially has electrical connections and support legs 6. The unconducted conductivity system is supported by the substrate 5 and the electrical interconnection between the ball contact member 2 and the leg 6. An outer cover 7 is positioned above the wafer 1 and the substrate 5 components and sealed to the intersection line with a surface 4. The invention relates to providing a low thermal resistance path 8 from the surface of the wafer (referred to as the rear surface 9 in the figure) to the outer cover 7, and providing a fusion thermal connection to the rear surface 9, and for The hot spot control of the chip 1 provides special paths 8a and 8b. The low-thermal-resistance path 8 has a fusion pad 10 on the rear surface 9 and has the function of forming a fusion interface with the rest of the low-heat-resistance path. From the bottom side of the outer cover 7 along the path 8 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) binding line 579555 A7 B7 5. Description of the invention (5) to the fusion pad 10 It is composed of a section of high thermal conductivity member 11 instead of 8, 8a and 8b in Figs. The first end point 12 of the high thermal conductivity member 11 is attached to the bottom side of the outer cover 7 with a low thermal resistance connection portion. The length of the high thermal conductivity member is such that when the outer cover 7 is positioned above the wafer 1, the wafer contact end 13 of the high thermal conductivity member 11 is brought into contact with the wafer contact fusion pad 10 on the rear surface 9 of the wafer. . Then, a low temperature shift and retention are performed to fuse the fusion pad 10 to the wafer contact end 13 of the high thermal conductivity member 11 and the wafer rear side surface 9, thereby directly passing from the back surface 9 of the wafer 1 to the outside. The cover 7 provides a low thermal impedance. If desired, as many thermal conductive path fusion pads as possible can be deposited on the backside 9 of the wafer 1. The high thermal conductivity member n may be a suitable shape such as a pillar or a ball, and is selected with favorable conductivity. The material of the fusion pad is selected to have good bonding characteristics at the operating temperature of the wafer. By locating the heat conduction path, the stress caused by the wafer's mesogen can be reduced. It will be apparent that the principle of providing a heat conduction path from the hot spot on the wafer to the outer periphery and thus to the surrounding environment can be shown in Figure 3 between the configuration of a larger and smaller fusion pad 10 between the wafer The back surface (the back surface 9 of the wafer 1) is completed by using fused resins of different sizes and densities. It will be apparent that the fusion pad can be deposited in any and as many locations as long as it is a hot spot expected for the electronic engineering of the wafer. The fusion splice 10 need not be in a grid pattern, and its size can be changed to meet the local heat transfer requirements of the semiconductor wafer. It can include several layers of metal to enhance wetting and hinder diffusion. Using two layers ... The first layer fused to the surface 9 of the semiconductor wafer 1 may be an adhesion promoter such as titanium or chromium, the second layer may be an ordinary metal such as palladium or nickel, and the third layer at the outermost layer may be gold.
579555 A7579555 A7
第4至6圖說明倒裝晶片技術之第一範例，其中該高導熱 率構件為滾球及支柱。於該圖面中，該熱傳導路徑構件係 顯不為實線，而該電連接部份為影線。 參考第4圖，其顯示一包裝之剖視圖，並使用一層金屬球 當作先前圖面之高導熱率構件丨丨。該半導體晶片η1使用焊 球113以倒裝晶片式接合在一基材112上。該基材112之外側 連接構件係另一組焊球118。該包裝之金屬外蓋115係軟焊 、銅焊、或膠黏至該基材112上。一層金屬球121軟焊或銅 知至該金屬外蓋115之内表面上，及軟焊至該半導體晶片 111身面而對應於先前圖面中之溶合塾13之金屬塾131上。 於孫外蓋115係由塑膠製成之結構中，一列陣金屬球121係 坎入該塑膠外蓋内側及軟焊至該晶片u丨上之墊丨3 1，如同 該金屬外蓋。 第4圖金屬—球界面之詳細結構係顯示於第5圖中。由金 屬或高溶點焊接合金製成之金屬球121係首先藉著軟焊或銅 焊接合至該外蓋115之内側表面。然後將一低熔點焊接合金 層125放在該金屬球121上方。在該半導體晶片1^之背面上 ，該金屬墊13 1係覆蓋著另一低溫熔點焊接合金丨26，諸如 錯/錫合金、錫/銦合金、銦或等價物。於組裝操作期間，本 有該晶片之包裝將加熱至該烊接材料層125及126之溶點。 該層125，126及131之熔化將使該金屬球121溶合至該半導 體晶片111，藉此形成先前圖面之路徑11。那些層125及126 將補償該晶片表面及該金屬球間由於表面粗輪度及平面性 所造成之任何不規則間隙。假如該金屬球全然由低溶點焊 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) ' ------- 579555 A7 B7 五、發明説明 接合金製成，則可進一步補償該間隙。於此情況中，可略 去該焊接層125或甚至該二層125及126。該層金屬球121提 供一對該半導體晶片U1所需之應力消除，此應力係該半導 體晶片111及該外蓋115間之熱膨脹不協調所造成。 參考第6圖，其顯示先前圖面之路徑丨丨係使用支柱。使用 支柱之一主要優點是提供額外之應力消除，其中可修改該 腳柱之長度以減少對該晶片之機械應力。於第6圖中，由諸 如具有相對較南熔點之銅或焊接合金之熱傳導材料製成之 金屬腳柱221，係經由一層具較低熔點之焊接合金225焊接 至孩包裝215之金屬外蓋内表面。該半導體晶片211之背面 具有一列陣金屬墊23 1，並以一層低熔點焊接合金226覆蓋 該金屬墊。於組裝操作期間，該包裝將加熱至該焊接合金 226之熔點，其將與該支柱221熔合，以由該晶片2ιι至該包 裝215之外蓋提供一更有效之熱傳導路徑。由於結構變化， 該支柱221可與該外蓋215結合成單件式銅或銅鎢合金，或 該支柱221可由一陣列來自該外蓋215之突出部份製成。 除了用作第丨至6圖第一範例之”倒裝晶片”型技術外，本發 明亦可使用其他技術，諸如有關第7圖中所示之引線接合法 及第8圖中所示穿過該外蓋之金屬腳柱。 參考第7圖，其顯示一球格列陣包裝外殼之剖視圖，其中 一半導體晶片310係放入一基材312之中心凹孔3ιι ,及藉著 該技藝中早已習知之引線接合技術連接至該基材312表面上 之禾不出W線。由該基材312至外側之連接係經由一列陣之 焊球川。-金屬外蓋315係軟烊、銅焊、或膠黏至該基材 -10- 579555 A7 ______B7 五、發明説明（8 ) 。一列陣金屬球321軟焊至該外蓋315之内表面及該半導體 晶片310有源側333上之金屬墊331。一層電絕緣但熱傳導之 薄膜3 3 2係放入該金屬塾3 3 1及該晶片之有源側3 3 3間，以防 止短路。 參考第8圖，其顯示一球格列陣包裝之剖視圖，並使用整 合一列陣金屬腳柱之金屬外蓋，該腳柱延伸穿過及整合該 外蓋。半導體晶片411係使用焊球413以倒裝晶片式接合至 一基材412，及藉著該基材412另一側面上之焊球418提供外 側之連接。一金屬外蓋415係軟焊、銅焊、或膠黏至該基材 412上，以保護該半導體晶片411。一列陣金屬腳柱421衝孔 穿過該金屬外蓋415，而藉著衝孔穿過該外蓋415之變形保 持緊抓每一腳柱，以致每一金屬腳柱之一端由該外蓋415之 外側突出。在該半導體晶片411背面上之腳柱位置大致與先 前圖面中所用型式之金屬墊對齊。一低熔點之焊接合金層 426蓋住該金屬墊而與該金屬腳柱接觸。於包裝組合期間， 該包裝將加熱至該焊接合金之溶點，且該外蓋415下壓直至 該金屬腳柱421插入該熔化之焊接合金426。該金屬腳柱421 可經由焊接合金426與該晶片411熱接觸，及未將不必要之 機械應力加至該晶片411。該金屬腳柱可藉著模鑄或燒結法 製成該金屬外蓋之一部分而形成一單件。該金屬腳柱亦可 由異於該外蓋之材料所製成，例如該腳柱由銅製成，而該 外蓋由銅/鎢合金製成。 於所討論之所有包裝技術中，藉著改變該熱傳導路徑之 直徑、長度及材料可進一步減少對該晶片之機械應力。 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 579555 A7 B7 五、發明説明（ 在二層金屬球之間有一插入件即可達成在該晶片上又進 步減少機械應力。此一結構係顯示於第9圖中，而在第1 〇 圖顯示該插入件界面之一放大細節。 參考第9圖，其顯示該技藝中早已習知且非本發明之一部 分之典型栓格列陣包裝。其在此用作一說明該晶片及該包 裝外蓋間有一層金屬球結構之範例。在此所述概念可應用 至具有一或多數晶片之任何其他半導體晶片包裝。該半導 體晶片5 11使用一工業上常見之列陣焊球5丨3以倒裝晶片式 接合至一基材512。該基材512之外表面具有一列陣之連接 栓銷5 14。一金屬外蓋5 15係軟焊、銅焊、或膠黏至該基材 512上。該二層金屬球516及517係接合至一插入件518。 該界面之詳細結構係顯示於第1 〇圖中。參考第1 〇圖，該 插入件518包括一層核心材料519，在其二表面覆蓋以材料 層520及521薄片。有充滿熱傳導材料之通孔522將該外層 520及521連接在一起。該通孔522係與金屬球516及517對齊 。較佳之層520及521與通孔522之材料為銅。該通孔522延 伸穿過之核心層523材料為不變鋼、鉬、或熱膨脹係數在該 半導體晶片及包裝外蓋515間之其他材料。該金屬球516及 517可為與該半導體晶片511及包裝外蓋515之材料相容之任 何型式熱傳導材料。例如，其可為銅、鉛/錫合金、錫/銦合 金或銦。假如使用銅，將加入另一層低熔點焊接合金，以 將該金屬球熔合至該外蓋515之内表面及該半導體晶片511 上表面525上之金屬墊524。假如低熔點焊接合金係用作金 屬球，該金屬球可直接軟焊至該外蓋515之内表面及該半導 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂 579555 A7 _____ B7 五、發明説明（1Q ) ~ ' 體晶片511上之金屬墊。分別在該金屬層52〇及521上之選用 遮罩層527及528係可用以個別分開該金屬球516及517 ,其 樣式類似於有關第3圖所討論之樣式。 已欽述者是一種半導體積體晶片之包裝原理，其中直接 由該晶片表面上之一位置至該外蓋及因而至周圍提供一低 熱阻抗路徑。 主要元件符號表 1 晶片 312 基材 2 電連接球接觸構件 315 金屬外蓋 3 前表面 318 焊球 4 上表面 321 金屬球 5 基材 331 金屬塾 6 支撐腳柱 332 電絕緣但熱傳導之薄膜 7 外蓋 333 源側 8 低熱阻抗路徑 411 半導體晶片 8a 特製路徑 412 基材 8b 特製路徑 413 焊球 9 後側表面 415 金屬外蓋 10 溶合塾 418 焊球 11 高導熱率構件 421 金屬腳柱 12 第一端點 426 低熔點之焊接合金層 13 晶片接觸端 511 半導體晶片 111 半導體晶片 512 基材 112 基材 513 焊球 113 焊球 514 連接栓銷 -13-Figures 4 to 6 illustrate a first example of flip chip technology, where the high thermal conductivity member is a ball and a post. In the drawing, the heat conduction path member is not shown as a solid line, and the electrical connection part is a hatched line. Refer to Figure 4, which shows a cross-sectional view of a package and uses a layer of metal balls as the high thermal conductivity member of the previous drawing. This semiconductor wafer? 1 is bonded to a substrate 112 in a flip-chip manner using solder balls 113. The outer-side connecting member of the base material 112 is another set of solder balls 118. The metal outer cover 115 of the package is soldered, brazed, or glued to the substrate 112. A layer of metal balls 121 is soldered or brazed to the inner surface of the metal outer cover 115 and soldered to the body of the semiconductor wafer 111 to correspond to the metal 131 of the fused 13 in the previous drawing. In the structure in which the sun outer cover 115 is made of plastic, an array of metal balls 121 is bumped into the inside of the plastic outer cover and soldered to a pad 丨 3 1 on the chip u 丨 like the metal outer cover. Figure 4 shows the detailed structure of the metal-ball interface in Figure 5. A metal ball 121 made of a metal or a high melting point welding alloy is first bonded to the inner surface of the outer cover 115 by soldering or brazing. A low melting point solder alloy layer 125 is then placed over the metal ball 121. On the back of the semiconductor wafer 1 ^, the metal pad 13 1 is covered with another low-temperature-melting-point soldering alloy 26, such as a w / tin alloy, a tin / indium alloy, indium, or an equivalent. During the assembly operation, the package containing the wafer will be heated to the melting point of the bonding material layers 125 and 126. The melting of the layers 125, 126, and 131 will fuse the metal ball 121 to the semiconductor wafer 111, thereby forming the path 11 of the previous drawing. Those layers 125 and 126 will compensate for any irregular gaps between the surface of the wafer and the metal ball due to the surface roughness and flatness. If the metal ball is made entirely of low-solubility spot-welded paper, the Chinese national standard (CNS) A4 specification (210 X 297 mm) is used. ------- 579555 A7 B7 V. Invention description Bonding gold, then This gap can be further compensated. In this case, the solder layer 125 or even the two layers 125 and 126 may be omitted. The layer of metal balls 121 provides the stress relief required for the pair of semiconductor wafers U1, which is caused by the uncoordinated thermal expansion between the semiconductor wafer 111 and the outer cover 115. Reference is made to Fig. 6, which shows that the path of the previous drawing uses pillars. One of the main advantages of using a post is to provide additional stress relief, where the length of the post can be modified to reduce mechanical stress on the wafer. In Figure 6, a metal foot 221 made of a thermally conductive material, such as copper or a solder alloy with a relatively south melting point, is welded to the metal outer cover of the child package 215 through a layer of solder alloy 225 having a lower melting point. surface. The semiconductor wafer 211 has an array of metal pads 23 1 on its back surface, and the metal pads are covered with a layer of low melting solder alloy 226. During the assembly operation, the package will be heated to the melting point of the solder alloy 226, which will fuse with the pillar 221 to provide a more efficient heat conduction path from the wafer 2m to the outer cover of the package 215. Due to the structural change, the pillar 221 may be combined with the outer cover 215 into a single piece of copper or copper tungsten alloy, or the pillar 221 may be made of an array of protruding portions from the outer cover 215. In addition to the "flip-chip" technology used as the first example in Figures 1-6, the present invention can also use other technologies, such as the wire bonding method shown in Figure 7 and the pass-through shown in Figure 8 The metal feet of the cover. Referring to FIG. 7, it shows a cross-sectional view of a ball grid package housing, in which a semiconductor wafer 310 is placed in a central recess 3m of a substrate 312, and is connected to the wire bonding technology by wire bonding technology already known in the art. There is no W line on the surface of the substrate 312. The connection from the substrate 312 to the outside is via an array of solder balls. -The metal outer cover 315 is soft palate, brazed, or glued to the substrate -10- 579555 A7 ______B7 5. Description of the invention (8). An array of metal balls 321 is soldered to the inner surface of the outer cover 315 and the metal pad 331 on the active side 333 of the semiconductor wafer 310. An electrically insulating but thermally conductive film 3 3 2 is placed between the metal 塾 3 3 1 and the active side 3 3 3 of the wafer to prevent a short circuit. Reference is made to Fig. 8, which shows a cross-sectional view of a ball grid array package and uses a metal outer cover that integrates an array of metal posts that extend through and integrate the outer cover. The semiconductor wafer 411 is flip-chip bonded to a substrate 412 using solder balls 413, and external connections are provided by solder balls 418 on the other side of the substrate 412. A metal cover 415 is soldered, brazed, or glued to the substrate 412 to protect the semiconductor wafer 411. An array of metal posts 421 is punched through the metal outer cover 415, and each leg is held tightly by the deformation of the punched hole through the outer cover 415, so that one end of each metal foot is covered by the outer cover 415 Outer side protrudes. The positions of the pins on the back surface of the semiconductor wafer 411 are substantially aligned with the type of metal pad used in the previous figure. A low melting point solder alloy layer 426 covers the metal pad and contacts the metal leg. During the packaging assembly, the package is heated to the melting point of the welding alloy, and the outer cover 415 is pressed down until the metal leg 421 is inserted into the molten welding alloy 426. The metal pin 421 can be in thermal contact with the wafer 411 via a solder alloy 426, and unnecessary mechanical stress is not applied to the wafer 411. The metal leg can be formed as a single piece by molding or sintering a part of the metal cover. The metal foot post may also be made of a material different from the outer cover, for example, the foot post is made of copper, and the outer cover is made of copper / tungsten alloy. In all of the packaging technologies discussed, the mechanical stress on the wafer can be further reduced by changing the diameter, length, and material of the heat conduction path. -11-This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 579555 A7 B7 5. Description of the invention (with an insert between the two layers of metal balls to achieve further progress on the wafer Mechanical stress. This structure is shown in Fig. 9, and an enlarged detail of the insert interface is shown in Fig. 10. Reference is made to Fig. 9, which shows the technique already known and not part of the present invention. A typical peg-array package. It is used here as an example to illustrate the structure of a layer of metal balls between the wafer and the package cover. The concepts described herein can be applied to any other semiconductor wafer package with one or more wafers. The semiconductor wafer 5 11 is flip-chip bonded to a substrate 512 using an array of solder balls 5 丨 3 commonly used in the industry. The substrate 512 has an array of connecting pins 5 14 on its outer surface. A metal outer The cover 5 15 is soldered, brazed, or glued to the substrate 512. The two-layer metal balls 516 and 517 are joined to an insert 518. The detailed structure of the interface is shown in Figure 10. Referring to FIG. 10, the insert 518 includes A layer of core material 519 is covered on its two surfaces with material layers 520 and 521. There are through holes 522 filled with thermally conductive material to connect the outer layers 520 and 521 together. The through holes 522 are aligned with the metal balls 516 and 517. The material of the good layers 520 and 521 and the through hole 522 is copper. The material of the core layer 523 through which the through hole 522 extends is constant steel, molybdenum, or other materials with a thermal expansion coefficient between the semiconductor wafer and the package cover 515. The metal balls 516 and 517 may be any type of thermally conductive material compatible with the materials of the semiconductor wafer 511 and the packaging cover 515. For example, they may be copper, lead / tin alloy, tin / indium alloy, or indium. If copper is used , Another layer of low melting solder alloy will be added to fuse the metal ball to the inner surface of the outer cover 515 and the metal pad 524 on the upper surface 525 of the semiconductor wafer 511. If the low melting solder alloy is used as a metal ball, the The metal ball can be soldered directly to the inner surface of the outer cover 515 and the semiconducting -12- This paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) binding 579555 A7 _____ B7 V. Description of the invention ( 1Q) ~ 'Body The metal pads on the sheet 511. The optional masking layers 527 and 528 on the metal layers 52 and 521, respectively, can be used to separate the metal balls 516 and 517, respectively, in a style similar to that discussed in relation to FIG. What has been described is a packaging principle of a semiconductor integrated chip, in which a low thermal resistance path is provided directly from a position on the surface of the wafer to the cover and thus to the surroundings. Symbols of main components 1 Wafer 312 Substrate 2 Electrical connection Ball contact member 315 Metal cover 3 Front surface 318 Solder ball 4 Upper surface 321 Metal ball 5 Substrate 331 Metal 塾 6 Supporting post 332 Electrically insulating but thermally conductive film 7 Cover 333 Source side 8 Low thermal impedance path 411 Semiconductor wafer 8a Special path 412 Substrate 8b Special path 413 Solder ball 9 Rear side surface 415 Metal cover 10 Fusion 塾 418 solder ball 11 High thermal conductivity member 421 Metal pin 12 First endpoint 426 Low melting point solder alloy layer 13 Wafer contact End 511 Semiconductor wafer 111 Semiconductor wafer 512 Substrate 112 Substrate 513 Solder ball 113 Solder ball 514 Connection pin-13-
579555 A7 B7 五、發明説明（11 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 115 金屬外蓋 515 金屬外蓋 118 焊球 516 金屬球 121 金屬球 517 金屬球 125 低熔點焊接合金層 518 插入件 126 低溫熔點焊接合金 519 核心材料 131 金屬墊 520 材料層 211 半導體晶片 521 材料層 215 包裝 522 通孔 221 金屬聊柱 523 核心層 225 低熔點之焊接合金 524 金屬墊 226 低熔點焊接合金 525 上表面 231 金屬墊 527 遮罩層 310 半導體晶片 528 遮罩層 311 中心凹孔579555 A7 B7 V. Description of the invention (11 This paper size applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) 115 Metal cover 515 Metal cover 118 Solder ball 516 Metal ball 121 Metal ball 517 Metal ball 125 Low melting point Welding alloy layer 518 Insert 126 Low melting point welding alloy 519 Core material 131 Metal pad 520 Material layer 211 Semiconductor wafer 521 Material layer 215 Packaging 522 Through hole 221 Metal chat post 523 Core layer 225 Low melting point solder alloy 524 Metal pad 226 Low melting point Solder alloy 525 upper surface 231 metal pad 527 mask layer 310 semiconductor wafer 528 mask layer 311 center recess