CN1165079C - Chip package with high effective heat transferring structure - Google Patents
Chip package with high effective heat transferring structure Download PDFInfo
- Publication number
- CN1165079C CN1165079C CNB011048999A CN01104899A CN1165079C CN 1165079 C CN1165079 C CN 1165079C CN B011048999 A CNB011048999 A CN B011048999A CN 01104899 A CN01104899 A CN 01104899A CN 1165079 C CN1165079 C CN 1165079C
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- chip
- integrated circuit
- encapsulation
- melting
- shell
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- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
A chip packaging structural principle is provided wherein a direct fused attachment thermal path from the surface of the chip to a cover is constructed. The thermal path location on the cover has attached thereto in a low thermal impedance connection, the cover contacting end of a high thermal conductivity path member with a length such that when the cover is in position over the chip, the chip contacting end of the high thermal conductivity member is in contact with the chip contact fusion member on the surface of the chip. As many fusion members for thermal paths as desired may be deposited. The high thermal conductivity members can be a convenient shape such as posts or balls and are selected for favorable conductivity. The material for the fusion member is selected for properties that give good bonding at low temperatures. Stress due to heat generation in die chip is alleviated by positioning of the thermal paths and through the use of a stress stabilizing member between the chip and the cover.
Description
The field of the invention is the semiconductor integrated circuit chip encapsulation, specifically has the semiconductor die package of direct heat transmission channel from the chip to the package casing.
Along with the density of semiconductor chip and the raising of power index, the heat that the chip that can leave is produced and the heat delivered that produces can having been increased to the needs outside the Chip Packaging.Under present technical merit, the power that chip produces is about 50 watts, and requirement is in the future estimated to be about 200 watts.Along with continuous progress, the heat that existing encapsulation technology transmission is produced makes the as far as possible little ability of regional area focus just be challenged simultaneously.
In the Chip Packaging process, purpose will be to provide maximum heat transfer by simple package structure.What is called simply is in structure with aspect assembling two.
Under present technical merit, the semiconductor die package technology relates to the considerable additional structure that is used to dispel the heat, and this has increased the complexity of assembling process.
Some examples comprise:
Use is transmitted to heat the heat-conducting liquid of semiconductor package casing from integrated circuit (IC) chip.Heat-conducting liquid is accommodated in the gap between chip and the shell, and needs additional structure come receiving fluids and protection chip.United States Patent (USP) 4323914 shows an example of this technology.
Use the mechanical hot link between chip and the shell, the pressure by hot link element in the assembling process has permanent physical deformation.Pressure particularly to the thermal resistance of the illeffects and the mechanical deformation node of chip, is the problem that this technology will be considered to structure.United States Patent (USP) 5786635 shows an example.
Use remains between the shell of appropriate location at chip and after assembling, the polymer membranous type structural detail of the fusible post of location and support scolder and so on.Being retained in the existence of the structural detail below the shell after assembling, is the problem that will consider in this technology.The Research Disclosure in December, 1991, No.332 show an example.
Use provides the metal shell of the combination forming of heat passage compression and air cooling ability.The Research Disclosure in January, 1991, No.321 show an example.
Need stress-free chip encapsulation technology in present technique, it has low thermal resistance the process that heat is transferred to shell and surrounding environment from chip.
The invention provides a kind of chip-packaging structure principle, wherein constituted the fixing direct heat path of the fusing from the chip surface to the shell.On chip surface, provide the heat passage position with melting element.The form that connects with low thermal resistance on it has been fixed the heat passage position on the shell, shell joint contacts the end of the high heat conductance passage elements with length in addition, make when shell to be positioned at chip when top, touch the chip of high heat conductance element and contact melting element with chip on the chip surface and contact.Carry out little temperature drift then and stop, terminal so that the chip of fusing melting element and high heat conductance element contacts, thus the path of the low thermal resistance from the chip back to the shell is provided.Heat passage melting element that can the deposit requirement.The high heat conductance element can be the suitable shape of post or ball and so on and select suitable thermal conductivity.Selection has the material of the melting element of good bonding character at low temperatures.By means of the location of heat passage and utilize chip and shell between the stress equilibrium element, alleviate the stress that heating causes in the chip.
Fig. 1 is the profile that has the part of semiconductor chip encapsulation of the present invention of heat passage between chip surface and the shell.
Fig. 2 is the perspective view that has the part of semiconductor chip encapsulation of the present invention of heat passage between chip surface and the shell.
Fig. 3 is in the structure of heating position in corresponding to chip, is deposited on the exemplary configurations of the melting element solder joint on the semiconductor chip surface.
Fig. 4 is to use the profile of the semiconductor packages of one deck heat passage Metal Ball.
Fig. 5 is the amplification profile of the ball that encapsulates of Fig. 4 to the interface of chip.
Fig. 6 is the amplification profile of the heat passage that encapsulates of Fig. 4 to chip interface.
Fig. 7 is the embodiment of encapsulation of the present invention, and heat passage wherein joins the chip in the wire bonds array area.
Fig. 8 is the embodiment that has as the semiconductor packages of heat passage element and package casing metal column in aggregates.
Fig. 9 is the profile of semiconductor packages of the present invention, and two layers of Metal Ball that wherein have insert layer are used to reduce mechanical stress.
Figure 10 adopts to be inserted into layer enlarged drawing at the heat transfer interface of Fig. 9 of two layers of Metal Ball separating.
In the encapsulation process of the IC chip that the current densities in chip improves constantly, namely Make size and the power consumption of individual devices very little, the degree that total power consumption also reaches roughly watt, and core The heat difference that the zones of different of sheet produces. In the present invention, provide a kind of chip package knot The structure principle has wherein consisted of the direct heat path of the shell of top from the chip back to the chip, with Just can access and can the high heat that the stress of the extra heat passage at focus place is controlled be passed Defeated.
In conjunction with Fig. 1,2 and 3 the present invention is described generally, the profile and the perspective view of a part of flip-chip that is capped provided by the invention wherein are provided respectively in Fig. 1 and 2, and have figure 3 illustrates the example of the heat transfer path location layout on the chip back.
With reference to Fig. 1 and 2, as first example, show the present invention who is used to flip chip type technology, chip 1 wherein has the contact element 2 of receiving that is electrically connected on its front surface 3, with ball contact 2 upper surface 4 tops that chip 1 is supported in substrate 5 are made it separated from one another, substrate 5 is electrically connected and is supporting pin 6 again.Unshowned conductor is by the electrical interconnection support between substrate 5 and ball 2 and the pin 6.Shell 7 is placed in the assembly parts top of chip 1 and substrate 5, and sealed with surperficial 4 intersections.The present invention relates to hot link and the 8a and the 8b that repeat focus in the control chip 1 by means of the fusion that is provided to the back side 9, thereby provide from the surface of chip 1, is the back side 9, to the direct low thermal resistance path 8 of shell 7 at this moment.Low thermal resistance path 8 have as with the back side 9 of the melting interface of remaining low thermal resistance path on fusion solder joint 10., constitute along the distance of path 8 from the downside of shell 7 by the length of the high heat conductance element 11 that replaces 8 among Fig. 1 and 2,8a and 8b to fusion solder joint 10.High heat conductance element 11 has first end 12 that is affixed to the downside of shell 7 with low thermal resistance.The length of high heat conductance element makes and touches the chip of the end 13 of high heat conductance element 11 when shell 7 is in chip 1 top position, contacts fusion solder joint 10 with chip on the chip back 9 and contacts.Carry out little temperature drift then and stop,, thereby provide from the back side 9 of chip 1 directly the low thermal resistances of shell 7 so that fusion solder joint 10 is melted to the chip contact terminal 13 of high heat conductance element 11 and the back side 9 of chip.Can be on the back side 9 of chip 1 the heat passage fusion solder joint of deposit requirement.High heat conductance element 11 can be the suitable shape of post or ball and so on and select suitable thermal conductivity.Be chosen in the material of the fusion solder joint that has good bonding character under the chip operation temperature.By means of the location of heat passage, alleviate the stress that heating causes in the chip.Obviously, in the layout of either large or small solder joint 10, utilize the different sizes and the density of the solder joint on the chip back shown in Figure 3 on the back side 9 of chip 1, thereby can realize providing the principle of the heat passage of focus on the chip to shell to surrounding environment.Obviously, solder joint can be deposited on any amount of position that the chip electronic circuit is expected to produce focus.Solder joint 10 needn't become grid pattern, and the size that can change them is to adapt to the localized heat transfer requirement of semiconductor chip 1.They can be made of which floor metal to strengthen infiltration and to stop diffusion.Used three layers: the ground floor that is melted to semiconductor chip 1 surface 9 can be the adhesion promotor such as titanium or chromium, and the second layer can be the common metal such as palladium or nickel, and as outermost the 3rd layer can be the gold.
In Fig. 4-6, the explanation of the first example flip chip technology (fct) is provided, wherein the high heat conductance element is ball and post.In the drawings, the heat passage element is illustrated as solid, is illustrated as shade and be electrically connected.
With reference to Fig. 4, show the profile of encapsulation with the Metal Ball of the high heat conductance element 12 of one deck earlier figures.Semiconductor chip 111 is bonded on the substrate 112 by solder ball 113 flip-chips.It is another assembly welding pellet 118 that the outside of substrate 112 connects.The metal shell of encapsulation is 115 soldered, brazing or be glued on the substrate 112.Soldered or the brazing of the layer that Metal Ball 121 is formed and is welded on being positioned on the metal solder joint 131 on semiconductor chip 111 back sides of the fusion solder joint 13 that is equivalent in the earlier figures on the inner surface of metal shell 115.In the structure that shell 115 is waited to want made of plastic, the array that Metal Ball 121 is formed is embedded among the plastic casing, and is soldered to the solder joint 131 on the chip 111 as having metal shell.
Fig. 5 shows the detailed structure at metal-ball interface of Fig. 4.By the Metal Ball 121 that metal or high melting point solder alloy are made, at first be bonded to the inner surface of shell 115 with welding or method of brazing.Then eutectic solder alloy-layer 125 is placed Metal Ball 121 tops.On the back side of semiconductor chip 111, metal solder joint 131 is covered by the another kind of eutectic solder alloy such as lead/ashbury metal, tin/indium alloy, indium 126.In the assembly manipulation process, the encapsulation that has chip is heated to the fusing point of the scolder of layer 125 and 126.The fusing of layer 125,126 and 131 will make Metal Ball 121 be molten to semiconductor chip 111, thereby form the path 11 of earlier figures.Chip surface that layer 125 and 126 causes compensation meter surface roughness and planarization and any irregular gap between the Metal Ball.If Metal Ball is directly made by the eutectic solder alloy, then can further compensate this gap.In this case, can cancel solder layer 125 or even the layer 125 and 126 the two.The layer that Metal Ball 121 is formed provides the release of the stress that the semiconductor chip 111 required thermal expansion mismatch by between semiconductor chip 111 and the shell 115 cause.
With reference to Fig. 6, show the post of the path 11 that is used for earlier figures.Use the main benefit of post to provide extra Stress Release, the height that wherein can cut out post is to reduce the mechanical stress of chip.In Fig. 6, the metal column 221 by making than the Heat Conduction Material the higher solder alloy such as copper or fusing point by eutectic solder alloy-layer 225, is soldered to the inner surface of the metal shell of encapsulation 215.The back side of semiconductor chip 211 has the array of metal solder joint 231 compositions that covered by eutectic solder alloy-layer 226.In assembling process, encapsulation is heated to the fusing point of solder alloy 226, this will with post 221 fusions, so that 215 more effective heat transfer path to be provided from chip 211 to package casing.As a kind of constructive variations, post 221 can be combined into a slice copper or copper-tungsten with shell 215, and perhaps post 221 can be made of the microprojection array application of shell 215.
Except as " flip-chip " type technology in conjunction with first example of Fig. 1-6, the present invention can also be used for such as other the technology in conjunction with wire bonds shown in Figure 7 and the metal column that passes through shell shown in Figure 8.
With reference to Fig. 7, show the profile of BGA Package shell, wherein semiconductor chip 310 is placed among the center cavity 311 of substrate 312, and is connected to substrate 312 lip-deep unshowned wirings with the well-known wire bonds method of present technique.Connection from substrate 312 to the outside is the array of forming by solder ball 318.Metal shell is 315 soldered, brazing or be glued to substrate.The array that Metal Ball 321 is formed is soldered to the metal solder joint 331 on the source 333 of having of the inner surface of shell 315 and semiconductor chip 311.Electric insulation but the thin layer 332 of heat conduction is placed in metal solder joint 331 and chip has between the source 333 is to prevent short circuit.
With reference to Fig. 8, show the profile that adopts with the BGA Package of the integrated metal shell of the array that extends through and form with shell metal column in aggregates.With solder ball 413 semiconductor chip 411 flip-chips are bonded to substrate 412, and provided outside the connection by the solder ball 418 on substrate 412 opposite sides.Metal shell is 415 soldered, brazing or be glued on the substrate 412, with protection semiconductor chip 411.The array that metal column 421 is formed is stamped by metal shell 415, keeps clamping by the deformation in metal shell 415 processes and each by means of punching press, causes an end of each metal column to be projected into the outside of shell 415.The position of post usually be used for semiconductor chip 411 back sides on the metal solder joint of type of earlier figures aim at.Eutectic solder alloy-layer 426 is covered with the solder joint that contacts with metal column.In the encapsulation assembling process, encapsulation is heated to the fusing point of solder alloy, and to pressing down shell 415, is inserted in the solder alloy 426 of fusing until metal column 421.Metal column 421 can not apply unnecessary mechanical stress to chip with chip 411 thermo-contacts by scolder 426.Utilize mold pressing or sintering method, metal column can be manufactured the part of metal shell, become as a whole.Metal column also can be made by the material that is different from shell, and for example post is made of copper, and shell is made by copper/tungsten alloy.
In all packaging technologies of being discussed, diameter, length and material selection by means of changing the heat passage material can further reduce the mechanical stress to chip.
Two layers of ball of insert layer are arranged in the middle of utilizing, can obtain the further reduction of mechanical stress on the chip.Fig. 9 shows this structure, and Figure 10 shows the details of the amplification of insert layer.
With reference to Fig. 9, show that present technique is well-known not to belong to a kind of typical pin grid array package of the present invention.The structure of chip and two Metal Ball layers between the shell of encapsulation is described used as example herein.Idea described herein can be used to have any other semiconductor die package of one or more chips.The array that the solder ball 513 that generally adopts with industrial quarters is formed is bonded to substrate 512 with semiconductor chip 511 flip-chips.The outer surface of substrate 512 has the array that connects pin 514 compositions.Metal shell is 515 soldered, brazing or be glued on the substrate 512.Two layers of Metal Ball layer 516 and 517 is bonded to insert layer 518.
Figure 10 shows the detailed structure at interface.With reference to Figure 10, insert layer 518 is made up of the core material layer 519 that two surfaces are laminated with material layer 520 and 521.The through hole 522 that outer 520 Heat Conduction Materials that connect together with 521 are filled is arranged.Through hole 522 is aimed at Metal Ball 516 and 517. Layer 520 and 521 and the optimal material of through hole 522 be copper.Through hole 522 is invar, molybdenum or thermal coefficient of expansion other material between semiconductor chip and package casing 515 by the material of the core layer 523 of wherein extending.Metal Ball 516 and 517 can be the Heat Conduction Material with any kind of of the material compatibility of semiconductor chip 511 and package casing 515.For example can be copper, lead/ashbury metal, tin/indium alloy or indium.If adopt copper, then to add another eutectic solder alloy-layer, so that ball is molten to the metal solder joint 524 on the upper surface 525 of the inner surface of shell 515 and semiconductor chip 511.If the eutectic solder alloy is used to ball, then can directly ball bonding be received the inner surface of shell 515 and the metal solder joint on the semiconductor chip 511. Optional mask layer 527 and 528 on the metal level 520 and 521 can be used to separate separately the ball 516 and 517 in the figure similar with combining figure that Fig. 3 discusses respectively.
What described is a kind of semiconductor integrated chip encapsulation principle, thereby wherein provides directly from the chip surface position to shell to the low thermal resistance path of surrounding environment.
Claims (20)
1. semiconductor die package, wherein semiconductor chip is provided at the position of shell below and adjacent housings, it is characterized in that described semiconductor die package comprises: at least one is used for the transmission to the heat of described chip place generation from described chip surface to described shell and in the fixing direct heat passage elements of at least one end fusion.
2. the semiconductor die package of claim 1, wherein said heat passage element are that first is fixed to described shell and second portion and melting element and is melted in high heat conductance passage elements on the described chip surface.
3. the semiconductor die package of claim 2, wherein said heat passage element comprises at least a element that is selected from ball and post.
4. the semiconductor die package of claim 3, the wherein said element that is selected from ball and post is made of copper.
5. the semiconductor die package of claim 3 wherein further comprises: the low-melting-point metal of deposit and fusion between element that is selected from described ball and post and described shell at least is used for described heat passage element fixing to described shell.
6. the semiconductor die package of claim 3, wherein said heat passage element runs through by described shell to the end with the post element that fixedly comprises at least of described shell.
7. the semiconductor die package of claim 6, wherein said post is made of copper, and described shell is made by the alloy of copper and tungsten.
8. the semiconductor die package of claim 3, wherein said melting element is the low-melting-point metal of one deck at least solder joint that is positioned on the described chip surface.
9. the semiconductor die package of claim 8, wherein said melting element are the tactic low-melting-point metal solder joints that is selected from the 3rd layer of formation that the ground floor of titanium and chromium, the second layer that is selected from palladium and nickel and gold form from the described surface of described chip respectively.
10. the encapsulation of the integrated circuit (IC) chip in the electronic installation, wherein, the dielectric substrate district supports to have at least one integrated circuit (IC) chip of surface thermal radiation and support outer surface to be exposed to the crust component of external environment condition, the described surface thermal radiation of the contiguous described integrated circuit (IC) chip of the inner surface of this crust component is also separated with it, it is characterized in that described integrated circuit (IC) chip encapsulation comprises:
At least one high heat conductance passage elements between the described inner surface of the described lip-deep heating position of described integrated circuit (IC) chip and described crust component is used for heat transfer.
11. the encapsulation of the integrated circuit (IC) chip of claim 10, wherein said high heat conductance passage elements comprises the described lip-deep low-melting-point metal melting element of described integrated circuit (IC) chip.
12. the encapsulation of the integrated circuit (IC) chip of claim 11, wherein said high heat conductance passage elements comprises the element that is selected from ball and post.
13. the encapsulation of the integrated circuit (IC) chip of claim 11, the wherein said high heat conductance passage elements that is selected from ball and post is made of copper.
14. the integrated circuit (IC) chip of claim 11 encapsulation, the described lip-deep described low-melting-point metal melting element of wherein said integrated circuit (IC) chip are the tactic low-melting-point metal solder joints that is selected from the 3rd layer of formation that the ground floor of titanium and chromium, the second layer that is selected from palladium and nickel and gold form from the described surface of described chip respectively.
15. the integrated circuit (IC) chip of claim 14 encapsulation wherein further comprises: the low-melting-point metal of deposit and fusion between described passage elements and described shell at least, the described high heat conductance passage elements that is used to be selected from ball and post is fixing to described shell.
16. the integrated circuit (IC) chip of claim 12 encapsulation, wherein said high heat conductance path post element runs through by described shell to the end with described cartridge by diffusion of volatile treating agent that fixedly comprises at least of described shell.
17. the encapsulation of the integrated circuit (IC) chip of claim 16, wherein said post element is made of copper, and described shell is made by the alloy of copper and tungsten.
18. the encapsulation of the integrated circuit (IC) chip of claim 12, wherein said high heat conductance path post element is made by the plastics of molding to the described shell that fixedly comprises of described shell, and described cylindricality high heat conductance passage elements is embedded in wherein.
19. the encapsulation of the integrated circuit (IC) chip of claim 16, wherein said post element is made by the high melting point solder alloy.
20. the encapsulation of the integrated circuit (IC) chip of claim 12, wherein said high heat conductance passage elements is made by two layers of Metal Ball that are inserted into layer separation.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US52360600A | 2000-03-13 | 2000-03-13 | |
| US09/523,606 | 2000-03-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1313637A CN1313637A (en) | 2001-09-19 |
| CN1165079C true CN1165079C (en) | 2004-09-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011048999A Expired - Fee Related CN1165079C (en) | 2000-03-13 | 2001-02-28 | Chip package with high effective heat transferring structure |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3447051B2 (en) |
| KR (1) | KR20010091898A (en) |
| CN (1) | CN1165079C (en) |
| TW (1) | TW579555B (en) |
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| CA2547358C (en) * | 2001-05-24 | 2013-08-06 | Fry's Metals, Inc. | Thermal interface material and solder preforms |
| US6576992B1 (en) * | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| KR20050016087A (en) * | 2003-08-06 | 2005-02-21 | 로무 가부시키가이샤 | Semiconductor device |
| US7049695B1 (en) * | 2005-01-14 | 2006-05-23 | International Business Machines Corporation | Method and device for heat dissipation in semiconductor modules |
| US9299634B2 (en) | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
| US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
| US20080290502A1 (en) * | 2007-05-25 | 2008-11-27 | Zafer Kutlu | Integrated circuit package with soldered lid for improved thermal performance |
| JP5356972B2 (en) * | 2009-10-20 | 2013-12-04 | 新光電気工業株式会社 | Heat dissipating component, manufacturing method thereof, and semiconductor package |
| US8553420B2 (en) * | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
| US8633576B2 (en) | 2011-04-21 | 2014-01-21 | Tessera, Inc. | Stacked chip-on-board module with edge connector |
| JP5974454B2 (en) * | 2011-11-14 | 2016-08-23 | イビデン株式会社 | Electronic components |
| JP6618745B2 (en) * | 2015-09-18 | 2019-12-11 | セイコーインスツル株式会社 | Electronic components |
| JP6681716B2 (en) * | 2016-01-13 | 2020-04-15 | セイコーインスツル株式会社 | Electronic parts |
| US10588231B2 (en) * | 2017-05-18 | 2020-03-10 | Covidien Lp | Hermetically sealed printed circuit boards |
| US10973142B2 (en) | 2017-05-18 | 2021-04-06 | Covidien Lp | Hermetically sealed printed circuit boards |
| US10580715B2 (en) * | 2018-06-14 | 2020-03-03 | Texas Instruments Incorporated | Stress buffer layer in embedded package |
| US11626343B2 (en) | 2018-10-30 | 2023-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with enhanced thermal dissipation and method for making the same |
| CN210325761U (en) * | 2018-12-29 | 2020-04-14 | 华为技术有限公司 | Chip device and electronic equipment |
| KR20210018577A (en) | 2019-08-05 | 2021-02-18 | 삼성전자주식회사 | Semiconductor package device |
| CN110767617A (en) * | 2019-10-31 | 2020-02-07 | 太极半导体（苏州）有限公司 | Sealing cover balanced filling packaging structure and process for sorting flip chip |
| JP7298799B1 (en) * | 2022-10-26 | 2023-06-27 | 三菱電機株式会社 | Semiconductor device and its manufacturing method |
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2001
- 2001-01-31 TW TW090101903A patent/TW579555B/en not_active IP Right Cessation
- 2001-02-21 KR KR1020010008576A patent/KR20010091898A/en not_active Application Discontinuation
- 2001-02-28 CN CNB011048999A patent/CN1165079C/en not_active Expired - Fee Related
- 2001-03-08 JP JP2001065576A patent/JP3447051B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1313637A (en) | 2001-09-19 |
| TW579555B (en) | 2004-03-11 |
| KR20010091898A (en) | 2001-10-23 |
| JP3447051B2 (en) | 2003-09-16 |
| JP2001298131A (en) | 2001-10-26 |
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Granted publication date: 20040901 Termination date: 20120228 |