TWI529872B - 射頻裝置封裝及其製造方法 - Google Patents

射頻裝置封裝及其製造方法 Download PDF

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TWI529872B
TWI529872B TW102129956A TW102129956A TWI529872B TW I529872 B TWI529872 B TW I529872B TW 102129956 A TW102129956 A TW 102129956A TW 102129956 A TW102129956 A TW 102129956A TW I529872 B TWI529872 B TW I529872B
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radio frequency
frequency device
semiconductor substrate
device package
interconnect structure
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TW201411787A (zh
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楊明宗
洪建州
李東興
黃偉哲
黃裕華
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聯發科技股份有限公司
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Description

射頻裝置封裝及其製造方法
本發明係關於一種射頻裝置封裝及其製造方法，特別係關於一種具改良的射頻損失和線性度性能的射頻裝置封裝及其製造方法。
在高速(high speed)應用中(例如射頻(radio-frequency，以下簡稱RF)應用)，習知的RF裝置封裝包括數個分離的(discrete)射頻晶片和其他的主動元件或被動元件(例如功率放大器(power amplifiers(PAs)、濾波器、去耦電路或匹配電路(decoupling or matching circuits))，該主動元件或被動元件利用一焊線製程固接於一RF主晶片(RF main die)上。然而，習知的RF裝置封裝會因為焊線接合的RF晶片的接地平面(ground(GND)plane)係設計為接觸RF主晶片，所以會遭受RF損失(low RF loss)和低線性度(low linearity)的問題。
因此，在此技術領域中，需要一種改良式的RF裝置封裝，其具改良的射頻損失和線性度性能。
有鑑於此，本發明之目的在於提供一種改良式的射頻裝置封裝及其製造方法。
本發明之一實施例係提供一種射頻裝置封裝。上述射頻裝置封裝包括一基座；以及一射頻裝置晶片，固接於上述基座上，其中上述射頻裝置晶片包括一半導體基板，其具有一前側和一後側；一射頻構件，設置於上述半導體基板的上述前側；一內連線結構，設置於上述射頻構件上，其中上述內連線結構係電性連接至上述射頻構件，且上述半導體基板的一厚度小於上述內連線結構的一厚度；一通孔，從上述半導體基板的上述後側穿過上述半導體基板形成，且連接至上述內連線結構；以及一矽通孔結構，設置於上述通孔內。
本發明之另一實施例係提供一種射頻裝置封裝的製造方法。上述射頻裝置封裝的製造方法包括提供一射頻裝置晶片，其中上述射頻裝置晶片包括一半導體基板，其具有一前側和一後側，其中上述半導體基板具有一第一厚度；一射頻構件，設置於上述半導體基板的上述前側；以及一內連線結構，設置於上述射頻構件上，其中上述內連線結構係電性連接至上述射頻構件；進行一薄化製程，從上述半導體基板的上述後側移除一部分上述半導體基板，因而形成一薄化半導體基板，其中上述薄化半導體基板具有小於上述第一厚度的一第二厚度；從上述薄化半導體基板的一後側移除上述薄化半導體基板的一部分和上述內連線結構的一介電層的一部分，直到上述內連線結構的一第一金屬層圖案暴露出來為止，因而形成一通孔；於上述通孔內形成一矽通孔結構；以及將一射頻裝置晶片固接於一基座上，其中上述薄化半導體基板的上述後側較該薄化半導體基板的一前側接近於上述基座。
本發明所揭示之射頻裝置封裝及其製造方法，可改善射頻裝置的RF損失(low RF loss)和低線性度(high linearity)等缺點。
500‧‧‧射頻裝置封裝
300‧‧‧射頻裝置晶片
200‧‧‧半導體基板
200a‧‧‧薄化半導體基板
201‧‧‧淺溝槽隔絕物
202‧‧‧射頻構件
204、208、212‧‧‧介電層
206、210‧‧‧金屬層圖案
220‧‧‧內連線結構
222‧‧‧前側
224、224a‧‧‧後側
230‧‧‧通孔
232‧‧‧側壁
234‧‧‧底部
236、236a‧‧‧絕緣襯墊
238‧‧‧導電介層孔插塞
240‧‧‧矽通孔結構
241‧‧‧末端
242‧‧‧導電凸塊
246‧‧‧被動構件
250‧‧‧基座
T1、T2、T3‧‧‧厚度
d‧‧‧距離
H‧‧‧高度
第1~7圖為本發明一實施例之一射頻裝置封裝的製造方法的剖面示意圖。
為了讓本發明之目的、特徵、及優點能更明顯易懂，下文特舉實施例，並配合所附圖示，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。且實施例中圖式標號之部分重複，係為了簡化說明，並非意指不同實施例之間的關聯性。
第1~7圖為本發明一實施例之一射頻(RF)裝置封裝500的製造方法的剖面示意圖。在本實施例中，射頻裝置封裝500係利用一矽通孔技術(through silicon via technology,TSV technology)形成。在本發明一實施例中，射頻裝置封裝500包括一基座250；以及一射頻裝置晶片300，固接於基座250上，其中射頻裝置晶片300包括：一半導體基板200a；一射頻構件202；一內連線結構220，其中內連線結構220係電性連接至射頻構件202，且半導體基板200a的厚度T3少於內連線結構220的厚度T2；一通孔230，從半導體基板200a的該後側224a穿過該半導體基板200a形成，且連接至該內連線結構220；以及一 矽通孔結構240，設置於通孔230內。
如第1圖所示，提供一射頻(RF)裝置晶片300。在本發明一實施例中，射頻裝置晶片300可包括一半導體基板200，且半導體基板200具有一前側222和一後側224。在本發明一實施例中，半導體基板200可為矽基板。在本發明其他實施例中，可利用鍺化矽(SiGe)基板、塊狀半導體(bulk semiconductor)基板、應變半導體(strained semiconductor)基板、化合物半導體(compound semiconductor)基板、絕緣層上覆矽(silicon on insulator,SOI)基板或其他常用之半導體基板做為半導體基板200。可藉由於半導體基板200中植入p型或n型不純物的方式，使半導體基板200具有想要的導電類型。一射頻(RF)構件202，係設置於半導體基板200的前側222上。如第1圖所示，射頻構件202可藉由形成於半導體基板200中的淺溝槽隔絕物(STI feature)201以與其他元件(圖未顯示)隔絕。一內連線結構220，係形成於半導體基板200的前側222上。在本發明一實施例中，可由介電層204、介電層208和介電層212以及金屬層圖案206、金屬層圖案210構成內連線結構220。上述內連線結構220可用於射頻構件202的訊號的輸入/輸出(input/output，I/O)連接或接地(GND)。因此，可於內連線結構220中形成訊號端或接地(GND)端。在如第1圖所示之本發明實施例中，內連線結構220的金屬層圖案206、金屬層圖案210係電性連接至射頻構件202。在本發明一實施例中，金屬層圖案210係設置於內連線結構220的一頂層(top level)，而金屬層圖案206係設置於內連線結構220的一頂層下一層(lower-to-top level)。上述介電層和金屬層圖案 的數目係依據射頻構件202的設計而定，然非限制本發明的保護範圍。在如第1圖所示之本發明實施例中，半導體基板200的厚度T1大於內連線結構220的厚度T2。
接著，如第2圖所示，可翻轉射頻裝置晶片300，使半導體基板200的後側224朝上。然後，進行一薄化製程，從半導體基板200的後側224(如第1圖所示)移除一部分半導體基板200(如第1圖所示)而形成薄化半導體基板200a，以降低半導體基板200的厚度。在本發明一實施例中，上述薄化製程包括一化學機械研磨製程(chemical mechanical polishing,CMP)。進行上述薄化製程之後，形成一薄化半導體基板200a。在本發明一實施例中，上述薄化半導體基板200a具有一厚度T3，厚度T3小於如第1圖所示的半導體基板200的厚度T1。在本實施例中，上述薄化半導體基板200a的厚度T3可設計為介於20μm和50μm之間，以避免薄化半導體基板200a破裂。並且，薄化半導體基板200a的厚度T3可設計為小於內連線結構220的厚度T2。
接著，如第3~5圖所示，進行用於射頻裝置晶片300的矽通孔製程。如第3圖所示，進行例如一雷射鑽孔製程的一溝槽開口製程，從薄化半導體基板200a的後側224a移除薄化半導體基板200a的一部分和內連線結構220的一介電層204的一部分，直到內連線結構220的金屬層圖案206暴露出來為止，因而形成通孔230，即內連線結構220從通孔230暴露出來。在本發明一實施例中，通孔230係定義後續形成的矽通孔結構的形成位置。
接著，如第4圖所示，利用一沉積製程、一微影製 程和一圖案化製程，一致地(conformably)於每一個通孔230的一底部234和一側壁232上形成一絕緣襯墊236。並且，絕緣襯墊236覆蓋內連線結構220的金屬層圖案206的一部分。
接著，如第5圖所示，進行一蝕刻製程，以移除絕緣襯墊236位於上述通孔230的底部234上的部分，因而形成一絕緣襯墊236a。在本發明一實施例中，上述蝕刻製程可包括一乾蝕刻製程或一濕蝕刻製程。之後，於上述通孔230中填入一導電材料，以形成一導電介層孔插塞238，其中導電介層孔插塞238具有一第一端和一第二端，其中第一端係連接至內連線結構220，且第二端對齊半導體基板200a的後側224。如第5圖所示，導電介層孔插塞238覆蓋絕緣襯墊236的側壁。形成導電介層孔插塞238之後，於通孔230中形成一矽通孔結構240，上述矽通孔結構240係包括絕緣襯墊236a和被絕緣襯墊236a包圍的導電介層孔插塞238。在本實施例中，上述矽通孔結構240係電性連接至位於內連線結構220的頂層下一層的金屬層圖案206。
之後，如第6圖所示，進行一凸塊製程，於矽通孔結構240的一末端241上形成一導電凸塊242，其中上述末端241接近於薄化半導體基板200a的後側224a。在本發明一實施例中，上述導電凸塊242可包括一焊錫凸塊、一金屬柱狀物或上述組合。
然後，如第7圖所示，可再次翻轉射頻裝置晶片300，使半導體基板200的後側224a朝下。接著，進行一固接製程，將射頻裝置晶片300固接於一基座250上。如第7圖所示， 將射頻裝置晶片300固接於基座250上之後，導電凸塊242係連接至基座250。在本發明一實施例中，基座250可包括一主晶片(main die)或一印刷電路板(PCB)。在本發明一實施例中，上述薄化半導體基板200a的後側224a較前側222更接近於基座250。射頻構件202和基座250之間的一距離d等於上述薄化半導體基板200a的總厚度T3加上導電凸塊242的一高度H的總合。進行上述製程之後，本發明一實施例之一射頻(RF)裝置封裝500係製造完成。
在本發明其他實施例中，射頻裝置封裝500的射頻裝置晶片300可更包括一被動構件246，設置於內連線結構220中，其中被動構件246包括位於內連線結構220的頂層的金屬層圖案210。
本發明實施例係提供一種射頻(RF)裝置封裝500。在本發明一實施例中，上述射頻裝置封裝係使用用於射頻裝置晶片的一薄化製程和一矽通孔製程。相較於習知的焊線(bonding wire)，使用一矽通孔結構的上述射頻裝置晶片可達到一高密度和一較短連接路徑的目標。相較於習知的焊線裝置封裝(bonding device package)，本發明一實施例的射頻裝置封裝係由於用於射頻裝置晶片的矽通孔結構而可具有較低的內連線電阻。並且，可於上述射頻裝置封裝的內連線結構中形成訊號端或接地(GND)端。因此，本發明一實施例的射頻裝置封裝可不需用於習知的焊線裝置封裝的一接地平面(GND plane)，上述習知的焊線裝置封裝的接地平面設計設置於射頻裝置封裝的一背側上且接觸基座。因此，本發明實施例的射頻裝置封 裝的製造可避免習知的焊線裝置封裝因為接地平面接觸基座而產生RF性能衰退的缺點。並且，設計本發明實施例的射頻裝置封裝的一背側較前側更接近於基座。因此，相較於習知的焊線裝置封裝(bonding device package)，本發明一實施例的射頻裝置封裝可對被動構件提供一更高的設置位置。可以降低基座對被動構件的干擾，使射頻裝置封裝達到更優異的性能，例如低RF損失(low RF loss)和高線性度特性(high linearity)。
雖然本發明已以實施例揭露於上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
500‧‧‧射頻裝置封裝
300‧‧‧射頻裝置晶片
201‧‧‧淺溝槽隔絕物
202‧‧‧射頻構件
204、208、212‧‧‧介電層
206、210‧‧‧金屬層圖案
220‧‧‧內連線結構
222‧‧‧前側
224a‧‧‧後側
232‧‧‧側壁
234‧‧‧底部
236a‧‧‧絕緣襯墊
238‧‧‧導電介層孔插塞
240‧‧‧矽通孔結構
242‧‧‧導電凸塊
246‧‧‧被動構件
250‧‧‧基座
T2、T3‧‧‧厚度
d‧‧‧距離
H‧‧‧高度

Claims (20)

  1. 一種射頻裝置封裝，包括：一基座；以及一射頻裝置晶片，固接於該基座上，其中該射頻裝置晶片包括：一半導體基板，具有一前側和一後側；一射頻構件，設置於該半導體基板的該前側；一內連線結構，設置於該射頻構件上，其中該內連線結構係電性連接至該射頻構件，且該半導體基板的一厚度小於該內連線結構的一厚度；一通孔，從該半導體基板的該後側穿過該半導體基板形成，且連接至該內連線結構；以及一矽通孔結構，設置於該通孔內。
  2. 如申請專利範圍第1項所述之射頻裝置封裝，其中該矽通孔結構包括：一導電介層孔插塞，具有一第一端和一第二端，其中該第一端係連接至該內連線結構，且該第二端對齊該半導體基板的該後側；以及一絕緣襯墊，圍繞該導電介層孔插塞。
  3. 如申請專利範圍第1項所述之射頻裝置封裝，其中該內連線結構從該通孔暴露出來。
  4. 如申請專利範圍第1項所述之射頻裝置封裝，更包括：一導電凸塊，設置於該矽通孔結構的一末端上，其中該末端接近於該半導體基板的該後側，且該導電凸塊連接至該 基座。
  5. 如申請專利範圍第4項所述之射頻裝置封裝，其中該射頻構件和該基座之間的一距離等於該半導體基板的該厚度加上該導電凸塊的一高度的總合。
  6. 如申請專利範圍第1項所述之射頻裝置封裝，其中該半導體基板的該厚度介於20μm和50μm之間。
  7. 如申請專利範圍第1項所述之射頻裝置封裝，其中該內連線結構具有分別位於一頂層下一層的一第一金屬層圖案和位於一頂層的一第二金屬層圖案，且該矽通孔結構係直接連接至位於該頂層下一層的该第一金屬層圖案。
  8. 如申請專利範圍第7項所述之射頻裝置封裝，其中該射頻裝置晶片更包括一被動構件，該被動構件設置於該內連線結構中，其中該被動構件包括位於該內連線結構的該頂層的該第二金屬層圖案。
  9. 如申請專利範圍第1項所述之射頻裝置封裝，其中該射頻裝置晶片包括形成於該內連線結構中的訊號端或接地端。
  10. 一種射頻裝置封裝的製造方法，包括下列步驟：提供一射頻裝置晶片，其中該射頻裝置晶片包括：一半導體基板，具有一前側和一後側，其中該半導體基板具有一第一厚度；一射頻構件，設置於該半導體基板的該前側；以及一內連線結構，設置於該射頻構件上，其中該內連線結構係電性連接至該射頻構件；進行一薄化製程，從該半導體基板的該後側移除一部分該 半導體基板，因而形成一薄化半導體基板，其中該薄化半導體基板具有小於該第一厚度的一第二厚度；從該薄化半導體基板的一後側移除該薄化半導體基板的一部分和該內連線結構的一介電層的一部分，直到該內連線結構的一第一金屬層圖案暴露出來為止，因而形成一通孔；於該通孔內形成一矽通孔結構；以及將該射頻裝置晶片固接於一基座上，其中該薄化半導體基板的該後側較該薄化半導體基板的一前側接近於該基座。
  11. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，其中形成該矽通孔結構包括：於該通孔的一底部和一側壁上形成一絕緣襯墊；進行一蝕刻製程以移除該絕緣襯墊位於該通孔的該底部上的部分；以及於該通孔中填入一導電材料，以形成一導電介層孔插塞。
  12. 如申請專利範圍第11項所述之射頻裝置封裝的製造方法，其中該蝕刻製程包括一乾蝕刻製程或一濕蝕刻製程。
  13. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，將該射頻裝置晶片固接於該基座上之前更包括：於該矽通孔結構的一末端上形成一導電凸塊，其中該末端接近於該薄化半導體基板的該後側。
  14. 如申請專利範圍第13項所述之射頻裝置封裝的製造方法，其中將該射頻裝置晶片固接於該基座上之後，該導電凸塊係連接至該基座。
  15. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法， 其中該第二厚度介於20μm和50μm之間。
  16. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，其中該內連線結構具有分別位於一頂層下一層的一第一金屬層圖案和位於一頂層的一第二金屬層圖案，且該矽通孔結構係直接連接至位於該頂層下一層的该第一金屬層圖案。
  17. 如申請專利範圍第16項所述之射頻裝置封裝的製造方法，其中該射頻裝置晶片更包括一被動構件，該被動構件設置於該內連線結構中，其中該被動構件包括位於該內連線結構的該頂層的該第二金屬層圖案。
  18. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，其中該薄化製程包括一化學機械研磨製程。
  19. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，其中利用一雷射鑽孔製程形成該通孔。
  20. 如申請專利範圍第10項所述之射頻裝置封裝的製造方法，其中該內連線結構具有一第三厚度，其中該第二厚度小於該第三厚度。
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US9607894B2 (en) 2017-03-28
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US20150162267A1 (en) 2015-06-11
US20150162242A1 (en) 2015-06-11

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