TWI628766B - 晶粒裝置、半導體裝置及其製造方法 - Google Patents

晶粒裝置、半導體裝置及其製造方法 Download PDF

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Publication number
TWI628766B
TWI628766B TW106115641A TW106115641A TWI628766B TW I628766 B TWI628766 B TW I628766B TW 106115641 A TW106115641 A TW 106115641A TW 106115641 A TW106115641 A TW 106115641A TW I628766 B TWI628766 B TW I628766B
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Taiwan
Prior art keywords
die
active layer
bump
substrate
die device
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TW106115641A
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TW201832333A (zh
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Po-Chun Lin
林柏均
Chin-Lung Chu
朱金龍
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Nanya Technology Corporation
南亞科技股份有限公司
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Publication of TWI628766B publication Critical patent/TWI628766B/zh
Publication of TW201832333A publication Critical patent/TW201832333A/zh

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Abstract

本揭露係關於一種晶粒裝置、半導體裝置及其製造方法。該晶粒裝置包含一晶粒以及一凸塊。該晶粒具有一主動層以及一互連元件，其中該互連元件經配置以電性連接該主動層且接觸該晶粒中的一基板。該凸塊獨立於該晶粒之外且經配置以電性連接該主動層。

Description

晶粒裝置、半導體裝置及其製造方法
本揭露係關於一種晶粒裝置、半導體裝置及其製造方法，特別關於一種包含堆疊晶粒的半導體裝置及其製造方法。
現代電路的製造涉及一些步驟。先在半導體晶圓上製造積體電路，該半導體晶圓包含多個重複的半導體晶片，各自包括多個積體電路。而後，自晶圓切割半導體晶片並且封裝。封裝製程具有兩個主要目的：為了保護半導體晶片以及將內部積體電路連接至外部連接。
在封裝積體電路(IC)晶片中，焊接接合系最常用於接合IC晶片以封裝基板的方法之一，該等基板可包含或不包含積體電路或其他被動元件。在封裝製程過程中，可使用覆晶接合，將半導體晶粒或晶片安裝於封裝基板上。該封裝基板可為中介物(interposer)，其包含金屬連接用於在對側之間引導電子訊號。亦可使用其他形式的基板。可經由直接金屬接合、焊接接合、或類似方法，將晶粒接合至基板。晶片封裝有許多挑戰。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露的實施例提供一種晶粒裝置。該晶粒裝置包含一晶粒及一凸塊。該晶粒具有一主動層及一互連元件。該互連元件經配置以電性連接該主動層且接觸該晶粒中的一基板。該凸塊獨立於該晶粒之外且經配置以電性連接該主動層。
在本揭露的一些實施例中，該互連元件的一熔點低於銅的一熔點。
在本揭露的一些實施例中，該互連元件的一材料包含錫(Sn)。
在本揭露的一些實施例中，該凸塊位於該晶粒的該主動層上。
在本揭露的一些實施例中，該凸塊位於該晶粒的一第一表面上，以及該晶粒裝置未有其他凸塊位於該晶粒的一第二表面上，該第二表面與該第一表面對立。
在本揭露的一些實施例中，該主動層位於該晶粒的該第一表面內。
本揭露的實施例提供一種半導體裝置。該半導體裝置包含一第一晶粒裝置及一第二晶粒裝置。該第一晶粒裝置包含具有一第一主動層的一第一晶粒，以及一第一互連元件。該第一互連元件經配置以電性連接該第一主動層。該第二晶粒裝置包含具有一第二主動層的一第二晶粒，以及一凸塊。該凸塊獨立於該第二晶粒之外且經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件環繞。
在本揭露的一些實施例中，該凸塊接觸該第一互連元件。
在本揭露的一些實施例中，該半導體裝置另包含一黏著層，藉以使得該第二晶粒裝置接合至該第一晶粒裝置。
在本揭露的一些實施例中，該第二晶粒裝置位於該黏著層上，以及該黏著層位於該第一晶粒裝置上。
在本揭露的一些實施例中，該第一晶粒裝置與該第二晶粒裝置之間的一距離與該黏著層的一厚度實質相同。
在本揭露的一些實施例中，該凸塊的一部分受到該第一互連元件環繞，以及該凸塊的剩餘部分受到該黏著層環繞。
在本揭露的一些實施例中，該第一互連元件的一熔點低於銅的熔點。
在本揭露的一些實施例中，在本揭露的一些實施例中，該第一互連元件的材料包含錫(Sn)。
在本揭露的一些實施例中，該凸塊為該第二凸塊。該第一晶粒裝置令包含一第一凸塊，獨立於該第一晶粒之外，經配置用於該第一主動層的電性連接。
在本揭露的一些實施例中，該第一凸塊位於該第一晶粒的一第一表面上，以及該第一晶粒裝置未有其他凸塊位於該第一晶粒的一第二表面上，該第二表面與該第一表面對立。
在本揭露的一些實施例中，該第一主動層位於該第一晶粒的該第一表面內。
在本揭露的一些實施例中，該第一凸塊位於該第一晶粒的該第一主動層上。
本揭露的實施例提供一種方法，包含藉由進行一操作兩次，得到一第一晶粒裝置與一第二晶粒裝置，該操作包含形成一主動層於一基板中且於該基板上；形成一凸塊於該主動層上；形成一溝槽於該基板中，暴露該主動層；以及形成一拋光的傳導層於該溝槽中且於該主動層上；以及將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該拋光的傳導層中。
在本揭露的一些實施例中，該方法另包含藉由熔化該拋光的傳導層以形成一熔化且拋光的傳導層，其中該拋光的傳導層的一熔點低於銅的熔點。
在本揭露的一些實施例中，將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該拋光的傳導層中包含將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該熔化且拋光的傳導層中。
在本揭露的一些實施例中，一晶粒的一互連元件接觸一基板。由於該互連元件由非銅的材料製成，因而雖然該互連元件接觸該基板，並無發生銅擴散問題。因此，不需要絕緣層分隔該互連元件與該基板。因此，該半導體製程相對簡單。
相對地，在一些現有的半導體裝置中，現有的半導體裝置包含一第一晶粒，具有銅的貫穿矽插塞。該貫穿矽插塞作為該第一晶粒的一主動層的電性連接。若該貫穿矽插塞接觸該第一晶粒的一基板，該銅的貫穿矽插塞會擴散至基板中，造成該基板中的洩漏路徑。以此方式，現有的半導體裝置可能功能異常。為了防止此問題，在該貫穿矽插塞與該基板之間配置該第一晶粒的一隔離層，藉以分隔該貫穿矽插塞與該基板。為了製造該隔離層，製程相對複雜。該第一晶粒的內部結構與第二晶粒的內部結構實質相同。因此，該第二晶粒具有與該第一晶粒相同的問題。
再者，在本揭露中，由於不需要凸塊在第一晶粒裝置的第二表面上作為第一晶粒之第一互連結構的電性連接，並且由於第二晶粒裝置的凸塊作為第二晶粒之第二主動層的電性連接且係插入至第一互連結構中，因而本揭露的半導體裝置之高度相對小。本揭露的半導體裝置因而相對緊密。
相對地，在一些現有的半導體裝置中，現有的半導體裝置包含一第一晶粒與一第二晶粒。該第一晶粒與該第二晶粒經由它們的凸塊而接合在一 起。以此方式，由於該等凸塊，該第一晶粒與該第二晶粒之間有一距離。此距離對於縮小現有半導體裝置尺寸產生障礙。再者，為了將該第一晶粒分別耦合至該第二晶粒與一載體基板，該第一晶粒需要兩個凸塊。製造兩個凸塊需要相對複雜的製程。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10‧‧‧半導體裝置
100‧‧‧第一晶粒
102‧‧‧第一凸塊
104‧‧‧第二凸塊
106‧‧‧貫穿矽插塞
108‧‧‧基板
110‧‧‧晶種層
112‧‧‧隔離層
114‧‧‧主動層
140‧‧‧第二晶粒
142‧‧‧第三凸塊
200‧‧‧晶粒
202‧‧‧凸塊
206‧‧‧互連元件
208‧‧‧基板
210‧‧‧晶種層
214‧‧‧主動層
310‧‧‧第一黏著層
312‧‧‧載體基板
316‧‧‧第二黏著層
320‧‧‧第一晶粒
322‧‧‧第一互連元件
324‧‧‧第一主動層
326‧‧‧第一凸塊
350‧‧‧第二晶粒
352‧‧‧第二互連元件
354‧‧‧第二主動層
356‧‧‧第二凸塊
400‧‧‧基板
402‧‧‧主動層
404‧‧‧凸塊
407‧‧‧溝槽
408‧‧‧圖案化遮罩
409‧‧‧基板
410‧‧‧傳導層
412‧‧‧拋光的傳導層
414‧‧‧載體晶圓
416‧‧‧第一黏著層
418‧‧‧第二黏著層
H1‧‧‧高度
H2‧‧‧高度
S1‧‧‧第一表面
S2‧‧‧第二表面
S30‧‧‧第一表面
S32‧‧‧第二表面
T1‧‧‧距離
D10‧‧‧第一晶粒裝置
D12‧‧‧第二晶粒裝置
D20‧‧‧第一晶粒裝置
D22‧‧‧第二晶粒裝置
D50‧‧‧第一晶粒裝置
D52‧‧‧第二晶粒裝置
參閱詳細說明與申請專利範圍結合考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為示意圖，例示本揭露的比較例之半導體裝置。
圖2為示意圖，例示本揭露實施例的晶粒裝置。
圖3為示意圖，例示本揭露實施例的半導體裝置。
圖4至11為剖面示意圖，例示本揭露實施例製造半導體裝置的各種操作。
圖式所繪示之本揭露的實施例或範例係使用特定語言描述。應理解本揭露的範圍並不因而受到限制。對於該技藝中具有通常技術者而言，所述實施例之任何變化或修飾以及本揭露所述原理之任何其他應用係被視為正 常發生。在實施例中，元件符號可重複，即使具有相同的元件符號，但非要求一實施例的特徵應用於另一實施例。
應理解當元件被稱為「連接至」或「耦合至」另一元件時，可直接連接或耦合至另一元件，或是可有中間元件存在。
應理解雖然本文中可使用第一、第二、第三等語詞以描述各種元件、組件、區域、層、或區段，然而這些元件、組件、區域、層或區段並不受到這些語詞的限制。而是，這些語詞僅用以區別一元件、組件、區域、層或區段與另一區域、層或區段。因此，第一元件、組件、區域、層或區段可稱為第二元件、組件、區域、層或區段，而不脫離本揭露發明概念的教示。
本揭露所使用的用語僅為了描述特定範例實施例，而非用以限制本揭露概念。如本文所使用，除非特別說明，否則單數形式「一」與「該」亦用以包含複數形式。亦應理解在說明書中，「包括」一詞指定特徵、整體、步驟、操作、元件或組件的存在，但並不排除一或多個其他特徵、整體、步驟、操作、元件、組件或其群組的存在或增加。
圖1為示意圖，例示本揭露的比較例之半導體裝置10。參閱圖1，半導體裝置10包含第一晶粒裝置D10、第二晶粒裝置D12以及載體基板130。
第一晶粒裝置D10包含第一晶粒100、在第一晶粒100之第一表面上的第一凸塊102、以及在第一晶粒100之第二表面上的第二凸塊104。第二晶粒裝置D12包含第二晶粒140、在第二晶粒140之第一表面上的第三凸塊142。
第一晶粒100與第二晶粒140經由其第二凸塊104與第三凸塊142而接合在一起。在此方式中，第一晶粒100與第二晶粒140之間的第二凸塊104 與第三凸塊142距離為T1。距離T1為縮小半導體裝置10尺寸的障礙。例如，半導體裝置10的高度H1相對大。再者，為了將第一晶粒100耦合至第二晶粒140與載體基板130，第一晶粒100需要兩個凸塊，即第一凸塊102與第二凸塊104。製造兩個凸塊102與104需要相對複雜的製程。
第一晶粒100包含銅的貫穿矽插塞106以及晶種層110。貫穿矽插塞106作為第一晶粒100之主動層114的電性連接。若貫穿矽插塞106接觸第一晶粒100的基板108，則貫穿矽插塞106的銅會擴散至基板108中，造成基板108中的洩漏路徑。在此方式中，半導體裝置10可能功能異常。為了防止此問題，在貫穿矽插塞106與基板108之間放置第一晶粒100的隔離層112，或稱為襯墊，藉以分隔貫穿矽插塞106與基板108。製造隔離層112需要相對複雜的製程。第一晶粒100的內部結構與第二晶粒140的內部結構實質相同。因此，第二晶粒140具有與第一晶粒100相同的問題。
圖2為示意圖，例示本揭露實施例的晶粒裝置20。參閱圖2，晶粒裝置20包含晶粒200以及在晶粒200上的凸塊202。在一實施例中，晶粒200可為邏輯晶粒(例如中心處理單元、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、功率管理晶粒(例如功率管理積體電路(power management integrated circuit，PMIC)晶粒)、無線射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(digital signal processing，DSP)晶粒)、前端晶粒(例如類比前端(analog front-end，AFE)晶粒)、類似物、或其組合。
晶粒200包含主動層214與互連元件206。主動層214包含定義電晶體的通道的所在處的主動區(未繪示)。再者，主動層214另包含經配置用於電晶體的互連的互連，例如插塞、金屬-1層以及金屬-2層。
互連元件206作為主動層214的電性連接(或者，經配置以電性連接主動層214)。互連元件206接觸晶粒200中的基板208。在一實施例中，基板208包含晶圓，其上方形成裝置，例如半導體裝置或是其他裝置。在一些實施例中，基板208包含半導體基板，例如塊狀半導體基板。塊狀半導體基板包含元素半導體，例如矽或鍺；化合物半導體，如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦；或其組合。在一些實施例中，基板208包含多層基板，例如絕緣體覆矽(silicon-on-insulator，SOI)基板，其包含底部半導體層、包埋氧化物層(buried oxide layer，BOX)以及頂部半導體層。
在另一實施例中，基板208可為p型摻雜基板或n型摻雜基板，意指半導體基板208可經n型或p型雜質摻雜。基板208係由矽、砷化鎵、矽鍺、碳化矽、或其他已知用於半導體裝置製程的半導體材料所形成。雖然本揭露的實施例使用半導體基板，然而在其他的實施例中，可使用外延生長的半導體材料或是絕緣體覆矽(SOI)層作為基板208。
如圖2所示，顯然，互連元件206藉由晶粒200的晶種層210而與基板208分隔。然而，互連元件206的材料與晶種層210的材料實質相同。晶種層210應用於形成互連元件206。因此，晶種層210可被視為互連元件206的一部分，因而互連元件206可被視為接觸基板208。
再者，互連元件206為銅之外的材料。因此，雖然互連元件206接觸基板208，然而，未有銅擴散問題。因此，不需要用以分隔互連元件絕緣層206與基板208的絕緣層，例如襯墊。因此，半導體製程相對簡單。在一實施例中， 互連元件206的熔點低於銅的熔點。在一實施例中，互連元件206的材料包含錫(Sn)。
凸塊202獨立於晶粒200之外，作為主動層214的電性連接(或者，經配置以電性連接主動層214)。再者，凸塊202係位於晶粒200之第一表面S1內的主動層214上。更具體而言，凸塊202位於晶粒200的第一表面S1上，並且晶粒裝置20未有其他凸塊位於與第一表面S1對立之晶粒200的第二表面S2上，現有的半導體裝置中需要該其他凸塊。
圖3為示意圖，例示本揭露實施例之半導體裝置30。參閱圖3，半導體裝置30包含第一晶粒裝置D20、第二晶粒裝置D22、第一黏著層310、第二黏著層316以及載體基板312。第一晶粒裝置D20與第二晶粒裝置D22各自具有與圖2所示與所述之晶粒裝置20相同的結構與功能。
第一晶粒裝置D20經由第一黏著層310接合至載體基板312。第二晶粒裝置D22經由第二黏著層316接合至第一晶粒裝置D20。更具體而言，第二晶粒裝置D22位於第二黏著層316上，以及第二黏著層316依序位於第一晶粒裝置D20上。
第一晶粒裝置D20包含第一晶粒320與第一凸塊326。在一實施例中，第一晶粒320可為邏輯晶粒(例如中心處理單元、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、功率管理晶粒(例如功率管理積體電路(PMIC)晶粒)、無線射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(DSP)晶粒)、前端晶粒(例如類比前端(AFE)晶粒)、類似物、或其組合。
第一晶粒320包含第一主動層324與第一互連元件322。第一互連元件322作為第一主動層324的電性連接。在一實施例中，第一互連元件322的熔點低於銅的熔點。在一實施例中，第一互連元件322的材料包含錫(Sn)。
第一凸塊326獨立於第一晶粒320之外且位於第一晶粒320的第一主動層324上，作為第一主動層324的電性連接。第一凸塊326位於第一晶粒320的第一表面S30上。然而，第一晶粒裝置D20未有其他凸塊位於第一晶粒320的第二表面S32上以作為第一互連元件322的電性連接，該第二表面S32與第一表面S30對立。更具體而言，第一主動層324位於第一晶粒320的第一表面S30內。
第二晶粒裝置D22包含第二晶粒350與第二凸塊356。在一實施例中，第二晶粒350可為邏輯晶粒(例如中心處理單元、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等)、功率管理晶粒(例如功率管理積體電路(PMIC)晶粒)、無線射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(DSP)晶粒)、前端晶粒(例如類比前端(AFE)晶粒)、類似物、或其組合。
第二晶粒350包含第二主動層354與第二互連元件352。第二互連元件352作為第二主動層354的電性連接。在一實施例中，第二互連元件352的熔點低於銅的熔點。在一實施例中，第二互連元件352的材料包含錫(Sn)。
第二凸塊356獨立於第二晶粒350之外，作為第二主動層354的電性連接。第二凸塊356在第一互連元件322中受到第一互連元件322環繞，並且與第一互連元件322接觸。更具體而言，第二凸塊356的一部分受到第一互連元件322的環繞，並且第二凸塊356的剩餘部分受到第二黏著層316環繞。第一晶粒裝置D20與第二晶粒裝置D22之間的距離與第二黏著層316的厚度實質相等。為了說明， 圖3誇大繪示第二黏著層316的厚度。第二黏著層316極薄。據此，第一晶粒裝置D20與第二晶粒裝置D22之間沒有間隙存在。
在本揭露中，由於第一晶粒裝置D20的第二表面S32上不需要凸塊作為第一互連結構322的電性連接，以及由於第二晶粒裝置D22的第二凸塊356受到第一互連結構322環繞，因而半導體裝置30的高度H2相對小。因此，半導體裝置30相對緊密。
再者，如圖2相關說明所述，在一實施例中，第一互連元件322與第二互連元件352各自為非銅的材料。因此，雖然第一互連元件322與第二互連元件352分別接觸第一晶粒裝置D20與第二晶粒裝置D22的基板208，不會發生銅擴散問題。因此，不需要絕緣層分隔第一互連元件322與基板208以及分隔第二互連元件352與基板208。
圖4至圖11為剖面示意圖，例示本揭露實施例製造半導體裝置的各個操作。參閱圖4，提供基板400。接著，在基板400中與基板400上，形成主動層402。
參閱圖5，形成凸塊404於主動層402上。參閱圖6，使用圖案化遮罩408作為遮罩以圖案化基板400，而形成具有溝槽407的基板409。因此，暴露主動層402的一部分。
參閱圖7，在所得基板409與主動層402之暴露部分上，共形形成晶種層408。在一實施例中，在形成晶種層408之前，藉由例如沉積操作，在所得基板409與主動層402的暴露部分上，共形形成絕緣層。接著，在該絕緣層上，形成晶種層408。
參閱圖8，例如，藉由無電鍍或電鍍的鍍操作，在晶種層408上，形成傳導層410。參閱圖9，藉由拋光該傳導層410，在溝槽407中以及在主動層402上方，形成拋光的傳導層412。再者，在所得基板409之表面上的晶種層的一部分亦被 移除。所得結構如圖9所示，包含本揭露之晶粒裝置的結構。據此，藉由進行圖4至圖9所示與所述之操作，分別得到第一晶粒裝置D50與第二晶粒裝置D52。
參閱圖10，提供載體晶圓414。在載體晶圓414上，形成第一黏著層416，以及在第一晶粒裝置D50之所得基板409與拋光的傳導層412上，形成第二黏著層418。參閱圖11，第二晶粒裝置D52的凸塊404插入至第一晶粒裝置D50之拋光的傳導層412中。
在一實施例中，參閱圖10，藉由熔化拋光的傳導層412，形成熔化且拋光的傳導層。拋光的傳導層412之熔點低於銅的熔點。更具體而言，在製造半導體裝置的腔室中，溫度升高至高於拋光的傳導層412之熔點但低於銅的熔點。而後，第二晶粒裝置D52的凸塊404插入至第一晶粒裝置D50之熔化且拋光的傳導層中。
在本揭露中，圖2所示的互連元件206係非銅的材料製成。因此，雖然互連元件206接觸基板208，並不會發生銅擴散問題。因此，不需要絕緣層分隔互連元件206與基板208，簡化了半導體製程。
再者，在本揭露中，由於第一晶粒裝置D20的第二表面S32上不需要凸塊作為第一互連結構322的電性連接，並且由於第二晶粒裝置D22的第二凸塊356插入至第一互連結構322中，因此，半導體裝置30的高度H2相對小，半導體裝置30因而相對緊密。
本揭露的一些實施例提供一種晶粒裝置。該晶粒裝置包含一晶粒及一凸塊。該晶粒具有一主動層及一互連元件。該互連元件經配置以電性連接該主動層且接觸該晶粒中的一基板。該凸塊獨立於該晶粒之外，經配置以電性連接該主動層。
本揭露的一些實施例提供一種半導體裝置。該半導體裝置包含一第一晶粒裝置及一第二晶粒裝置。該第一晶粒裝置包含具有一第一主動層的一第一晶粒，以及一第一互連元件。該第一互連元件經配置以電性連接該第一主動層。該第二晶粒裝置包含具有一第二主動層的一第二晶粒，以及一凸塊。該凸塊獨立於該第二晶粒之外，經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件環繞。
本揭露的一些實施例提供一種方法，包含藉由進行一操作兩次，得到一第一晶粒裝置與一第二晶粒裝置，該操作包含形成一主動層於一基板中且於該基板上；形成一凸塊於該主動層上；形成一溝槽於該基板中，暴露該主動層；以及形成一拋光的傳導層於該溝槽中且於該主動層上；以及將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置的該拋光的傳導層中。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。

Claims (19)

  1. 一種晶粒裝置，包括：一晶粒，包含：一主動層；以及一互連元件，經配置以電性連接該主動層且接觸該晶粒中的一基板；以及一凸塊，獨立於該晶粒之外且經配置以電性連接該主動層；其中該互連元件的一熔點低於銅的一熔點。
  2. 一種晶粒裝置，包括：一晶粒，包含：一主動層；以及一互連元件，經配置以電性連接該主動層且接觸該晶粒中的一基板；以及一凸塊，獨立於該晶粒之外且經配置以電性連接該主動層；其中該互連元件的一材料包含錫(Sn)。
  3. 一種晶粒裝置，包括：一晶粒，包含：一主動層；以及一互連元件，經配置以電性連接該主動層且接觸該晶粒中的一基板；以及一凸塊，獨立於該晶粒之外且經配置以電性連接該主動層；其中該凸塊位在該晶粒的該主動層上。
  4. 如請求項3所述之晶粒裝置，其中該凸塊位在該晶粒的一第一表面上，以及該晶粒裝置未有其他凸塊位於該晶粒的一第二表面上，該第二表面與該第一表面對立。
  5. 如請求項3所述之晶粒裝置，其中該主動層位在該晶粒的該第一表面內。
  6. 一種半導體裝置，包括：一第一晶粒裝置，包含：一第一晶粒，包含：一第一主動層；以及一第一互連元件，經配置以電性連接該第一主動層；以及一第二晶粒裝置，包含：一第二晶粒，包含：一第二主動層；以及一凸塊，獨立於該第二晶粒之外且經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件的環繞；一黏著層，藉以使得該第二晶粒裝置接合至該第一晶粒裝置。
  7. 如請求項6所述之半導體裝置，其中該凸塊接觸該第一互連元件。
  8. 如請求項6所述之半導體裝置，其中該第二晶粒裝置位於該黏著層上，並且該黏著層位於該第一晶粒裝置上。
  9. 如請求項6所述之半導體裝置，其中該第一晶粒裝置與該第二晶粒裝置之間的一距離與該黏著層的一厚度實質相同。
  10. 如請求項6所述之半導體裝置，其中該凸塊的一部分受到該第一互連元件環繞，以及該凸塊的剩餘部分受到該黏著層環繞。
  11. 如請求項6所述之半導體裝置，其中該凸塊為該第二凸塊，該第一晶粒裝置另包含：一第一凸塊，獨立於該第一晶粒之外，經配置用於該第一主動層的電性連接。
  12. 一種半導體裝置，包括：一第一晶粒裝置，包含：一第一晶粒，包含：一第一主動層；以及一第一互連元件，經配置以電性連接該第一主動層；以及一第二晶粒裝置，包含：一第二晶粒，包含：一第二主動層；以及一凸塊，獨立於該第二晶粒之外且經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件的環繞；其中該第一互連元件的一熔點低於銅的熔點。
  13. 一種半導體裝置，包括：一第一晶粒裝置，包含：一第一晶粒，包含：一第一主動層；以及一第一互連元件，經配置以電性連接該第一主動層；以及一第二晶粒裝置，包含：一第二晶粒，包含：一第二主動層；以及一凸塊，獨立於該第二晶粒之外且經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件的環繞；其中該第一互連元件的一材料包含錫(Sn)。
  14. 一種半導體裝置，包括：一第一晶粒裝置，包含：一第一晶粒，包含：一第一主動層；以及一第一互連元件，經配置以電性連接該第一主動層；以及一第二晶粒裝置，包含：一第二晶粒，包含：一第二主動層；以及一凸塊，獨立於該第二晶粒之外且經配置以電性連接該第二主動層，其中該凸塊受到該第一互連元件的環繞；其中該第一凸塊位於該第一晶粒的一第一表面上，以及該第一晶粒裝置未有其他凸塊於該第一晶粒的一第二表面上，該第二表面與該第一表面對立。
  15. 如請求項14所述之半導體裝置，其中該第一主動層位於該第一晶粒的該第一表面內。
  16. 如請求項14所述之半導體裝置，其中該第一凸塊位於該第一晶粒的該第一主動層上。
  17. 一種半導體裝置之製造方法，包括：藉由進行一操作兩次，得到一第一晶粒裝置以及一第二晶粒裝置，該操作包含：形成一主動層於一基板中且於該基板上；形成一凸塊於該主動層上；形成一溝槽於該基板中，暴露該主動層；以及形成一拋光的傳導層於該溝槽中且於該主動層上；以及將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該拋光的傳導層中。
  18. 如請求項17所述之製造方法，另包括：藉由熔化該拋光的傳導層，形成一熔化且拋光的傳導層，其中該拋光的傳導層的一熔點低於銅的熔點。
  19. 如請求項17所述之製造方法，其中將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該拋光的傳導層中包含：將該第二晶粒裝置的該凸塊插入至該第一晶粒裝置之該熔化且拋光的傳導層中。
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