TWI500155B - 晶片封裝體及其形成方法 - Google Patents
晶片封裝體及其形成方法 Download PDFInfo
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Description
本發明係有關於晶片封裝體,且特別是有關於金氧半場效電晶體晶片封裝體。
晶片封裝製程是形成電子產品過程中之一重要步驟。晶片封裝體除了將晶片保護於其中,使免受外界環境污染外,還提供晶片內部電子元件與外界之電性連接通路。
使晶片封裝體之尺寸縮小化,並進一步提升晶片封裝體之效能成為重要課題。
本發明一實施例提供一種晶片封裝體,包括:一半導體基底,具有一第一表面及相反之一第二表面;一汲極區,位於該半導體基底中;一源極區,位於該半導體基底中;一閘極,位於該半導體基底之上或至少部分埋於該半導體基底之中,其中該閘極與該半導體基底之間隔有一閘極介電層;一汲極導電結構,設置於該半導體基底之該第一表面上,且電性連接該汲極區;一源極導電結構,設置於該半導體基底之該第二表面上,且電性連接該源極區;以及一閘極導電結構,設置於該半導體基底之該第一表面上,且電性連接該閘極。
本發明一實施例提供一種晶片封裝體的形成方法,包括:提供一半導體基底,具有一第一表面及一第二表面,其中該半導體基底中具有一汲極區及一源極區,且其中一閘極位於該半導體基底之上或至少部分埋於該半導體基底之中,該閘極與該半導體基底之間隔有一閘極介電層;於該半導體基底之該第一表面上形成一汲極導電結構,其中該汲極導電結構電性連接該汲極區;於該半導體基底之該第二表面上形成一源極導電結構,其中該源極導電結構電性連接該源極區;以及於該半導體基底之該第一表面上形成一閘極導電結構,其中該閘極導電結構電性連接該閘極。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是,本發明提供許多可供應用的發明概念,其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式,非用以限制本發明之範圍。此外,在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明,不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者,當述及一第一材料層位於一第二材料層上或之上時,包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝金氧半場效電晶體晶片,例如是功率模組晶片。然其應用不限於此,例如在本發明之晶片封裝體的實施例中,其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components),例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System;MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package;WSP)製程對影像感測元件、發光二極體(light-emitting diodes;LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率晶片模組(power IC modules)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後,再予以切割成獨立的封裝體,然而,在一特定實施例中,例如將已分離之半導體晶片重新分布在一承載晶圓上,再進行封裝製程,亦可稱之為晶圓級封裝製程。另外,上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓,以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
第1A-1R圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。如第1A圖所示,提供半導體基底100,其具有表面100a及表面100b。半導體基底100例如可為矽基底,如矽晶圓。在其他實施例中,半導體基底100亦可為其他適合的半導體材料,例如可為鍺、矽鍺、碳化矽、砷化鎵、或其相似物等。
在半導體基底100中可預先形成有源極區106及汲極區。在一實施例中,半導體基底100之導電型式可為N型或P型,一般而言,以N型之半導體基底居多。以導電型式為N型之半導體基底100為例,其可為摻雜有N型摻質之矽基底。半導體基底100中之摻質種類與摻雜濃度可為不均一的。例如,半導體基底100下部分(靠近表面100b之部分)所摻雜之N型摻質的種類與摻雜濃度可不同於上部分(靠近表面100a之部分)中之N型摻質種類與摻雜濃度。半導體基底100本身可形成一汲極區。因此,標號100亦可代表汲極區(指半導體基底100中未形成源極區或其他摻雜區之部分)。
在一實施例中,半導體基底100可包括摻雜區(未顯示),其可自表面100b或接近表面100b處朝表面100a延伸。摻雜區之導電型式不同於半導體基底100。例如,當半導體基底100為N型基底時,摻雜區之導電型式為P型,反之亦然。
在一實施例中,半導體基底100包括源極區106,其可位於摻雜區中。源極區106之導電型式與半導體基底100相同,例如皆為N型。在一實施例中,源極區106自表面100b或接近表面100b處朝表面100a延伸,且可部分被摻雜區圍繞。在第1A圖中,為簡化與清楚化圖式,僅顯示出源極區106。
在一實施例中,半導體基底100之表面100b上設置有介電層104。介電層104中可形成有源極電極102S,其可透過形成於介電層104及/或半導體基底100中之導電線路而電性連接至源極區106。例如,在第1A圖之實施例中,介電層104中形成有介層窗結構(via structure)103,其電性連接源極電極102S與源極區106。
在一實施例中,介電層104中還可形成有閘極102G,其例如可為(但不限於)一多晶矽層。閘極102G與半導體基底100之間所間隔之介電層104可用作閘極介電層。此外,在另一實施例中,閘極與閘極介電層可為埋入式結構,其可形成於基底之凹穴中。在此情形下,閘極102G至少部分埋於半導體基底100之中。
接著,如第1A圖所示,可於源極電極102S上形成源極導電墊108S,並可於閘極102G上選擇性形成閘極導電墊108G。源極電極102S與源極導電墊108S可共同作為與源極區106電性連接之源極導電結構,其係設置於半導體基底100之表面100b上。
接著,如第1B圖所示,可於半導體基底100之表面100b上形成保護層110。保護層110具有至少一開口,露出部分的源極電極102S(即,露出部分的源極導電結構)。在一實施例中,開口中可更包括一保護層凸塊,可依設計需求於保護層110之圖案化過程中形成。所露出之源極導電結構可用以與其他導電結構電性連接。在一實施例中,可選擇性於露出之源極導電結構上形成導電凸塊或銲球。在一實施例中,保護層110可覆蓋閘極102G。
接著,如第1C圖所示,可選擇性於半導體基底100之表面100b上設置承載基底112。在一實施例中,可透過黏著層114而將半導體基底100固定於承載基底112上,其中黏著層114可位於保護層110與承載基底112之間。在另一實施例中,保護層110可選用具黏性之材質。在此情形下,可不形成黏著層114,並直接使承載基底112與保護層110直接接觸而使半導體基底100固定於承載基底112之上。承載基底112之設置有助於後續製程之進行。
接著,如第1D圖所示,可選擇性薄化半導體基底100。例如,可以承載基底112為支撐,自半導體基底100之表面100a將半導體基底100薄化至適合的厚度。適合的薄化製程例如是(但不限於)機械研磨、化學機械研磨、及/或其他相似製程。
接著,如第1E圖所示,於半導體基底100之表面100a上形成遮罩層116。遮罩層116具有開口116a,其露出部分的半導體基底100。開口116a之位置可大抵位於閘極102G之正上方。
接著,如第1F圖所示,自半導體基底100之表面100a移除部分的半導體基底100以形成朝表面100b延伸之孔洞118。例如,可以蝕刻之方式移除半導體基底100以形成孔洞118。孔洞118可露出閘極102G。遮罩層116可保護其下方之半導體基底100於形成孔洞118的製程期間免於受到傷害。
接著,如第1G圖所示,例如以氣相沉積法或塗佈法於孔洞118之側壁上形成絕緣層120。絕緣層120可能會覆蓋在孔洞118之底部上,並延伸於半導體基底100之表面100a上。在後續製程中,將於孔洞118中形成與閘極102G電性連接之導電層,因此可透過圖案化製程移除孔洞118底部上之絕緣層120以使閘極102G露出。孔洞118底部上之絕緣層120可在於孔洞118中形成絕緣層120後,並於形成導電層前的任一適合時間點移除。
接著,如第1H-1I圖所示,進行絕緣層120之圖案化製程以露出半導體基底100之部分表面100a(即,露出汲極區)。如第1H圖所示,可於半導體基底100之表面100a上設置遮罩層122。遮罩層122具有至少一開口122a,其露出部分的絕緣層120。接著,移除所露出之絕緣層120,如第1I圖所示。例如,可採用蝕刻製程移除所露出之絕緣層120,其中由遮罩層122所覆蓋之絕緣層120可大抵免於被蝕刻。在一實施例中,可選用乾膜作為遮罩層122。乾膜大抵不會填入孔洞118中,可免去後續的孔洞清洗製程。
接著,如第1J圖所示,移除遮罩層122,以及移除孔洞118之底部上的部分絕緣層120以使閘極102G露出。接著,於半導體基底100之表面100a上形成晶種層124,其與所露出之半導體基底100(即,汲極區)電性接觸。晶種層124還進一步沿著孔洞118之側壁延伸至孔洞118之底部而與閘極102G電性接觸。
接著,如第1K圖所示,於晶種層124之部分表面上形成遮罩層126,其下方所覆蓋之晶種層124將於後續製程中移除。遮罩層126具有開口,其至少露出汲極區上方之晶種層124與孔洞118中之晶種層124。
接著,如第1L圖所示,進行電鍍製程以於所露出之晶種層124上電鍍沉積導電材料而形成導電層124a。如第1M圖所示,接著移除遮罩層126,並將原由遮罩層126所覆蓋之晶種層移除以形成汲極導電層124b與閘極導電層124c。可例如以蝕刻方式移除由遮罩層126所覆蓋之晶種層,因此原為導電層124a之汲極導電層124b與閘極導電層124c之厚度將因蝕刻製程而略薄於原本導電層124a之厚度。
應注意的是,雖然上述實施例中之導電層係以電鍍方式進行,然本發明實施例不限於此。在其他實施例中,亦可採用氣相沉積法或塗佈法形成導電材料層,並透過微影及蝕刻製程將之圖案化為所需之導電層。在此情形下,可不需形成晶種層。
此外,雖然上述實施例中,孔洞118之底部上的絕緣層120係在移除汲極區上之部分的絕緣層120之後才移除,但本發明實施例不限於此。例如,可先移除孔洞118之底部上的絕緣層120,接著才移除汲極區上之部分的絕緣層120。或者,在一實施例中,可同時移除孔洞118之底部上的絕緣層120與汲極區上之部分的絕緣層120。
接著,如第1N圖所示,選擇性分別於汲極導電層124b與閘極導電層124c上形成凸塊下金屬層128D與128G,其中凸塊下金屬層128D與汲極導電層124b係用作汲極區之汲極導電結構,而凸塊下金屬層128G與閘極導電層124c係用作閘極102G之閘極導電結構。接著,於半導體基底100之表面100a上形成保護層130,其具有開口,分別露出部分的凸塊下金屬層128D與128G。即,保護層130分別具有至少一露出汲極導電結構之開口與至少一露出閘極導電結構之開口。在一實施例中,露出汲極導電結構之開口中可更包括一保護層凸塊,可依設計需求於保護層130之圖案化過程中形成。
如第1O圖所示,接著可選擇性透過黏著層134而於半導體基底100之表面100a上設置承載基底132。接著,如第1P圖所示,移除半導體基底100之表面100b下方的黏著層114與承載基底112。移除承載基底112之後,設置於半導體基底100之表面100a上的承載基底132可用作移動半導體基底100時之操作基底。
如第1Q圖所示,接著可將半導體基底100設置於薄膜框載體140,並移除先前所設置之承載基底132,其中半導體基底100之表面100b面向薄膜框載體140。例如,在一實施例中,半導體基底100為半導體晶圓,其中形成有多個金氧半場效電晶體,彼此間間隔有預定切割道。在此情形下,可進一步沿著切割道切割半導體基底100以形成複數個個別的晶片封裝體以供利用。個別的晶片封裝體可自薄膜框載體140取下以供利用,如第1R圖所示。
本發明實施例可有許多其他變化。第2A-2C圖舉例顯示根據本發明實施例之晶片封裝體的剖面圖,其中相同或相似之標號用以標示相同或相似之元件。
如第2A圖所示,此實施例與第1圖實施例主要差異在於第2A圖實施例包括承載基底212而未將其移除。保留承載基底212有助於增加晶片封裝體的結構強度。此外,在一實施例中,可將承載基底212圖案化以形成露出源極導電結構之開口212a。在一實施例中,開口212a中可更包括一保護層凸塊,可依設計需求於保護層110之圖案化過程中形成。在一實施例中,保護層130之開口中可更包括一保護層凸塊,可依設計需求於保護層130之圖案化過程中形成。
如第2B圖所示,此實施例與第1圖實施例主要差異在於第2B圖實施例更包括形成於半導體基底100之表面100b上之凸塊下金屬層208S。在一實施例中,凸塊下金屬層208S延伸進入保護層110之開口中而電性連接至源極導電結構。凸塊下金屬層208S例如係順應性位於保護層110之上。凸塊下金屬層208S可延伸於保護層110之下表面上而增加源極導電結構與其他電子構件電性接觸之面積。在一實施例中,保護層110之開口中可更包括一保護層凸塊,可依設計需求於保護層110之圖案化過程中形成。在此情形下,凸塊下金屬層208S可順應性覆蓋於保護層凸塊上。在一實施例中,保護層130之開口中可更包括一保護層凸塊,可依設計需求於保護層130之圖案化過程中形成。
如第2C圖所示,此實施例與第2A圖實施例主要差異在於第2C圖實施例更包括形成於半導體基底100之表面100b上之凸塊下金屬層208S。在一實施例中,凸塊下金屬層208S延伸進入承載基底212之開口及保護層110之開口中而電性連接至源極導電結構。凸塊下金屬層208S例如係順應性位於承載基底212之上。凸塊下金屬層208S可延伸於承載基底212之下表面上而增加源極導電結構與其他電子構件電性接觸之面積。在一實施例中,保護層110之開口中可更包括一保護層凸塊,可依設計需求於保護層110之圖案化過程中形成。在此情形下,凸塊下金屬層208S可順應性覆蓋於保護層凸塊上。在一實施例中,保護層130之開口中可更包括一保護層凸塊,可依設計需求於保護層130之圖案化過程中形成。
第3A及3B圖分別顯示根據本發明一實施例之晶片封裝體之相反表面的上視示意圖,其中相同或相似之標號用以標示相同或相似之元件。第3A圖例如是對應至第2B圖實施例之下表面,而第3B圖例如是對應至第2B圖實施例之上表面,其分別顯示連接至源極區、汲極區、及閘極之金屬層208S、128D、及128G之可能的分佈方式,其中金屬層128G係透過形成於孔洞118中之穿基底導電結構而電性連接至閘極。
在本發明實施例中,透過孔洞與導電層所構成之穿基底導電結構可將閘極導電結構與汲極導電結構設置於半導體基底之同一側上,有利於與其他電子構件整合,可縮小電子產品之尺寸,並可縮短電性訊號的傳遞距離而提升電子產品之效能。例如,在一實施例中,可堆疊兩晶片封裝體,其中下方之晶片封裝體的汲極導電結構可電性接觸上方之晶片封裝體的源極導電結構。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100...基底
100a、100b...表面
102S...源極電極
102G...閘極
103...介層窗結構
104...介電層
106...源極區
108S、108G...導電墊
110...保護層
112...承載基底
114...黏著層
116...遮罩層
116a...開口
118...孔洞
120...絕緣層
122...遮罩層
122a...開口
124...晶種層
124a、124b、124c...導電層
126...遮罩層
128D、128G...金屬層
130...保護層
132...承載基底
134...黏著層
140...薄膜框載體
208S...金屬層
212...承載基底
212a...開口
第1A-1R圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2A-2C圖顯示根據本發明實施例之晶片封裝體的剖面圖。
第3A及3B圖分別顯示根據本發明一實施例之晶片封裝體之相反表面的上視示意圖。
100...基底
100a、100b...表面
102S...源極電極
102G...閘極
103...介層窗結構
104...介電層
106...源極區
108S、108G...導電墊
110...保護層
118...孔洞
120...絕緣層
124b、124c...導電層
128D、128G...金屬層
130...保護層
Claims (20)
- 一種晶片封裝體,包括:一半導體基底,具有一第一表面及相反之一第二表面;一汲極區,位於該半導體基底中;一源極區,位於該半導體基底中;一閘極,位於該半導體基底之上或至少部分埋於該半導體基底之中,其中該閘極與該半導體基底之間隔有一閘極介電層;一汲極導電結構,設置於該半導體基底之該第一表面上,且電性連接該汲極區;一源極導電結構,設置於該半導體基底之該第二表面上,且電性連接該源極區;以及一閘極導電結構,設置於該半導體基底之該第一表面上,且電性連接該閘極。
- 如申請專利範圍第1項所述之晶片封裝體,更包括:一孔洞,自該半導體基底之該第一表面朝該第二表面延伸;一導電層,位於該孔洞之一側壁上,其中該導電層電性連接該閘極與該閘極導電結構;以及一絕緣層,位於該導電層與該半導體基底之間。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一第一保護層,設置於該半導體基底之該第一表面上,其中該第一保護層具有至少一第一開口及至少一第二開口,分別露出部分的該汲極導電結構及部分的該閘極導電結構。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一第二保護層,設置於該半導體基底之該第二表面上,其中該第二保護層具有至少一開口,露出部分的該源極導電結構。
- 如申請專利範圍第4項所述之晶片封裝體,更包括一凸塊下金屬層,順應性位於該第二保護層之上,且延伸進入該開口而電性連接該源極導電結構。
- 如申請專利範圍第4項所述之晶片封裝體,更包括一承載基底,設置於該第二保護層之上。
- 如申請專利範圍第6項所述之晶片封裝體,其中該承載基底具有至少一開口,露出部分的該源極導電結構。
- 如申請專利範圍第6項所述之晶片封裝體,更包括一凸塊下金屬層,順應性位於該承載基底之上,且延伸進入該第二保護層之該開口而電性連接該源極導電結構。
- 如申請專利範圍第1項所述之晶片封裝體,更包括一承載基底,設置於該半導體基底之該第二表面上。
- 如申請專利範圍第9項所述之晶片封裝體,其中該承載基底具有至少一開口,露出部分的該源極導電結構。
- 一種晶片封裝體的形成方法,包括:提供一半導體基底,具有一第一表面及一第二表面,其中該第一表面與該第二表面互為相反表面,其中該半導體基底中具有一汲極區及一源極區,且其中一閘極位於該半導體基底之上或至少部分埋於該半導體基底之中,該閘極與該半導體基底之間隔有一閘極介電層;於該半導體基底之該第一表面上形成一汲極導電結構,其中該汲極導電結構電性連接該汲極區;於該半導體基底之該第二表面上形成一源極導電結構,其中該源極導電結構電性連接該源極區;以及於該半導體基底之該第一表面上形成一閘極導電結構,其中該閘極導電結構電性連接該閘極。
- 如申請專利範圍第11項所述之晶片封裝體的形成方法,更包括:自該半導體基底之該第一表面移除部分的該半導體基底以形成朝該第二表面延伸之一孔洞;於該孔洞之一側壁上形成一絕緣層;以及於該孔洞中之該絕緣層上形成一導電層,其中該導電層電性連接該閘極與該閘極導電結構。
- 如申請專利範圍第12項所述之晶片封裝體的形成方法,其中在形成該孔洞的步驟之前,更包括自該半導體基底之該第一表面薄化該半導體基底。
- 如申請專利範圍第13項所述之晶片封裝體的形成方法,其中在薄化該半導體基底的步驟之前,更包括於該半導體基底之該第二表面上設置一承載基底。
- 如申請專利範圍第14項所述之晶片封裝體的形成方法,更包括: 在於該孔洞中形成該導電層之後,於該半導體基底之該第一表面上設置一第二承載基底;在設置該第二承載基底之後,移除該承載基底;將該半導體基底設置於一薄膜框載體上,其中該半導體基底之該第二表面面向該薄膜框載體;以及移除該第二承載基底。
- 如申請專利範圍第14項所述之晶片封裝體的形成方法,更包括將該承載基底圖案化以形成露出部分的該源極導電結構之一開口。
- 如申請專利範圍第16項所述之晶片封裝體的形成方法,更包括於該承載基底上順應性形成一凸塊下金屬層,其中該凸塊下金屬層延伸進入該承載基底之該開口而電性連接至該源極導電結構。
- 如申請專利範圍第11項所述之晶片封裝體的形成方法,更包括於該半導體基底之該第二表面上形成一保護層,其中該保護層具有露出部分的該源極導電結構之一開口。
- 如申請專利範圍第18項所述之晶片封裝體的形成方法,更包括於該半導體基底之該第二表面上形成一凸塊下金屬層,其中該凸塊下金屬層延伸進入該保護層之該開口中而電性連接至該源極導電結構。
- 如申請專利範圍第11項所述之晶片封裝體的形成方法,更包括於該半導體基底之該第一表面上形成一保護層,其中該保護層具有至少一第一開口及至少一第二開口,分別露出部分的該汲極導電結構及部分的該閘極導電結構。
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TWI485818B (zh) * | 2011-06-16 | 2015-05-21 | Xintec Inc | 晶片封裝體及其形成方法 |
US8987851B2 (en) | 2012-09-07 | 2015-03-24 | Mediatek Inc. | Radio-frequency device package and method for fabricating the same |
US20150255499A1 (en) * | 2014-03-07 | 2015-09-10 | Xintec Inc. | Chip package and method of fabricating the same |
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US10109663B2 (en) * | 2015-09-10 | 2018-10-23 | Xintec Inc. | Chip package and method for forming the same |
CN107564963A (zh) * | 2017-08-14 | 2018-01-09 | 深圳市芯电元科技有限公司 | 倒置栅极结构的功率mosfet及制作方法 |
US10373883B2 (en) * | 2017-10-26 | 2019-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device and method of manufacturing the same |
CN110943056B (zh) | 2018-09-21 | 2021-11-23 | 联华电子股份有限公司 | 具有散热结构的高电阻晶片及其制作方法 |
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