TWI708332B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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TWI708332B
TWI708332B TW107143108A TW107143108A TWI708332B TW I708332 B TWI708332 B TW I708332B TW 107143108 A TW107143108 A TW 107143108A TW 107143108 A TW107143108 A TW 107143108A TW I708332 B TWI708332 B TW I708332B
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semiconductor device
solder resist
resin
wiring
opening area
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TW107143108A
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TW202011537A (zh
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齋藤伸治
小野美隆
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日商東芝記憶體股份有限公司
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Abstract

本發明之實施形態提供一種可靠性較高之半導體裝置及半導體裝置之製造方法。 實施形態之半導體裝置具備：基板1，其配置有配線2；半導體元件5，其配置於基板1上；第1阻焊劑3，其配置於配線2上，具有開口區域A，且配線2之一部分面朝開口區域A；接合線6，其於開口區域A，將配線2與半導體元件5連接；及第2阻焊劑4，其覆蓋面朝開口區域A之配線2。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施形態係關於一種半導體裝置及半導體裝置之製造方法。
先前，已知關於在BGA(Ball Grid Array，球柵陣列)等半導體封裝中搭載有半導體元件之基板之導線接合部分，熱應力集中於Cu配線(接合墊)、阻焊劑、接合線、樹脂等不同材料相交之部分。根據評估解析得知，若為了電容增加而使樹脂密封型半導體裝置之厚度與矽總厚度增加，則有TCT(Temperature Cycle Test，溫度循環測試)之可靠性惡化之傾向，認為其原因在於Cu配線發生斷線。
本發明之實施形態提供一種可靠性較高之半導體裝置及半導體裝置之製造方法。
實施形態之半導體裝置具備：基板，其設置有配線；半導體元件，其設置於基板上；第1樹脂，其設置於基板上，且形成有開口區域；電極部，其係配線自第1樹脂露出之部分；導線，其將電極部與半導體元件連接；以及第2樹脂，其覆蓋電極部，且於導線附近之上表面低於導線之最大高度。
又，較理想為，電極部之整個表面由導線與第2樹脂所覆蓋。
又，較理想為，具備絕緣性樹脂，該絕緣性樹脂配置於半導體元件、第1樹脂及第2樹脂上，且含有填料。
又，較理想為，第1樹脂之一部分與第2樹脂之一部分積層。
又，較理想為，開口區域由第2樹脂填充。
又，較理想為，在半導體元件與第2樹脂之間具有間隙。
又，較理想為，第2樹脂覆蓋半導體元件。
又，於將第1樹脂之熱膨脹係數設為β1(/K)，將第2樹脂之熱膨脹係數設為β2(/K)時，(2×|β1-β2|/(β1+β2))×100之值較理想為5.0以下，更理想為3.0以下。
根據本發明之實施形態，可提供一種可靠性較高之半導體裝置及半導體裝置之製造方法。
1:基板
2:配線
3:第1阻焊劑
4:第2阻焊劑
5:半導體元件
6:接合線
7:黏晶
8:焊料球
9:絕緣膜
10:絕緣性樹脂
11:焊盤
100:半導體裝置
101:半導體裝置
102:半導體裝置
103:半導體裝置
104:半導體裝置
105:半導體裝置
106:半導體裝置
107:半導體裝置
108:半導體裝置
200:半導體裝置
A:開口區域
圖1係表示第1實施形態中之半導體裝置之構成之一例的剖視圖。
圖2係說明第1實施形態中之半導體裝置之構成之圖，且係用以說明第1實施形態與比較例中之階梯區域之接點及支柱之配置構成之一例的俯視圖。
圖3係第1實施形態中之半導體裝置之步驟圖。
圖4係第1實施形態中之半導體裝置之步驟圖。
圖5係表示第2實施形態中之半導體裝置之構成之一例的剖視圖。
圖6係表示第3實施形態中之半導體裝置之構成之一例的剖視圖。
圖7係表示第4實施形態中之半導體裝置之構成之一例的剖視圖。
圖8係表示第5實施形態中之半導體裝置之構成之一例的剖視圖。
圖9係表示第6實施形態中之半導體裝置之構成之一例的剖視圖。
圖10係表示第7實施形態中之半導體裝置之構成之一例的剖視圖。
圖11係表示第8實施形態中之半導體裝置之構成之一例的剖視圖。
以下，於實施形態中，對作為半導體封裝之半導體裝置之內部構造進行說明。以下，使用圖式進行說明。
(第1實施形態)
圖1係表示第1實施形態中之半導體裝置之構成之一例的剖視圖。圖2係說明第1實施形態中之半導體裝置之構成之圖。於圖1及圖2中，第1實施形態中之半導體裝置100具備：基板1，其配置有配線2；半導體元件5，其配置於基板1上；第1阻焊劑3，其配置於配線2上，具有開口區域A，且配線2之一部分面朝開口區域A；接合線6，其於開口區域A，將配線2與半導體元件5連接；第2阻焊劑4，其覆蓋面朝開口區域A之配線2；以及絕緣性樹脂10。在半導體元件5與基板1之間配置有黏晶7。於基板1之與半導體元件5側為相反側之面，配置有複數個焊料球8。於基板1之通孔內配置有絕緣膜9。基板1之半導體元件5側之面由絕緣性樹脂10密封。於圖1中示出BGA(Ball Grid Array)型半導體裝置。
基板1係配置有Cu等配線2之配線基板。於基板1配置有半導體元件5。於基板1之一面配置有半導體元件5，於與一面為相反側之另一面配置有作為半導體裝置100之外部端子之焊料球8。配線2將半導體元件5與焊料球8電性連接。於基板1中包含貫通基板1之通孔，於通孔內配 置有配線2與絕緣膜9，藉由配線2將基板1之正面及背面電性連接。基板1並不特別限定於玻璃基板或陶瓷基板等。
第1阻焊劑3係配置於基板1上及配線2上之絕緣膜。第1阻焊劑3具有開口區域A。配線2之一部分面朝開口區域A，且於開口區域A，配線2與半導體元件5藉由Au導線等接合線6而連接。面朝開口區域A之配線2係未設置阻焊劑之被稱為所謂之接合墊(電極部)之部分。接合墊係配線2中於開口區域A露出而未被第1阻焊劑3覆蓋之部分。第1阻焊劑3包含熱固性樹脂或光硬化樹脂。第1阻焊劑3較佳為由不含填料之材料構成。
第2阻焊劑4係配置於基板1上及配線2上之絕緣膜。圖2係省略了接合線6及絕緣性樹脂10之俯視圖。開口區域A係以粗實線包圍之區域，且係靠近成為半導體裝置100之主要熱源之半導體元件的區域。第2阻焊劑4覆蓋面朝開口區域A之配線2即電極部。第2阻焊劑4於先前之半導體裝置中配置於配置有密封劑(本案中提及之絕緣性樹脂10)之位置。第2阻焊劑4包含熱固性樹脂或光固性樹脂。第2阻焊劑4較佳為由不含填料之材料構成。於本實施形態以後之複數個實施形態中，第2阻焊劑4係於接合線6之附近以上表面低於所謂之脊頂(最大高度)之方式設置。然而，亦可形成為高於脊頂。
圖1中，以與半導體元件5隔開之方式配置有第2阻焊劑4。亦即，在半導體元件5與第2阻焊劑4之間具有間隙。再者，於半導體元件5與第2阻焊劑4之間隙配置有絕緣性樹脂10。又，於圖1中，第2阻焊劑4與基板1直接相接。又，於圖1中，第2阻焊劑4與配線2直接相接。又，於圖1中，第2阻焊劑4與第1阻焊劑3直接相接。又，於圖1中，第2阻焊劑4 與接合線6直接相接。又，於圖1中，第2阻焊劑4與絕緣性樹脂10直接相接。
於圖1中，第1阻焊劑3與第2阻焊劑4以成為相同高度之方式構成。又，於圖1中，接合線6貫通第2阻焊劑4。於圖1中，第2阻焊劑4中，雖整體性地被覆接合線6，但第2阻焊劑4除與配線2之連接部分以外，亦能夠使第2阻焊劑4與接合線6非接觸。
藉由設置第2阻焊劑4，以阻焊劑覆蓋配置於基板1之形成有半導體元件5之側之面的配線2之亦包含開口區域A在內之大半部分。於配置於基板1之形成有半導體元件5之側之面的配線2中與接合線6連接之部分，混合存在有配線2、第2阻焊劑4及接合線6等3種材料。與面朝開口區域A之部分相連之配線2係由第1阻焊劑3覆蓋配線2。
先前，於配置於基板1之形成有半導體元件5之側之面的配線2中與接合線6連接之部分，混合存在有配線2、密封劑而非第2阻焊劑4、及接合線6等3種材料。開口區域A係與發熱之半導體元件5鄰接之區域，因此，開口區域A係容易施加熱應力之區域。於先前之半導體裝置中，開口區域A附近之由第1阻焊劑3覆蓋之配線2容易斷線。亦即，面朝開口區域A之配線2之部分與未面朝開口區域A之配線2之部分之間容易斷線。
面朝開口區域A之配線2之部分與未面朝開口區域A之配線2之部分之差異在於有無接合線6及密封劑。若材料不同則熱膨脹係數不同。而且，若材料之硬度等不同，則熱膨脹之影響增大。因此，為了緩和面朝開口區域A之配線2之部分與未面朝開口區域A之配線2之部分的熱應力、機械應力、或熱應力及機械應力，藉由以與第1阻焊劑3同樣地為阻焊 劑之第2阻焊劑4覆蓋面朝開口區域A之配線2，而緩和該等應力，使配線2之可靠性提高。
亦即，於實施形態中，在開口區域A中混合存在有配線2、第2阻焊劑4及接合線6等3種。又，於實施形態中，於與開口區域A鄰接之區域中混合存在有配線2及第1阻焊劑3之2種。於開口區域A與鄰接於開口區域A之區域，配線2與阻焊劑共通。藉由使開口區域A與鄰接於開口區域A之區域中之構成接近，可防止鄰接於開口區域A之配線2斷線，從而可使半導體裝置100之可靠性提高。
於開口區域A中包含接合線6，但於開口區域A與開口區域A外，相同或類似之阻焊劑覆蓋配線2，因此，認為藉由使開口區域A與開口區域A外成為類似之部位而能夠防止配線2斷線。就使配線2之可靠性提高之觀點而言，較佳為第1阻焊劑3之熱膨脹係數β1(/K)與第2阻焊劑4之熱膨脹係數β2大致相同。所謂大致相同，和第1阻焊劑3之熱膨脹係數β1(/K)與第2阻焊劑4之熱膨脹係數β2(/K)之差(2×|β1-β2|/(β1+β2))為5.0%以內為相同含義。而且，就使配線2之可靠性提高之觀點而言，第1阻焊劑3之熱膨脹係數β1(/K)與第2阻焊劑4之熱膨脹係數β2(/K)之差更佳為3.0%以內。
若第1阻焊劑3與第2阻焊劑4為相同之阻焊劑，則配線2之可靠性進一步提高，因此較佳。
就使配線2之可靠性提高之觀點而言，較佳為面朝開口區域A之配線2之整個面由接合線6與第2阻焊劑4覆蓋。亦即，較佳為面朝開口區域A之配線2之面中，除與接合線6連接之部分以外之整個面由第2阻焊劑4覆蓋。進而，進而較佳為開口區域A由第2阻焊劑4填充。若開口區域A之60vol%以上由第2阻焊劑4填充，則上述熱應力、機械應力、或熱 應力及機械應力會進一步緩和。就該觀點而言，更佳為開口區域A之80vol%以上由第2阻焊劑4填充，進而更佳為開口區域A之100vol%由第2阻焊劑4填充。
半導體元件5配置於基板1上。半導體元件5例如包含運算元件或記憶元件。作為將運算元件用於半導體元件5之半導體裝置，並未特別限定，例如有CPU(Central Processing Unit，中央處理單元)、PLD(Programmable Logic Device，可程式邏輯器件)、GPU(Graphic Processing Unit，圖形處理單元)、ASIC(Application Specific Integration Circuit，專用積體電路)或DSP(Digital Signal Processor，數位信號處理器)等。作為將記憶元件用於半導體元件5之半導體裝置，並未特別限定，有DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)、ReRAM(Resistive Random Access Memory，電阻式隨機存取記憶體)、PCRAM(Phase Change Memory，相變記憶體)或NAND(Not AND，反及)等。半導體元件5經由接合線6及配線2而與基板1背面之焊料球8電性連接。半導體元件5配置於基板1上之黏晶7。
絕緣性樹脂10係絕緣性之密封劑。絕緣性樹脂10配置於半導體元件5、第1阻焊劑3及第2阻焊劑4上。絕緣性樹脂10將半導體元件5或設置有配線2之基板1密封。更具體而言，絕緣性樹脂10以焊料球8露出之方式將基板1及半導體元件5整體地覆蓋。絕緣性樹脂10為了機械地保護半導體裝置100而包含填料。再者，本案中，包含平均粒徑為10μm以下之填料的情形作為不含填料之情形處理。較佳為於絕緣性樹脂10中包含平均粒徑為20μm以上之填料。
其次，對半導體裝置100之製造方法進行說明。
半導體裝置100之製造方法包含以下步驟：第1步驟，其係於配置於配置有配線2與半導體元件5之基板1上、具有開口區域A、且配線2之一部分面朝開口區域A之第1阻焊劑3之開口區域A，利用接合線6將配線2與半導體元件5連接；以及第2步驟，其係於開口區域A，將未由接合線6連接之部分之配線2利用第2阻焊劑4覆蓋。
於圖3及圖4中表示半導體裝置100之步驟圖。圖3係於配置於配置有配線2與半導體元件5之基板1上、具有開口區域A、且配線2之一部分面朝開口區域A之第1阻焊劑3之開口區域A，利用接合線6將配線2與半導體元件5連接之步驟(第1步驟)的步驟圖。於未形成第2阻焊劑4之部件中形成接合線6，而將面朝開口區域A之配線2與半導體元件5連接。
繼而，於圖3所示之部件形成第2阻焊劑4。圖4係於開口區域A，將未由接合線6連接之部分之配線2以第2阻焊劑4覆蓋之步驟(第2步驟)。將第2阻焊劑4之前驅物塗佈於開口區域A，例如，照射紫外線而使第2阻焊劑4之前驅物(包含光固性樹脂)硬化。此外，亦可利用熱使第2阻焊劑4之前驅物(包含熱固性樹脂)硬化。第2阻焊劑4之前驅物之塗佈方法並未特別限定，有施配、噴墨及旋轉塗佈等。再者，於硬化後，可進行曝光及顯影，而控制第2阻焊劑4之形成位置等。若以噴墨塗佈第2阻焊劑4之前驅物，則即便不進行曝光、顯影，亦能控制第2阻焊劑4之形成位置。
藉由採用上述製造方法，可藉由簡便之步驟防止配線2斷線，從而獲得可靠性提高之半導體裝置100。
(第2實施形態)
第2實施形態係第1實施形態之變化例。圖5係表示第2實施形態中之 半導體裝置之構成之一例的剖視圖。於圖5所示之半導體裝置101中，第1阻焊劑3之一部分與第2阻焊劑4之一部分積層。由於配線2在開口區域A外側之開口區域A附近容易斷線，故而較佳為於開口區域A附近之第1阻焊劑3之側面與第2阻焊劑4之側面相接之位置，使第1阻焊劑3之一部分與第2阻焊劑4之一部分積層。若以第1阻焊劑3之一部分與第2阻焊劑4之一部分積層之方式形成第2阻焊劑4，則可防止因製造誤差而導致於第1阻焊劑3與第2阻焊劑4之間產生間隙。若在第1阻焊劑3與第2阻焊劑4之間存在間隙，則配線2於間隙附近容易斷線，故而不佳。
(第3實施形態)
第3實施形態係第1實施形態之變化例。圖6係表示第3實施形態中之半導體裝置之構成之一例的剖視圖。於圖6所示之半導體裝置102中，第1阻焊劑3由第2阻焊劑4覆蓋。該構造係與第2實施形態之半導體裝置101同樣地，在第1阻焊劑3與第2阻焊劑4之間不易產生間隙。又，於半導體裝置102中，除配置有半導體元件5之部分以外，於配置有配線2之基板1上整體地形成有第2阻焊劑4。與局部形成第2阻焊劑4之情形相比，第2阻焊劑4之可靠性提高，再者，可簡化形成步驟。
(第4實施形態)
第4實施形態係第3實施形態之變化例。圖7係表示第4實施形態中之半導體裝置之構成之一例的剖視圖。於圖7所示之半導體裝置103中，在半導體元件5與第2阻焊劑4之間存在間隙。於半導體裝置102中，半導體元件5具有與第2阻焊劑4相接之面及與絕緣性樹脂10相接之面兩者。因第 2阻焊劑4與絕緣性樹脂10之物性之差異，故對半導體元件5之熱性、機械或熱性及機械之外在影響因部位而異。另一方面，於半導體裝置103中，除黏晶7以外，半導體元件5由絕緣性樹脂10覆蓋，因此就上述觀點而言較佳。
(第5實施形態)
第5實施形態係第3實施形態之變化例。圖8係表示第5實施形態中之半導體裝置之構成之一例的剖視圖。於圖8所示之半導體裝置104中，除黏晶7以外，半導體元件5由第2阻焊劑4覆蓋。該構造就上述觀點而言較佳。
(第6實施形態)
第6實施形態係第1實施形態之變化例。圖9係表示第6實施形態中之半導體裝置之構成之一例的剖視圖。於圖9所示之半導體裝置105中，接合線6之直徑相對於第2阻焊劑4之厚度變大。即便第2阻焊劑4之厚度相對地較薄，實施形態之半導體裝置105之可靠性亦會提高。
(第7實施形態)
第7實施形態係第1實施形態之變化例。圖10係表示第7實施形態中之半導體裝置之構成之一例的剖視圖。於圖10所示之半導體裝置106中，將焊料球8置換為焊盤11。半導體裝置106為LGA(Land Grid Array，焊盤網格陣列)型，實施形態之構成於LGA型半導體裝置106中亦使可靠性提高。
(第8實施形態)
第8實施形態係第1實施形態之變化例。圖11係表示第8實施形態中之半導體裝置之構成之一例的剖視圖。圖11所示之半導體裝置200中，實施形態之半導體裝置107與108積層。即便為積層型，亦能防止配線2斷線，從而使半導體裝置200之可靠性提高。
此外，具備本發明之要素、且業者能夠適當進行設計變更之所有半導體裝置包含於本發明之範圍。
又，為了簡化說明，省略了半導體產業中通常所使用之方法、例如光微影製程、處理前後之清潔等，但當然亦可包含該等方法。
[相關申請案]
本申請案享有以日本專利申請案2018-173106號(申請日：2018年9月14日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:基板
2:配線
3:第1阻焊劑
4:第2阻焊劑
5:半導體元件
6:接合線
7:黏晶
8:焊料球
9:絕緣膜
10:絕緣性樹脂
100:半導體裝置

Claims (9)

  1. 一種半導體裝置，其具備：基板，其設置有配線；半導體元件，其設置於上述基板上；第1樹脂，其設置於上述基板上，且形成有開口區域；電極部，其係上述配線自上述第1樹脂露出之部分；導線，其將上述電極部與上述半導體元件連接；及第2樹脂，其覆蓋上述電極部，且於上述導線附近之上表面低於上述導線之最大高度；且於將上述第1樹脂之熱膨脹係數設為β1(/K)，將上述第2樹脂之熱膨脹係數設為β2(/K)時，(2×|β1-β2|/(β1+β2))×100之值為5.0以下。
  2. 如請求項1之半導體裝置，其中上述電極部之整個表面由上述導線與上述第2樹脂覆蓋。
  3. 如請求項1之半導體裝置，其具備絕緣性樹脂，該絕緣性樹脂配置於上述半導體元件、上述第1樹脂及上述第2樹脂上，且含有填料。
  4. 如請求項1之半導體裝置，其中上述第1樹脂之一部分與上述第2樹脂之一部分積層。
  5. 如請求項1之半導體裝置，其中上述開口區域由上述第2樹脂填充。
  6. 如請求項1之半導體裝置，其中在上述半導體元件與上述第2樹脂之間具有間隙。
  7. 如請求項1之半導體裝置，其中上述第2樹脂覆蓋上述半導體元件。
  8. 如請求項1之半導體裝置，其中上述值為3.0以下。
  9. 一種半導體裝置之製造方法，其包含以下步驟：準備設置有配線之基板；於上述基板設置形成有開口區域之第1樹脂，且形成上述配線自上述第1樹脂露出之部分即電極部；於上述基板設置半導體元件；將上述電極部與上述半導體元件以導線連接；及以上述導線附近之上表面低於上述導線之最大高度之方式，以第2樹脂覆蓋上述電極部；且於將上述第1樹脂之熱膨脹係數設為β1(/K)，將上述第2樹脂之熱膨脹係數設為β2(/K)時，(2×|β1-β2|/(β1+β2))×100之值為5.0以下。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4733289A (en) * 1980-04-25 1988-03-22 Hitachi, Ltd. Resin-molded semiconductor device using polyimide and nitride films for the passivation film
TW200629509A (en) * 2004-10-29 2006-08-16 Renesas Tech Corp A semiconductor device and a method for manufacturing of the same
TW201613004A (en) * 2014-09-17 2016-04-01 Toshiba Kk Semiconductor memory device
WO2018116785A1 (ja) * 2016-12-20 2018-06-28 株式会社デンソー 半導体装置およびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3825181B2 (ja) 1998-08-20 2006-09-20 沖電気工業株式会社 半導体装置の製造方法及び半導体装置
JP2002093950A (ja) 2000-09-20 2002-03-29 Mitsui Mining & Smelting Co Ltd 電子部品の実装方法および電子部品実装体
JP4067507B2 (ja) * 2003-03-31 2008-03-26 三洋電機株式会社 半導体モジュールおよびその製造方法
JP3701949B2 (ja) * 2003-04-16 2005-10-05 沖電気工業株式会社 半導体チップ搭載用配線基板及びその製造方法
JP3897749B2 (ja) 2003-10-31 2007-03-28 沖電気工業株式会社 半導体装置
US20070018308A1 (en) * 2005-04-27 2007-01-25 Albert Schott Electronic component and electronic configuration
JP2009503837A (ja) * 2005-07-28 2009-01-29 エヌエックスピー ビー ヴィ マイクロエレクトロニクス部品用パッケージ及びその製造方法
JP2009283873A (ja) 2008-05-26 2009-12-03 Toshiba Corp 半導体装置
JP2011211114A (ja) 2010-03-30 2011-10-20 Toshiba Corp 半導体装置
KR20130010359A (ko) * 2011-07-18 2013-01-28 삼성전자주식회사 반도체 장치용 기판 및 그를 포함한 반도체 장치
JP2020047664A (ja) * 2018-09-14 2020-03-26 キオクシア株式会社 半導体装置および半導体装置の作製方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4733289A (en) * 1980-04-25 1988-03-22 Hitachi, Ltd. Resin-molded semiconductor device using polyimide and nitride films for the passivation film
TW200629509A (en) * 2004-10-29 2006-08-16 Renesas Tech Corp A semiconductor device and a method for manufacturing of the same
TW201613004A (en) * 2014-09-17 2016-04-01 Toshiba Kk Semiconductor memory device
WO2018116785A1 (ja) * 2016-12-20 2018-06-28 株式会社デンソー 半導体装置およびその製造方法

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