TWI428997B - 半導體封裝結構及其製作方法 - Google Patents

半導體封裝結構及其製作方法 Download PDF

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TWI428997B
TWI428997B TW100144388A TW100144388A TWI428997B TW I428997 B TWI428997 B TW I428997B TW 100144388 A TW100144388 A TW 100144388A TW 100144388 A TW100144388 A TW 100144388A TW I428997 B TWI428997 B TW I428997B
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TW201324631A (zh
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Yu Tang Pan
Shih Wen Chou
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Chipmos Technologies Inc
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Priority to US13/647,406 priority patent/US8691630B2/en
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Description

半導體封裝結構及其製作方法
本發明是有關於一種半導體元件及其製作方法，且特別是有關於一種半導體封裝結構及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。常見的封裝方法是晶片透過打線接合(wire bonding)或覆晶接合(flip chip bonding)的方式而安裝至一導線架或一線路板上，以使晶片上的接點可電性連接至導線架或線路板上。如此一來，晶片的接點分佈可藉由導線架或線路板重新配置，以符合下一層級的外部元件的接點分佈。
然而隨著技術提昇以及元件尺寸微型化的趨勢，晶片的尺寸逐漸縮小。因此，當晶片的尺寸縮小時，晶片與導線架之引腳間的距離相對地增加，連接晶片與引腳的銲線長度也因此增長。如此一來，可能造成元件之傳輸信號衰減、電性效能降低、生產成本提高。再者，較長的銲線也可能在進行封膠製程時，產生線塌(collapse)或線偏移(wire sweep)的狀況，進而影響產品的可靠度。
本發明提供一種半導體封裝結構，其具有較佳的可靠度。
本發明提供一種半導體封裝結構的製作方法，用以製作上述之半導體封裝結構。
本發明提出一種半導體封裝結構的製作方法，其包括以下步驟。提供一導電基材，其中導電基材具有彼此相對之一第一表面與一第二表面。透過一第一黏著層將一導熱塊貼附於導電基材的部分第二表面上。對導電基材的第一表面進行一半蝕刻步驟，以移除部分導電基材，而形成一開口於第一表面。圖案化剩餘的導電基材，以形成多個彼此電性絕緣的引腳，並暴露部分導熱塊，其中每一引腳具有一第一部分與一第二部分，第一部分的厚度大於第二部分的厚度，且第一部分的一第一下表面與第二部分的一第二下表面齊平。將一晶片配置於被暴露出的部分導熱塊上，其中引腳的第二部分鄰近且環繞晶片的周圍，而晶片與引腳的第二部分電性連接。形成一封裝膠體以包覆晶片、部分引腳以及部分導熱塊。
本發明提出一種半導體封裝結構，其包括一導熱塊、多個引腳、一第一黏著層、一晶片以及一封裝膠體。導熱塊具有彼此相對之一第一頂面與一第一底面。引腳配置於導熱塊的第一頂面上，並暴露出部分第一頂面。引腳彼此電性絕緣，其中每一引腳具有一第一部分與一第二部分，且第一部分的厚度大於第二部分的厚度，而第一部分的一第一下表面與第二部分的一第二下表面齊平。第一黏著層配置於引腳與導熱塊之間。晶片配置於導熱塊被暴露出的部分第一頂面上，其中引腳的第二部分鄰近且環繞晶片的周圍，晶片與引腳的第二部分電性連接。封裝膠體包覆晶片、部分引腳以及部分導熱塊。
基於上述，由於本發明是對導電基材進行半蝕刻步驟及圖案化步驟來形成同時具有不同厚度之第一部分及第二部分的引腳。因此，當晶片設置於導熱塊上時，本發明之半導體封裝結構除了可具有較佳的散熱效能外，亦可透過引腳的第二部分鄰近且環繞晶片的設計來縮短採用打線接合時晶片與引腳之間的銲線距離，以避免習知長銲線線塌(collapse)或線偏移(wire sweep)的狀況，可有效提昇產品的可靠度。再者，當晶片採用覆晶接合的方式與引腳的第二部分電性連接時，亦可有效降低封裝厚度，使半導體封裝結構具有較薄的封裝厚度。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之一種半導體封裝結構的俯視示意圖。圖2A至圖2E為本發明之一實施例之一種半導體封裝結構的製作方法的剖面示意圖。請先參考圖2A，本實施例的半導體封裝結構的製作方法包括以下步驟。首先，提供一導電基材110，其中導電基材110具有彼此相對之一第一表面112與一第二表面114，且導電基材110的材質例如是金屬，包括銅、銅合金、鐵鎳合金或其他適當的金屬材質。當然，導電基材110的材質亦可是其他具有導電性質的材料。
接著，請再參考圖2A，透過一第一黏著層120將一導熱塊130貼附於導電基材110的部分第二表面114上，其中第一黏著層120位於導熱塊130與導電基材110之間，且導熱塊130暴露出導電基材110的部分第二表面114。具體來說，本實施例之導熱塊130具有彼此相對之一第一頂面132與一第一底面134，其中第一頂面132連接第一黏著層120，且導熱塊130的材質包括銅、鋁、銅合金、鋁合金、鐵鎳合金或其他具有導電性質的材料。
接著，請參考圖2B，對導電基材110的第一表面112進行一半蝕刻(half-etching)步驟，以移除部分導電基材110，而形成一開口113於導電基材110的第一表面112，其中位於開口113內之部分導電基材110的厚度小於原本導電基材110的厚度。
接著，請同時參考圖1與圖2C，圖案化剩餘的導電基材110，以形成多個彼此電性絕緣的引腳140，並暴露部分導熱塊130，即導熱塊130的部分第一頂面132，其中圖案化剩餘的導電基材110的方法例如是蝕刻法。
特別是，在本實施例中，每一引腳140具有一第一部分142與一第二部分144，其中第一部分142的厚度T1大於第二部分144的厚度T2，且第一部分142的一第一下表面143與第二部分144的一第二下表面145實質上齊平。此外，本實施例之任兩相鄰之引腳140之第一部分142的間距為P1，而任兩相鄰之引腳140之第二部分144的間距為P2，則較佳地0.8P1P21.2P1。於此，任兩相鄰之引腳140之第二部分144的間距P2例如是介於40微米至60微米之間，較佳地，介於50微米至60微米之間，此間距P2可依據晶片之接墊152之間的間距來調整，於此並不加以限制。
之後，請同時參考圖1與圖2D，將一晶片150配置於被暴露出的部分導熱塊130上，即導熱塊130的部分第一頂面132上，其中引腳140的第二部分144鄰近且環繞晶片150的周圍，而晶片150與引腳140的第二部分144電性連接。在本實施例中，晶片150是透過一第二黏著層125而固定於被暴露出的部分導熱塊130上，即第二黏著層125配置於導熱塊130的部分第一頂面132與晶片150之間，且晶片150透過多條銲線160與引腳140的第二部分144電性連接。
最後，請同時參考圖1與圖2E，形成一封裝膠體170以包覆晶片150、部分引腳140以及部分導熱塊130，並填滿引腳140之間的間隙，其中導熱塊130的第一底面132與封裝膠體170的一第二底面172實質上齊平。當然，於其他未繪示的實施例中，導熱塊130的第一底面132亦可包覆於封裝膠體170內。較佳地，封裝膠體170可暴露出引腳140的部分第一部分142以形成一般之導線架(如圖2E所示)，亦或，可視實際所需而不暴露出引腳140以形成一QFN結構(未繪示)。至此，已完成半導體封裝結構100a的製作。
在結構上，請再參考圖2E，本實施例之半導體封裝結構100a包括第一黏著層120、第二黏著層125、導熱塊130、引腳140、晶片150、銲線160以及封裝膠體170。詳細來說，導熱塊130具有彼此相對之第一頂面132與第一底面134。引腳140配置於導熱塊130的第一頂面132上，並暴露出部分第一頂面132。引腳140彼此電性絕緣，且每一引腳140具有第一部分142與第二部分144，其中第一部分142的厚度T1大於第二部分144的厚度T2，而第一部分142的第一下表面143與第二部分144的第二下表面145實質上齊平。第一黏著層120配置於引腳140與導熱塊130之間，其中引腳140透過第一黏著層120而固定於導熱塊130上。晶片150配置於導熱塊130被暴露出的部分第一頂面132上，其中引腳140的第二部分144鄰近且環繞晶片150的周圍，而晶片150透過第二黏著層125固定導熱塊130被暴露出的部分第一頂面132上，且晶片150透過銲線160與引腳140的第二部分144電性連接。封裝膠體170包覆晶片150、部分引腳140以及部分導熱塊130。於此，導熱塊130的第一底面132外露於封裝膠體170並與封裝膠體170的第二底面172實質上齊平。
由於本實施例是對導電基材110進行半蝕刻步驟及圖案化步驟來形成具有第一部分142及第二部分144的引腳140，其中第一部分142的厚度T1大於第二部分144的厚度T2。因此，當晶片150設置於導熱塊130上時，晶片150所產生的熱可透過導熱塊130的第一底面134快速地傳遞至外界，而使本實施例之半導體封裝結構100a具有較佳的散熱效能。再者，可利用引腳140的第二部分144鄰近且環繞晶片150的設計，使晶片150藉由打線接合的方式以透過銲線160來電性連接引腳140的第二部分144。如此一來，可有效縮短採用打線接合時晶片150與引腳140之間的銲線距離，以避免習知長銲線線塌(collapse)或線偏移(wire sweep)的狀況，可有效提昇產品的可靠度。
圖3A至圖3B為本發明之另一實施例之一種半導體封裝結構的製作方法之局部步驟的剖面示意圖。本實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，本實施例不再重複贅述。
請先參考圖3B，本實施例的半導體封裝結構100b與前述實施例之半導體封裝結構100a主要的差異是在於：半導體封裝結構100b更包括多個凸塊165，其中凸塊165配置於晶片150與引腳140之第二部分144之間，且晶片150是藉由覆晶接合的方式以透過凸塊165與引腳140之第二部分144電性連接。由於本實施例之晶片150是採用覆晶接合的方式與引腳140的第二部分144電性連接，且引腳140之第二部分144之厚度T2小於第一部分142之厚度T1，因此可有效降低整體封裝厚度，使半導體封裝結構100b具有較薄的封裝厚度。
在製程上，本實施例的半導體封裝結構100b可以採用與前述實施例之半導體封裝結構100a大致相同的製作方式，並且在圖2C之步驟後，即圖案化剩餘的導電基材110，以形成彼此電性絕緣的引腳140之後，藉由覆晶接合的方式使晶片150透過凸塊165與引腳140之第二部分144電性連接。接著，依序進行圖2E之步驟，即便可大致完成半導體封裝結構100b的製作。
當然，圖2A至圖2E以及圖3A至3B所繪示的製程僅是作為舉例說明之用，部分步驟為目前封裝製程中常見的技術。本領域的技術人員當可依據實際狀況調整、省略或增加可能的步驟，例如以陣列方式配置多個導熱塊130於導電基材110上，之後再進行單體化步驟以同時大量製作多個半導體封裝結構100a(或100b)，以符合量產及降低成本的需求，此處不再逐一贅述。
綜上所述，由於本發明是對導電基材進行半蝕刻步驟及圖案化步驟來形成同時具有不同厚度之第一部分及第二部分的引腳。因此，當晶片設置於導熱塊上時，本發明之半導體封裝結構除了可具有較佳的散熱效能外，亦可透過引腳的第二部分鄰近且環繞晶片的設計來縮短採用打線接合時晶片與引腳之間的銲線距離，以避免習知長銲線線塌(collapse)或線偏移(wire sweep)的狀況，可有效提昇產品的可靠度。再者，當晶片採用覆晶接合的方式與引腳的第二部分電性連接時，亦可有效降低封裝厚度，使半導體封裝結構具有較薄的封裝厚度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100a、100b．．．半導體封裝結構
110．．．導電基材
112．．．第一表面
113．．．開口
114．．．第二表面
120．．．第一黏著層
125．．．第二黏著層
130．．．導熱塊
132．．．第一頂面
134．．．第一底面
140．．．引腳
142．．．第一部分
143．．．第一下表面
144．．．第二部分
145．．．第二下表面
150．．．晶片
152．．．接墊
160．．．銲線
165．．．凸塊
170．．．封裝膠體
172．．．第二底面
P1．．．第一部分的間距
P2．．．第二部分的間距
T1、T2．．．厚度
圖1為本發明之一實施例之一種半導體封裝結構的俯視示意圖。
圖2A至圖2E為本發明之一實施例之一種半導體封裝結構的製作方法的剖面示意圖。
圖3A至圖3B為本發明之另一實施例之一種半導體封裝結構的製作方法之局部步驟的剖面示意圖。
100a．．．半導體封裝結構
120．．．第一黏著層
125．．．第二黏著層
130．．．導熱塊
132．．．第一頂面
134．．．第一底面
140．．．引腳
142．．．第一部分
143．．．第一下表面
144．．．第二部分
145．．．第二下表面
150．．．晶片
160．．．銲線
170．．．封裝膠體
172．．．第二底面
T1、T2．．．厚度

Claims (8)

  1. 一種半導體封裝結構的製作方法，包括：提供一導電基材，該導電基材具有彼此相對之一第一表面與一第二表面；透過一第一黏著層將一導熱塊貼附於該導電基材的部分該第二表面上；對該導電基材的該第一表面進行一半蝕刻步驟，以移除部分該導電基材，而形成一開口於該第一表面；圖案化剩餘的該導電基材，以形成多個彼此電性絕緣的引腳，並暴露部分該導熱塊，其中各該引腳具有一第一部分與一第二部分，該第一部分的厚度大於該第二部分的厚度，且該第一部分的一第一下表面與該第二部分的一第二下表面齊平，任兩相鄰之該些引腳之該些第一部分的間距為P1，而任兩相鄰之該些引腳之該些第二部分的間距為P2，則0.8P1P21.2P1；將一晶片配置於被暴露出的部分該導熱塊上，其中該些引腳的該些第二部分鄰近且環繞該晶片的周圍，而該晶片與該些引腳的該些第二部分電性連接；以及形成一封裝膠體以包覆該晶片、部分該些引腳以及部分該導熱塊。
  2. 如申請專利範圍第1項所述之半導體封裝結構的製作方法，其中任兩相鄰之該些引腳之該些第二部分的間距介於40微米至60微米之間。
  3. 如申請專利範圍第1項所述之半導體封裝結構的 製作方法，其中該晶片透過多條銲線與該些引腳的該些第二部分電性連接。
  4. 如申請專利範圍第1項所述之半導體封裝結構的製作方法，其中該晶片透過多個凸塊與該些引腳的該些第二部分電性連接。
  5. 一種半導體封裝結構，包括：一導熱塊，具有彼此相對之一第一頂面與一第一底面；多個引腳，配置於該導熱塊的該第一頂面上，並暴露出部分該第一頂面，該些引腳彼此電性絕緣，其中各該引腳具有一第一部分與一第二部分，且該第一部分的厚度大於該第二部分的厚度，而該第一部分的一第一下表面與該第二部分的一第二下表面齊平，任兩相鄰之該些引腳之該些第一部分的間距為P1，而任兩相鄰之該些引腳之該些第二部分的間距為P2，則0.8P1P21.2P1；一第一黏著層，配置於該些引腳與該導熱塊之間；一晶片，配置於該導熱塊被暴露出的部分該第一頂面上，其中該些引腳的該些第二部分鄰近且環繞該晶片的周圍，該晶片與該些引腳的該些第二部分電性連接；以及一封裝膠體，包覆該晶片、部分該些引腳以及部分該導熱塊。
  6. 如申請專利範圍第5項所述之半導體封裝結構，其中任兩相鄰之該些引腳之該些第二部分的間距介於40微米至60微米之間。
  7. 如申請專利範圍第5項所述之半導體封裝結構，更包括多條銲線，配置於該晶片與該些引腳之該些第二部分之間，其中該晶片透過該些銲線與該些引腳之該些第二部分電性連接。
  8. 如申請專利範圍第5項所述之半導體封裝結構，更包括多個凸塊，配置於該晶片與該些引腳之該些第二部分之間，其中該晶片透過該些凸塊與該些引腳之該些第二部分電性連接。
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