TWI595616B - 晶片封裝體及其形成方法 - Google Patents

晶片封裝體及其形成方法 Download PDF

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TWI595616B
TWI595616B TW103120140A TW103120140A TWI595616B TW I595616 B TWI595616 B TW I595616B TW 103120140 A TW103120140 A TW 103120140A TW 103120140 A TW103120140 A TW 103120140A TW I595616 B TWI595616 B TW I595616B
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Taiwan
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conductive
conductive plate
forming
chip package
patterned
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TW103120140A
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TW201508880A (zh
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許文松
林明杰
于達人
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聯發科技股份有限公司
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Description

晶片封裝體及其形成方法
本揭露書係有關於晶片封裝體及其形成方法，且特別是有關於晶片尺寸封裝體(chip scale package，CSP)及其形成方法。
晶片封裝體除了保護晶片使免受環境汙染之外，還對封裝於其中之晶片提供連接介面。隨著對更快、更小電子產品之需求增加，使具高速效能之晶片封裝體的需求增加。業界還有縮減晶片封裝體之製作成本與製作時間之需求。
本發明一實施例提供一種晶片封裝體，包括：一圖案化導電板，具有彼此電性隔離之複數個導電部分；複數個導電墊，設置於該圖案化導電板之一上表面之上；一晶片，設置於該些導電墊之上；複數個導電凸塊，設置於該圖案化導電板之一下表面之上，其中每一該些導電凸塊電性連接至該圖案化導電板之該些導電部分之對應的其中之一；以及一絕緣支撐層，部分圍繞該些導電凸塊。
本發明一實施例提供一種晶片封裝體的形成方法，包括：提供一導電板，其中複數個導電墊係設置於該導電板之一上表面之上；形成複數個導電凸塊於該導電板之一下表面之 上；藉由移除一部分的該導電板而將該導電板圖案化為一圖案化導電板，其中該圖案化導電板具有彼此電性隔離之複數個導電部分，且每一該些導電凸塊電性連接至該圖案化導電板之該些導電部分之對應的其中之一；形成一絕緣支撐層以部分圍繞該些導電凸塊；以及將一晶片設置於該些導電墊之上。
本發明之晶片封裝體及其形成方法可顯著地降低晶片封裝體的製作成本，且可獲得具有尺寸縮小化及效能提升化之晶片封裝體。
100‧‧‧導電板
100a、100b、100c、100d、100e‧‧‧導電部分
102a、102b、102c、102d、102e‧‧‧導電墊
104a、104b‧‧‧導電凸塊
106‧‧‧絕緣保護層
108‧‧‧絕緣支撐層
110‧‧‧晶片
112‧‧‧導電結構
114‧‧‧封膠材料
502‧‧‧凹陷
第1A-1E圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第2A及2B圖顯示根據本發明實施例之晶片封裝體的剖面圖。
第3A-3D圖顯示根據本發明一實施例之晶片封裝體的製程剖面圖。
第4A及4B圖顯示根據本發明實施例之晶片封裝體的剖面圖。
第5圖顯示根據本發明一實施例之晶片封裝體的剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在 不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
第1A-1E圖顯示根據本發明一實施例之晶片封裝 體的製程剖面圖。如第1A圖所示，提供導電板100，其可為(但不限於)單層基底(single layer substrate)。導電板100可包括(但不限於)金屬材料，例如銅、鋁、鎳、鐵、鉛、錫、或前述之組合。或者，導電板100可包括具有或不具有摻質(dopants)於其中之半導體材料。可於導電板100之上表面(upper surface)上設置複數個導電墊，例如是導電墊102a、102b、102c、102d、及102e。在一實施例中，可於導電板100之上表面上形成一導電層，並接著將之圖案化以形成導電墊(102a-102e)。導電墊(102a-102e)可直接接觸導電板100。或者，其他材料層(未顯示)可設置於導電墊與導電板100之間。在一實施例中，導電墊(102a-102e)與導電板100之材質係相同的。在其他實施例中，導電墊(102a-102e)之材質係不同於導電板100之材質。在一實施例中，用於晶片尺寸封裝製程(CSP package process)中之低成本導線架(low-cost lead frame)係經修飾調整並用做承載導電墊(102a-102e)之導電板100。因此，本發明實施例之晶片封裝體的製作成本可顯著地減少。
如第1A圖所示，可於導電板100之下表面(lower surface)上形成複數個導電凸塊(conducting bumps)，例如是導 電凸塊104a及104b。導電凸塊(104a-104b)可於後續的一選擇性蝕刻製程(optional etching process)期間，用作蝕刻遮罩。可進行選擇性蝕刻製程以將導電板100圖案化。因此，導電凸塊之圖案可根據需求而改變。在一實施例中，可於蝕刻製程中使用對於導電板100有相對高蝕刻速度之蝕刻劑(相較於對導電凸塊之蝕刻速度)。可藉由使用不同的蝕刻劑而調整蝕刻速度。 蝕刻速度可依需求而調變。在其他實施例中，每一導電凸塊(104a-104b)可較導電板100厚。因此，在蝕刻導電板100所露出之部分後，導電凸塊(104a-104b)仍保留。導電凸塊之尺寸、形狀、及/或分布可根據導電板100之所需圖案而調整。例如，每一導電凸塊可覆蓋於至少一導電墊之上。
如第1B圖所示，可選擇性地於導電板100之上表面 上形成絕緣保護層106以圍繞導電墊(102a-102e)。導電墊(102a-102e)係部分露出。絕緣保護層106可於後續的蝕刻製程中用作蝕刻停止層，並固定導電板100上之導電墊(102a-102e)。 絕緣保護層106之材質可包括(但不限於)非導電膜(non-conductive film)或非導電膏(non-conductive paste)。非導電膜或非導電膏可包括氧化物、氮化物、高分子、或前述之組合。
請參照第1C圖，接著藉由移除一部分的導電板100 而將導電板100圖案化。在一實施例中，導電凸塊104a及104b可用做蝕刻遮罩，並於導電板100之下表面上進行蝕刻製程以部分移除導電板100。可移除導電板100之未被導電凸塊(例如，導電凸塊104a及104b)覆蓋之部分以於導電板100之中形成開 口。如第1C圖所示，圖案化導電板具有複數個導電部分(conducting sections)，例如是導電部分100a及100b。然，應注意的是，本發明實施例不限於此。在其他實施例中，可於導電板100之下表面上另外形成遮罩層，例如是圖案化光阻層(未顯示)。遮罩層可具有露出部分導電板100之開口。接著，可進行蝕刻製程以透過遮罩層之開口而部分移除導電板100，使得導電板100根據需求而圖案化。
導電部分100a及100b可彼此電性隔離。每一導電 凸塊電性連接至圖案化導電板之對應的導電部分。例如，導電凸塊104a可電性連接至導電部分100a，而導電凸塊104b可電性連接至導電部分100b。在一實施例中，導電墊102a及102b可透過由導電部分100a所提供之導電路徑而電性連接至導電凸塊104a。相似地，導電墊102c可透過由圖案化導電板之另一導電部分(未顯示)所提供之導電路徑而電性連接至一導電凸塊(未顯示)。導電墊102c可沿著垂直於第1C圖所示剖面之方向延伸以電性接觸圖案化導電板之一對應的導電部分(未顯示)。或者，導電墊102c可為虛置接墊(dummy pad)，其不與任何的導電凸塊電性連接。
請參照第1D圖，可接著形成絕緣支撐層108以部分 圍繞導電凸塊104a及104b。在此實施例中，絕緣支撐層108可進一步延伸進入圖案化導電板之導電部分之間的開口(例如，導電部分100a與100b之間的開口)以圍繞導電部分之側壁。在一實施例中，絕緣支撐層108可透過圖案化導電板之導電部分之間的至少一開口而直接接觸至少一導電墊(例如，導電墊 102c)。絕緣支撐層108固定導電部分及其上之導電墊及導電凸塊，並提供更佳的結構強度。絕緣支撐層108之材質可包括(但不限於)非導電膜或非導電膏。非導電膜或非導電膏可包括氧化物、氮化物、高分子、或前述之組合。
如第1E圖所示，可例如使用覆晶製程(flip-chip process)而於導電墊上設置晶片110。在一實施例中，可選擇性於晶片110與導電墊(102a-102e)之間設置多個導電結構112。可選擇性將顯示於第1E圖之結構設置於印刷電路板(未顯示)之上。可於印刷電路板與導電凸塊之間形成焊球(solder ball)。因此，可藉由圖案化導電板之導電部分與其上之導電墊及導電凸塊而於印刷電路板與晶片110之間傳遞電性訊號。在此實施例中，晶片110直接透過圖案化導電板而與其他電子構件電性連結，而未透過任何的接合線(bonding wire)。電性訊號可以較快的速度傳遞。
本發明實施例可有許多變化。例如，第5圖顯示根 據本發明一實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。在一實施例中，在第1C圖所述之蝕刻製程進行之後，凹陷502可形成自其中一導電墊(例如，導電墊102c)的表面。凹陷502可自導電墊102c之下表面朝其內部(inner portion)延伸。
第2A及2B圖顯示根據本發明實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。如第2A圖所示，在一實施例中，可選擇性於圖案化導電板之上形成封膠材料(molding compound)114(例如，模塑底膠(molded underfill))以覆蓋晶片110。封膠材料114可覆蓋導電結構112及導電墊。如第2B圖所示，在另一實施例中，可選擇性於晶片110與導電墊之間形成底膠116(例如，毛細現象式底膠(capillary underfill))。底膠116可圍繞導電結構112。
第3A-3D圖顯示根據本發明另一實施例之晶片封 裝體的製程剖面圖，其中相同或相似之標號用以標示相同或相似之元件。如第3A圖所示，提供相似於第1A圖所示之結構。
請參照第3B圖，於導電板100(其尚未被圖案化)之 下表面上形成絕緣支撐層108。接著，如第3C圖所示，將導電板100圖案化以形成圖案化導電板，其具有彼此電性隔離之複數個導電部分，例如是導電部分100a、100b、100c、100d、及100e。在一實施例中，可於導電板100之上表面上進行蝕刻製程以部分移除導電板100。在一實施例中，導電墊(102a-102e)可於蝕刻製程期間用作蝕刻遮罩。在蝕刻製程中，可使用對於導電墊(102a-102e)具有相對低蝕刻速度的蝕刻劑。或者，可於導電板100之下表面上形成遮罩層(未顯示)，例如是圖案化光阻層。接著，可於導電板100之未被遮罩層所覆蓋的部分上進行蝕刻製程以將導電板100圖案化成導電部分(100a-100e)。
如第3D圖所示，可於導電墊之上設置晶片110，且可於其間形成用於電性連接之導電結構112。可採用覆晶製程來設置晶片110。因此，可透過圖案化導電板而於晶片110與配置於導電凸塊之下之一電子構件(未顯示)之間傳遞電性訊號。在此實施例中，絕緣支撐層108不直接接觸導電墊(102a-102e)。此外，絕緣支撐層108不圍繞圖案化導電板之導電部分 (100a-100e)。
第4A及4B圖顯示根據本發明實施例之晶片封裝體的剖面圖，其中相同或相似之標號用以標示相同或相似之元件。如第4A圖所示，在一實施例中，可選擇性於圖案化導電板上形成封膠材料114以覆蓋晶片110。封膠材料114可覆蓋導電結構112及導電墊。如第4B圖所示，在其他實施例中，可選擇性於晶片110與導電墊之間形成底膠116。底膠116可圍繞導電結構112。
在本發明實施例中，晶片封裝體的製作成本可顯著地降低。此外，可獲得具有尺寸縮小化及效能提升化之晶片封裝體。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100a、100b‧‧‧導電部分
102a、102b、102c、102d、102e‧‧‧導電墊
104a、104b‧‧‧導電凸塊
106‧‧‧絕緣保護層
108‧‧‧絕緣支撐層
110‧‧‧晶片
112‧‧‧導電結構

Claims (14)

  1. 一種晶片封裝體的形成方法，包括：提供一導電板，其中複數個導電墊係設置於該導電板之一上表面之上；形成複數個導電凸塊於該導電板之一下表面之上；藉由移除一部分的該導電板而將該導電板圖案化為一圖案化導電板，其中該圖案化導電板具有彼此電性隔離之複數個導電部分，且每一該些導電凸塊電性連接至該圖案化導電板之該些導電部分之對應的其中之一；形成一絕緣支撐層以部分圍繞該些導電凸塊；以及將一晶片設置於該些導電墊之上。
  2. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該絕緣支撐層係形成在將該導電板圖案化之後，且該絕緣支撐層更圍繞該圖案化導電板之該些導電部分的側壁。
  3. 如申請專利範圍第2項所述之晶片封裝體的形成方法，更包括於該導電板之該上表面上形成一絕緣保護層以在將該導電板圖案化之前圍繞該些導電墊。
  4. 如申請專利範圍第2項所述之晶片封裝體的形成方法，其中將該導電板圖案化之步驟包括在該導電板之該下表面上進行一蝕刻製程以移除該導電板之該部分。
  5. 如申請專利範圍第4項所述之晶片封裝體的形成方法，其中在進行該蝕刻製程之後，一凹陷形成自其中一該些導電墊之一表面。
  6. 如申請專利範圍第4項所述之晶片封裝體的形成方法，其中 在該蝕刻製程期間，該些導電凸塊係用作一蝕刻遮罩。
  7. 如申請專利範圍第1項所述之晶片封裝體的形成方法，其中該絕緣支撐層係形成於將該導電板圖案化之前。
  8. 如申請專利範圍第7項所述之晶片封裝體的形成方法，其中將該導電板圖案化之步驟包括於該導電板之該上表面之上進行一蝕刻製程以移除該導電板之該部分。
  9. 如申請專利範圍第8項所述之晶片封裝體的形成方法，其中在該蝕刻製程期間，該些導電墊係用作一蝕刻遮罩。
  10. 如申請專利範圍第1項所述之晶片封裝體的形成方法，更包括於該圖案化導電板之上形成一封膠材料以覆蓋該晶片。
  11. 一種晶片封裝體的形成方法，包括：提供一導電板；在該導電板之一上表面之上形成複數個導電墊；在該導電板之一下表面之上形成複數個導電凸塊；在該導電板之該下表面之上形成一絕緣支撐層，以部分圍繞該等導電凸塊；通過移除一部分的該導電板而將該導電板圖案化為圖案化導電板，其中該圖案化導電板具有彼此電性隔離之複數個導電部分，且該等導電凸塊中之每一個電性連接至該圖案化導電板之該等多個導電部分中對應的一個；以及將一晶片設置於該等導電墊之上。
  12. 根據申請專利範圍第11項所述的晶片封裝體的形成方法，其中，將該導電板圖案化之步驟包括：在該導電板之該上表面上進行蝕刻制程，以移除一部分的該導電板。
  13. 根據申請專利範圍第12項所述的晶片封裝體的形成方法，其中，在該蝕刻制程期間，該等導電墊用作蝕刻掩模。
  14. 根據申請專利範圍第11項所述的晶片封裝體的形成方法，其中，還包括：在該圖案化導電板之上形成模塑膠以覆蓋該晶片。
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TW201508880A (zh) 2015-03-01
CN104425421A (zh) 2015-03-18
US20150061117A1 (en) 2015-03-05
US20150087115A1 (en) 2015-03-26
CN104425421B (zh) 2017-07-07
US9437457B2 (en) 2016-09-06

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