TWI729895B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI729895B
TWI729895B TW109126008A TW109126008A TWI729895B TW I729895 B TWI729895 B TW I729895B TW 109126008 A TW109126008 A TW 109126008A TW 109126008 A TW109126008 A TW 109126008A TW I729895 B TWI729895 B TW I729895B
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Taiwan
Prior art keywords
insulating material
bonding wire
component
carrier substrate
metal layer
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TW109126008A
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English (en)
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TW202107632A (zh
Inventor
蔡憲聰
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聯發科技股份有限公司
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Abstract

本發明公開一種半導體封裝，包括：載體基板，具有上表面；半導體晶粒，安裝在該上表面上；第一接合引線，將該半導體晶粒連接到該載體基板；絕緣材料，封裝該第一接合引線；部件，安裝在該絕緣材料上，其中該部件包括金屬層；第二接合引線，將該部件的該金屬層連接至該載體基板，其中，該金屬層和該第二接合引線構成電磁干擾遮蔽結構；模塑料，覆蓋該載體基板的該上表面並封裝該半導體晶粒、該部件、該第一接合引線、該第二接合引線和該絕緣材料。

Description

半導體封裝
本發明涉及半導體技術領域，尤其涉及一種半導體封裝。
如本領域中已知的，靜電放電(electrostatic discharge，ESD)和電磁干擾(electromagnetic interference，EMI)是半導體技術領域中的懸而未決的問題。靜電放電可能會損壞積體電路中的半導體和其他電路部件。電磁干擾是由電磁輻射引起的，是電子電路設計中的重要考慮因素。電子電路和攜帶變化的電信號的部件會發出電磁輻射。
業界希望遮蔽敏感部件免受任何電磁輻射源的影響。還期望降低ESD損害半導體封裝中的電路部件的可能性。
有鑑於此，本發明提供一種半導體封裝，以解決上述問題。
根據本發明的第一方面，公開一種半導體封裝，包括：載體基板，具有上表面；半導體晶粒，安裝在該上表面上；第一接合引線，將該半導體晶粒連接到該載體基板；絕緣材料，封裝該第一接合引線；部件，安裝在該絕緣材料上，其中該部件包括金屬層；第二接合引線，將該部件的該金屬層連接至該載體基板，其中，該金屬層和該第二接合引線構成電磁干擾遮蔽結構； 模塑料，覆蓋該載體基板的該上表面並封裝該半導體晶粒、該部件、該第一接合引線、該第二接合引線和該絕緣材料。
根據本發明的第二方面，公開一種半導體封裝，包括：載體基板，具有上表面；半導體晶粒，安裝在該上表面上；第一接合引線，將該半導體晶粒連接到該載體基板；絕緣材料，封裝該第一接合引線；部件，安裝在該絕緣材料上，其中該部件包括金屬層；第二接合引線，將該部件的該金屬層連接至該載體基板，其中，該金屬層和該第二接合引線構成電磁干擾遮蔽結構；第二絕緣材料，封裝該第二接合引線；以及模塑料，覆蓋該載體基板的該上表面並封裝該半導體晶粒、該部件、該第一接合引線、該第二接合引線、該第一絕緣材料和該第二絕緣材料。
根據本發明的第三方面，公開一種半導體封裝，包括：載體基板，具有上表面；半導體晶粒，以倒裝晶片方式安裝在該上表面上；部件，堆疊在該半導體晶粒上，其中，該部件包括金屬層；接合引線，將該部件的該金屬層連接到該載體基板，其中，該金屬層和該第二接合引線構成電磁干擾遮蔽結構；絕緣材料，封裝該接合引線；以及模塑料，覆蓋該載體基板的該上表面並封裝該半導體晶粒、該部件、該接合引線和該絕緣材料。
本發明的半導體封裝由於使用該金屬層和該第二接合引線構成電磁干擾遮蔽結構，因此可以使半導體晶粒遮蔽免受EMI干擾和ESD損害。
1,2,3,4:半導體封裝
10:載體基板
10a:上表面
10b:底表面
20:半導體晶粒
20a:主動面
W1,W2,31,32:接合引線
41,42,WF:絕緣材料
50,MC:模塑料
60:連接元件
110,120:接合指
200:部件
202,702,81,82:黏合層
204:金屬層
210:I/O焊墊
212:連接元件
220:接合焊墊
222:導電通孔
230:突出部
700:間隔物
M1,M2:記憶體晶粒
BF1,BF2,P1,P2:焊墊
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中：圖1是根據本發明的一個實施例的半導體封裝的示意性俯視圖；圖2是沿著圖1中的虛線I-I’截取的示意性截面圖。
圖3是示出根據本發明另一實施例的半導體封裝的示意性截面圖。
圖4是示出根據本發明又一實施例的半導體封裝的示意性截面圖。
圖5是示出根據本發明又一實施例的半導體封裝的示意性截面圖。
圖6是根據本發明的一個實施例的多晶粒半導體封裝的示意性俯視圖。
圖7是沿圖6中的虛線II-II’截取的示意性截面圖。
在以下對本發明的實施例的詳細描述中，參考了附圖，這些附圖構成了本發明的一部分，並且在附圖中透過圖示的方式示出了可以實踐本公開的特定的優選實施例。
對這些實施例進行了足夠詳細的描述，以使所屬技術領域具有通常知識者能夠實踐它們，並且應當理解，可以利用其他實施例，並且可以在不脫離本發明的精神和範圍的情況下進行機械、化學、電氣和程式上的改變。本公開的範圍。因此，以下詳細描述不應理解為限制性的，並且本發明的實施例的範圍僅由所附申請專利範圍限定。
將理解的是，當元件或層稱為在另一元件或層“上”、“連接至” 或“耦接至”另一元件或層時，其可以直接在另一元件或層上、直接連接或耦接至另一元件或層或可以存在元件或層介於兩者中間。相反，當元件稱為“直接在”另一元件或層“上”、“直接連接至”或“直接耦接至”另一元件或層時，則不存在中間元件或層。貫穿全文，相似的數字表示相似的元素。如本文所使用的，術語“和/或”包括一個或複數個相關聯的所列專案的任何和所有組合。
圖1是根據本發明的一個實施例的半導體封裝的示意性俯視圖。圖2是沿著圖1中的虛線I-I’截取的示意性截面圖。如圖1和圖2所示，半導體封裝1包括具有上表面10a和底表面10b的載體基板10。半導體晶粒20直接安裝在上表面10a上。半導體晶粒20具有主動面(active surface)20a，在主動面20a上分佈有複數個輸入/輸出(I/O，input/output)焊墊210。根據說明性實施例，半導體晶粒20可以透過接合引線31電連接到載體基板10的上表面10a上的接合指(bond finger)110。根據說明性實施例，接合引線31可以包括銅、金、銀或任何合適的導電材料。根據說明性實施例，載體基板10可以包括封裝基板或插入(interposer)基板，但是不限於此。
根據說明性實施例，施加絕緣材料41以封裝接合引線31。例如，絕緣材料41可以以矩形或環形施加在半導體晶粒20周圍或周邊，但不限於此。絕緣材料41可以完全覆蓋或包裹接合引線31，並且僅與主動面20a的週邊區域直接接觸。因此，絕緣材料41可以不覆蓋主動面20a的中心區域。然而，應當理解，絕緣材料41可以僅覆蓋接合引線31的一部分。環形的絕緣材料41可以是絕緣材料41。連續或可能不連續。根據說明性實施例，絕緣材料41可以與半導體晶粒20的側壁直接接觸。
根據說明性實施例，絕緣材料41可以包括聚合物、環氧樹脂或樹脂，但是不限於此。塗覆在接合引線31上的絕緣材料41可以固化以為接合引線31提 供額外的機械支撐。絕緣材料41固定接合引線31，並且能夠在隨後的封裝過程中抵抗模制線掃動。根據說明性實施例，絕緣材料40具有低電容率(permittivity)或低介電常數(低k，low-k)，具有低電容率或低介電常數的絕緣材料40可以防止短路以及減輕相鄰引線之間的串擾(crosstalk)。
根據說明性實施例，將部件200直接安裝在絕緣材料41上，突出部230在部件200的邊緣與部件200和絕緣材料41之間的接觸點CP之間的距離為t。部件200絕緣元件41由絕緣材料41和接合引線31支撐。例如，部件200可以是虛設(dummy)矽晶粒、金屬片、陶瓷晶粒、玻璃晶粒或散熱器，但不限於此。部件200可以透過使用黏合層202附接到絕緣材料41和接合引線31。根據說明性實施例，部件200可以具有與載體基板10和載體基板10的形狀共同延伸的矩形形狀。部件200可以與半導體晶粒20完全重疊，例如從俯視方向看半導體晶粒20完全地被部件200覆蓋。
根據說明性實施例，部件200可以是虛設晶粒，例如虛設矽晶粒，在虛設矽晶粒的一側上塗覆有金屬層204。金屬層204是連續的金屬層(連續金屬層)，例如鋁層，其完全覆蓋部件200的上表面，從而形成EMI遮蔽結構的蓋(lid)，或EMI遮蔽蓋結構。連續金屬層例如是可以一整塊金屬層，沒有分塊和斷開。金屬層204透過接合引線32電耦接至載體基板10。接合引線32接合至設置在載體基板10的上表面10a上的各個接合指120，並且可以電耦接至接地平面124。在一個實施例中，接合指120也可以為連續的圍繞半導體晶粒設置的閉合的接合環或接地環。因此，接合引線32和金屬層204接地。部件200的金屬層204和接合引線32構成法拉第籠(Faraday cage)，該法拉第籠將半導體晶粒20遮蔽免受EMI干擾。 根據另一實施例，接合引線32可以接合至設置在載體基板10的上表面10a上的接地環。接合引線32圍繞晶粒20的週邊佈置以實現更好的EMI干擾效果。其中接地環可以是在上表面10a上的金屬環，並且電連接到接地平面124，以增加EMI干擾 效果。
在先前技術中，在封裝的製造期間，常常會遇到一些靜電，這些靜電常常會對封裝中電路及佈線產生干擾和損害，例如在施加模塑料(例如模塑料50)進行封裝時，使用的設備的軌道等部件上的靜電可能會損害晶粒等。而本發明的實施例中，先形成了金屬層204和接合引線32構成的電磁干擾遮蔽結構保護半導體晶粒20，因此在隨後的製程中，例如形成模塑料50的製程中，外部的設備所發出的靜電可以由電磁干擾遮蔽結構遮蔽，這樣就可以避免或減少了靜電干擾。此外，使用本發明是有利的，因為在封裝組裝過程的早期，部件200和接合引線32可以保護半導體晶粒20免受ESD損害。此外，在封裝製造完成後，金屬層204和接合引線32構成的電磁幹擾遮蔽結構同樣可以保護半導體晶粒20免受EMI干擾和ESD損害。
根據說明性實施例，可以在部件200和半導體晶粒20之間設置間隔物(spacer)700。可以透過使用黏合層702將間隔物700黏附至半導體晶粒20的主動面20a。間隔物700可以是虛設晶粒或具有匹配的熱膨脹係數(coefficient of thermal expansion，CTE)的任何合適的材料，但不限於此。間隔件700的厚度是可調節的。在一些實施例中，間隔物700可以更厚，使得部件200不與絕緣材料41和接合引線31直接接觸。在一些實施例中，間隔物700可以省去，如圖3所示。 間隔物700可以幫助支撐部件200，以增加半導體封裝結構的機械強度和穩定性；並且間隔物700幫助晶粒散熱，以及在封裝熱膨脹時為封裝提供額外的剛性，以抑制封裝的翹曲、變形等問題。
根據說明性實施例，模塑料50形成在載體基板10的上表面10a上以密封或封裝接合引線31和32、絕緣材料41、部件200、間隔物700和半導體晶粒20。 在說明性實施例中，模塑料50可包括環氧樹脂和填充材料，但不限於此。根據說明性實施例，絕緣材料41可以具有與模塑料50相同的環氧樹脂(epoxy)組成， 但是沒有填充材料或填充材料的含量較低。根據說明性實施例，絕緣材料41和模塑料50具有不同的成分。根據說明性實施例，絕緣材料41包含小於50ppm的鹵素含量，以防止接合引線31腐蝕。在形成模塑料50之後，可以在底表面10b上形成諸如焊球的連接元件60。絕緣材料41與模塑料50在不同的製程中形成，並且可以使用不同的形成方式形成。這樣在形成絕緣材料41時(例如使用點膠等方式)減少或避免產生靜電，以保護半導體晶粒20；在形成模塑料50時由金屬層204和接合引線32構成的電磁干擾遮蔽結構保護半導體晶粒20。
圖4是示出根據本發明的又一個實施例的半導體封裝的示意性截面圖，其中，相似的層，區域或元件由相似的數字或標籤表示。如圖4所示，半導體封裝2包括具有上表面10a和底表面10b的載體基板10。半導體晶粒20安裝在上表面10a上。半導體晶粒20具有主動面20a，在該主動面上分佈有複數個I/O焊墊210。根據說明性實施例，半導體晶粒20可以透過接合引線31電連接到載體基板10的上表面10a上的接合指110。根據說明性實施例，接合引線31可以包括銅、金銀或任何合適的導電材料。根據說明性實施例，載體基板10可以包括封裝基板或插入基板，但是不限於此。
根據說明性實施例，施加絕緣材料41到接合引線31。例如，絕緣材料41可以以矩形、環形的形狀被施加在半導體晶粒20周圍或周邊，但是不限於此。絕緣材料41可以完全覆蓋接合引線31，並且僅與主動面20a的週邊區域直接接觸。因此，絕緣材料41可以不覆蓋主動面20a的中心區域。然而，應當理解，絕緣材料41可以僅覆蓋接合引線31的一部分。環形的絕緣材料41可以是連續或不連續的。根據說明性實施例，絕緣材料41可以與半導體晶粒20的側壁直接接觸。
根據說明性實施例，絕緣材料41可以包括聚合物、環氧樹脂或樹脂，但是不限於此。塗覆在接合引線31上的絕緣材料41可以固化以為接合引線31提 供額外的機械支撐。絕緣材料41固定接合引線31，並且能夠在隨後的封裝過程中抵抗模制引線掃動。根據說明性實施例，絕緣材料41具有低介電常數或低介電常數(low-k)，其可以防止短路並減輕相鄰導線之間的串擾。
根據說明性實施例，將部件200直接安裝在絕緣材料41上，突出部230在部件200的邊緣與部件200和絕緣材料41之間的接觸點CP之間的距離為t。部件200絕緣元件41由絕緣材料41和接合引線31支撐。例如，部件200可以是虛設矽晶粒、金屬片、陶瓷晶粒、玻璃晶粒或散熱器，但不限於此。部件200可以透過使用黏合層202附接到絕緣材料41和接合引線31。根據說明性實施例，部件200可以具有與載體基板10和載體基板10的形狀共同延伸的矩形形狀。部件200可以與半導體晶粒20完全重疊。
根據說明性實施例，部件200可以是虛設晶粒，例如虛設矽晶粒，其包括用作EMI遮蔽層的金屬層204和在金屬層204上的黏合層202。部件200可以透過使用黏合層202附接到絕緣材料41和接合引線31。部件200包括佈置在部件200的上表面上的接合焊墊(或環)220。接合引線32接合至接合焊墊220。接合焊墊220透過導電通孔222電連接到金屬層202。
根據說明性實施例，可以施加絕緣材料42到接合引線32。例如，絕緣材料42可以以矩形或環形的形狀施加在絕緣材料41和接合引線31周圍。絕緣材料42絕緣層42可以完全覆蓋接合引線32，並且與主動面20a、間隔物700、部件200的周邊和底面直接接觸。可以理解，絕緣材料42可以僅覆蓋接合引線31的一部分。環形的絕緣材料42可以是連續的或可以是不連續的。絕緣材料41和絕緣材料42可以具有不同的成分。圖4所示的實施例同樣具有如圖2或圖3所示的效果，保護半導體晶粒20。
圖5是示出根據本發明的又一個實施例的半導體封裝的示意性截面圖，其中，相同的層、區域或元件由相同的數字或標籤表示。如圖5所示，同樣， 半導體封裝3包括具有上表面10a和底表面10b的載體基板10。根據說明性實施例，載體基板10可以包括封裝基板或插入基板，但是不限於此。半導體晶粒20以倒裝晶片的方式安裝在上表面10a上，其主動面20a透過複數個連接元件212耦接到載體基板10的上表面10a。根據說明性實施例，連接元件212可以包括銅、金、銀或任何合適的導電材料。例如，連接元件212可以是銅柱或銅凸塊，但不限於此。
根據說明性實施例，部件200直接安裝在半導體晶粒20的後表面20b上。例如，部件200可以是虛設矽晶粒、金屬片、陶瓷晶粒、玻璃晶粒或散熱器，但不限於此。可以透過使用黏合層202將部件200附接到半導體晶粒20。根據說明性實施例，部件200可以是虛設晶粒，例如虛設矽晶粒，其一側上塗覆有金屬層204。金屬層204是連續的金屬層，例如鋁層，其完全覆蓋部件200的上表面，從而形成EMI遮蔽結構的蓋。金屬層204透過接合引線32電耦接至載體基板10。 接合引線32接合至設置在載體基板10的上表面10a上的各個接合指120，並且可以電耦接至接地平面124。因此，金屬層204接地。部件200的金屬層204和接合引線32構成法拉第籠，該法拉第籠將半導體晶粒20遮蔽免受EMI干擾。根據另一實施例，接合引線32可以接合至設置在載體基板10的上表面10a上的接地環。接合引線32圍繞晶粒20的週邊佈置以實現更好的EMI干擾效果。
根據說明性實施例，可以施加接合引線32到絕緣材料42。例如，絕緣材料42可以以矩形或環形的形狀施加在絕緣材料41和接合引線31周圍。絕緣材料42絕緣材料42可以完全覆蓋接合引線32，並且與半導體晶粒20的周邊和主動面20a，連接元件212以及部件200的周邊直接接觸。可以理解，絕緣材料42可以僅覆蓋絕緣材料42。環形的絕緣材料42可以是連續的，也可以是不連續的。 絕緣材料42可以填充到半導體晶粒20的主動面20a和載體基板10的上表面10a之間的間隙中。因此，可以省去常規的底部填充分配過程。圖5所示的實施例同樣 具有如圖2或圖3或圖4所示的效果，保護半導體晶粒20。此外在本發明圖5的實施例中，位於載體基板10和半導體晶粒20之間的絕緣材料和位於接合引線32內的絕緣材料可以在同一製程步驟中形成，因此兩處的絕緣材料42是一體的(或一個整體的或一體成形的)。本發明的實施例可以減少製程步驟，提高生產效率。
請參考圖6及圖7，圖6為根據本發明的一實施例的多晶粒半導體封裝的立體俯視圖。圖7是沿著圖6中的虛線II-II’截取的示意性截面圖。如圖6和圖7所示，半導體封裝件4包括具有上表面10a和底表面10b的載體基板10。根據說明性實施例，載體基板10可以包括封裝基板或插入基板，但是不限於此。諸如系統單晶片(System on a Chip，SoC)之類的半導體晶粒20以倒裝晶片的方式安裝在上表面10a上，其主動面20a透過複數個連接元件212耦接到載體基板10的上表面10a。根據說明性實施例，連接元件212可以包括銅、金、銀、焊料或任何合適的導電材料。例如，連接元件212可以是銅柱或銅凸塊，但不限於此。
根據說明性實施例，至少記憶體晶粒M1透過使用黏合層81堆疊並安裝在半導體晶粒20的後表面20b上。例如，記憶體晶粒M1可以是4MB串列(serial)快閃(flash)RAM晶粒，但是不限於此。根據說明性實施例，至少記憶體晶粒M2可以透過使用黏合層82堆疊並安裝在記憶體晶粒M1上。例如，記憶體晶粒M2可以是4MB的虛擬(Pseudo)SRAM晶粒，但是不限於此。根據說明性實施例，記憶體晶粒M1包括焊墊P1，焊墊P1透過接合引線W1電連接到載體基板10的上表面10a上的各個焊墊BF1。根據說明性實施例，記憶體晶粒M2包括焊墊P2，焊墊P2透過接合引線W2電連接到載體基板10的上表面10a上的各個焊墊BF2。應當理解，圖6和圖7中的3D堆疊配置僅用於說明目的。
根據說明性實施例，可以將諸如具有適當流動性的可流動樹脂的絕緣材料WF施加到接合引線W1和W2。例如，絕緣材料WF可以沿著記憶體晶粒 M1和記憶體晶粒M2的周邊施加。絕緣材料WF可以完全覆蓋接合引線W1和W2。可以理解，絕緣材料WF可以僅覆蓋接合引線W1和W2的一部分。當將絕緣材料WF施加到接合引線W1和W2上時，絕緣材料WF也流入到半導體晶粒20和載體基板10之間的毛細效應中，使得絕緣材料WF可以圍繞並保護連接元件212。 與現有技術相比，由於可以省略傳統的底部填充製程，因此可以將載體基板10的上表面10a上的焊墊BF1和BF2設置得更靠近半導體晶粒20。因此，半導體封裝4的尺寸可以更緊湊。根據一些實施例，可以沿著半導體晶粒20的周邊分配額外的絕緣材料WF，以確保半導體晶粒20和載體基板10之間的間隙完全地底部填充。
根據說明性實施例，模塑料MC形成在載體基板10的上表面10a上，以封裝絕緣材料WF、記憶體晶粒M1、記憶體晶粒M2、半導體晶粒20和絕緣材料WF的上表面10a。根據說明性實施例，模塑料MC可以包括環氧樹脂和填充材料，但不限於此。根據說明性實施例，絕緣材料WF可以具有與模塑料MC相同的環氧組成，但是沒有填充材料或填充材料的含量較低。根據說明性實施例，絕緣材料WF和模塑料MC具有不同的組成。根據說明性實施例，絕緣材料WF包含小於50ppm的鹵素含量，以防止接合引線W1和W2的腐蝕。在形成模塑料MC之後，可以在底表面10b上形成諸如焊球的連接元件60。先前技術中，位於載體基板和半導體晶粒之間的絕緣材料和位於接合引線W1和W2內的絕緣材料是在不同的製程步驟中形成的，這樣製程步驟較多，製程較複雜。在本發明圖6和圖7的實施例中，位於載體基板10和半導體晶粒20之間的絕緣材料和位於接合引線W1和W2內的絕緣材料可以在同一製程步驟中形成，因此兩者的絕緣材料WF是一體的(或一個整體的或一體成形的)。本發明的實施例可以減少製程步驟，省去常規的底部填充分配過程(例如常規的載體基板和半導體晶粒之間的填充過程)，提高生產效率。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1:半導體封裝
10:載體基板
10a:上表面
20:半導體晶粒
20a:主動面
31,32:接合引線
41:絕緣材料
110,120:接合指
200:部件
204:金屬層

Claims (11)

  1. 一種半導體封裝，包括：載體基板，具有上表面；半導體晶粒，安裝在該上表面上；第一接合引線，將該半導體晶粒連接到該載體基板；第一絕緣材料，封裝該第一接合引線；部件，安裝在該第一絕緣材料上，其中該部件包括金屬層；第二接合引線，將該部件的該金屬層連接至該載體基板，其中，該金屬層和該第二接合引線構成電磁干擾遮蔽結構；第二絕緣材料，封裝該第二接合引線；以及模塑料，覆蓋該載體基板的該上表面並封裝該半導體晶粒、該部件、該第一接合引線、該第二接合引線、該第一絕緣材料和該第二絕緣材料。
  2. 如請求項1之半導體封裝，其中，該第二絕緣材料完全覆蓋該第二接合引線，並且與該部件的周圍和底表面直接接觸。
  3. 如請求項1之半導體封裝，其中，該第一絕緣材料和該第二絕緣材料具有不同的成分。
  4. 如請求項1之半導體封裝，其中，該部件透過黏合層附接到該第一絕緣材料。
  5. 如請求項1之半導體封裝，其中，該金屬層是連續金屬層，該連續金屬層完全覆蓋該部件的表面從而形成該電磁干擾遮蔽結構的蓋。
  6. 如請求項1之半導體封裝，其中，該第二接合引線電耦接至該載體基板的該上表面上的接地環。
  7. 如請求項1之半導體封裝，其中，該第二接合引線和該金屬層接地。
  8. 如請求項1之半導體封裝，其中，該第一絕緣材料以矩形環狀圍繞 該半導體晶粒設置。
  9. 如請求項1之半導體封裝，其中，該第一絕緣材料和該模塑料具有不同的成分。
  10. 如請求項1之半導體封裝，其中，該第一絕緣材料完全覆蓋該第一接合引線並且與該半導體晶粒的主動面的週邊區域直接接觸。
  11. 如請求項1之半導體封裝，還包括：間隔物，在該部件與該半導體晶粒之間。
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