TW201807796A - 電子封裝結構及其製法 - Google Patents

電子封裝結構及其製法 Download PDF

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Publication number
TW201807796A
TW201807796A TW105127017A TW105127017A TW201807796A TW 201807796 A TW201807796 A TW 201807796A TW 105127017 A TW105127017 A TW 105127017A TW 105127017 A TW105127017 A TW 105127017A TW 201807796 A TW201807796 A TW 201807796A
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Taiwan
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carrier
electronic
item
patent application
electronic component
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TW105127017A
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TWI611542B (zh
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邱志賢
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矽品精密工業股份有限公司
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Priority to TW105127017A priority Critical patent/TWI611542B/zh
Priority to CN201610785726.XA priority patent/CN107785277B/zh
Priority to US15/352,822 priority patent/US10573623B2/en
Application granted granted Critical
Publication of TWI611542B publication Critical patent/TWI611542B/zh
Publication of TW201807796A publication Critical patent/TW201807796A/zh
Priority to US16/740,631 priority patent/US20200152607A1/en

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Abstract

一種電子封裝結構，係包括：具有開口的第一承載件、設於該第一承載件上之第一電子元件與複數導電元件、結合至該些導電元件上之第二承載件、設於該第二承載件上並容置於該開口中之第二電子元件、以及形成於該第一承載件與該第二承載件上且包覆該第一電子元件、第二電子元件與導電元件之包覆層，以藉由將該第二電子元件容置於該開口中，而降低該電子封裝結構的高度。本發明復提供該電子封裝結構之製法。

Description

電子封裝結構及其製法
本發明係關於一種封裝結構，特別是關於一種應用於堆疊之電子封裝結構及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢發展，為因應此趨勢，半導體封裝業界遂開發各態樣的堆疊封裝(package on package，簡稱PoP)技術，以期能符合輕薄短小與高密度的要求。
如第1圖所示，係為習知封裝堆疊結構1的剖視示意圖。如第1圖所示，該封裝堆疊結構1包括：具有相對之第一表面10a及第二表面10b之第一基板10；結合於該第一基板10上之第一半導體晶片11；形成於該第一基板10上之銲錫柱13；形成於該第一基板10上以包覆該第一半導體晶片11與銲錫柱13之第一封裝膠體16；設於該第二表面10b上之銲球15；藉由銲錫柱13疊設於該第一基板10上之第二基板14；以打線方式結合於該第二基板14上之第二半導體晶片12；以及形成於該第二基板14上以包 覆該第二半導體晶片12之第二封裝膠體17。
惟，習知封裝堆疊結構1中，並無空間增設被動元件，致使電性難以最佳化。若欲增設被動元件，該被動元件之高度通常極高(一般被動元件均高於第一與第二半導體晶片11,12)，致使該封裝堆疊結構1之高度會因增設該被動元件而大幅增加(例如，被動元件設於該第一基板10上，該銲錫柱13之高度會增加；被動元件設於該第二基板14上，該第二封裝膠體17之高度會增加)，導致該封裝堆疊結構1無法符合輕薄短小之需求。
因此，如何克服上述習知技術的種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種電子封裝結構，係包括：第一承載件，係具有開口；第一電子元件，係設於該第一承載件上並電性連接該第一承載件；複數導電元件，係設於該第一承載件上並電性連接該第一承載件；第二承載件，係結合至該些導電元件上以電性連接至該第一承載件；第二電子元件，係設於該第二承載件上並容置於該開口中；以及包覆層，係形成於該第一承載件與該第二承載件上且包覆該第一電子元件、第二電子元件與導電元件。
本發明復提供一種電子封裝結構之製法，係包括：提供一具有開口之第一承載件，其中，該第一承載件上接置並電性連接有第一電子元件；提供一第二承載件，以將該 第一承載件透過複數導電元件結合並電性連接至該第二承載件上，且令至少一第二電子元件容置於該第一承載件之開口中並設於該第二承載件上；以及形成包覆層於該第一承載件與該第二承載件上，且令該包覆層包覆該第一電子元件、第二電子元件與該些導電元件。
前述之電子封裝結構及其製法中，該開口位於該第一承載件之邊緣內。
前述之電子封裝結構及其製法中，該開口位於該第一承載件之側邊。
前述之電子封裝結構及其製法中，該開口位於該第一承載件之角落處。
前述之電子封裝結構及其製法中，該第一電子元件係為封裝件、主動元件、或被動元件。
前述之電子封裝結構及其製法中，該導電元件係為銲球、銅核心球、金屬件或電路板。
前述之電子封裝結構及其製法中，該第一電子元件係位於該第一承載件與該第二承載件之間。
前述之電子封裝結構及其製法中，該第二電子元件係為封裝件、主動元件、被動元件或其三者組合。
前述之電子封裝結構及其製法中，該第一承載件及第二承載件係為線路結構、導線架、晶圓、或具有金屬佈線之載板。
前述之電子封裝結構及其製法中，該第二電子元件係電性連接該第一承載件及/或第二承載件。
前述之電子封裝結構及其製法中，該第二承載件包含至少一板體，以作為電磁干擾屏蔽。例如，該第二電子元件係藉由導電體電性連接至該第一承載件。
另外，前述之電子封裝結構及其製法中，復包括於形成該包覆層之前，形成用以包覆該第一電子元件之封裝層。
由上可知，本發明之電子封裝結構及其製法中，主要藉由將該第二電子元件(如被動元件)容置於該第一承載件之開口中，以減少該電子封裝結構的高度，而能符合輕薄短小之需求。
1‧‧‧封裝堆疊結構
10‧‧‧第一基板
10a,26a‧‧‧第一表面
10b,26b‧‧‧第二表面
11‧‧‧第一半導體晶片
12‧‧‧第二半導體晶片
13‧‧‧銲錫柱
14‧‧‧第二基板
15‧‧‧銲球
16‧‧‧第一封裝膠體
17‧‧‧第二封裝膠體
2,4‧‧‧電子封裝結構
20‧‧‧第一承載件
20a‧‧‧第一側
20b‧‧‧第二側
20c‧‧‧邊緣
200‧‧‧線路層
201‧‧‧開口
21,21’,21”‧‧‧第一電子元件
210‧‧‧導電凸塊
22‧‧‧第二電子元件
220‧‧‧導電體
23,23’,23”‧‧‧導電元件
23a‧‧‧銲錫材料
24,24’‧‧‧第二承載件
240,240’‧‧‧電性接觸墊
241‧‧‧板體
25‧‧‧支撐件
26‧‧‧包覆層
47‧‧‧封裝層
500‧‧‧側面線路
540‧‧‧線路
第1圖係為習知封裝堆疊結構之剖面示意圖；第2A至2C圖係為本發明之電子封裝結構之製法第一實施例的剖面示意圖；其中，第2B’圖係為第2B圖之另一實施例，第2C’及2C”圖係為第2C圖之其它實施例；第3A至3D圖係為第2A圖之第一承載件之不同態樣之上視示意圖；第4圖係為本發明之電子封裝結構之第二實施例之剖面示意圖；以及第5A及5B圖係為第2C’圖之不同態樣之剖面示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2C圖係為本發明之電子封裝結構2之製法第一實施例的剖面示意圖。
如第2A圖所示，提供一第一承載件20，其具有相對之第一側20a與第二側20b及連通該第一側20a與第二側20b之至少一開口201，且於該第一承載件20之第一側20a上設有至少一第一電子元件21與複數如銲球(solder ball)之導電元件23，並於該第一承載件20之第二側20b上設有複數第一電子元件21’,21”。
於本實施例中，該第一承載件20係為具有核心層或無核心層(coreless)之線路結構(如封裝基板substrate)，其具有複數線路層200，如扇出(fan out)型重佈線路層(redistribution layer，簡稱RDL)。應可理解地，該第一承載件20亦可為其它承載晶片之承載件，如導線架 (leadframe)、晶圓(wafer)、或其他具有金屬佈線(routing)之載板(如低溫共燒陶瓷(low temperature cofired ceramic，簡稱LTCC)或鐵氧體(Ferrite))，並不限於上述。
再者，該開口201的數量可為一個或多個，其位置可依需求而定或配合該線路層200之佈設範圍而改變，例如，位於該第一承載件20之中心、周圍或角落，以提高該第一承載件20的面積利用率。具體地，如第3A圖所示，係為該第一承載件20之上視示意圖，該開口201完全位於該第一承載件20之邊緣20c內；如第3B圖所示，該開口201之一側連通該第一承載件20之邊緣20c，即位於該第一承載件20之側邊；如第3C圖所示，該開口201之兩側連通該第一承載件20之邊緣20c，即位於該第一承載件20之角落處；如第3D圖所示，該開口201之三側連通該第一承載件20之邊緣20c，即移除該第一承載件20之其中一側面部分之材質。
又，該第一電子元件21,21’,21”係為封裝件(如標號21’)、主動元件(如標號21)、被動元件(如標號21”)或其三者組合等，其中，該封裝件係例如晶片級封裝(Chip Scale Package，簡稱CSP)，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第一電子元件21,21’係藉由複數如銲錫材料之導電凸塊210以覆晶方式設於該線路層200上並電性連接該線路層200；或者，該第一電子元件21,21’可藉由複數銲線(圖略)以打線方式電性連接該線路層200。亦或，該第一電子元件21” 可直接接觸該線路層200。然而，有關該第一電子元件電性連接該第一承載件20之方式不限於上述。
另外，亦提供一其上設有至少一第二電子元件22之第二承載件24，該第二承載件24係例如為導線架(leadframe)，其包含複數相分離之電性接觸墊240,240’，使該第二電子元件22結合至該電性接觸墊240’上以電性連接該第二承載件24。應可理解地，該第二承載件24亦可為其它承載晶片之承載件，例如，具有核心層或無核心層(coreless)之線路結構、晶圓(wafer)、或其他具有金屬佈線(routing)之載板(如低溫共燒陶瓷(low temperature cofired ceramic，簡稱LTCC)、鐵氧體(Ferrite))，並不限於上述。
所述之第二承載件24可選擇性地設於一如膠帶(tape)之支撐件25上，且該第二電子元件22係為封裝件、主動元件、被動元件或其三者組合等，其中，該封裝件係例如晶片級封裝(CSP)，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。於本實施例中，該第二電子元件22係以被動元件為例。
如第2B圖所示，將該第一承載件20以該些導電元件23結合至第二承載件24之該電性接觸墊240上，使該第一承載件20之線路層200電性連接該第二承載件24，且令該第二電子元件22對應容置於該第一承載件20之開口201中。
於另一實施例中，如第2B’圖所示，亦可先將該第一 承載件20與該第二承載件24相堆疊後，再將該第二電子元件22容置於該開口201中並設於該電性接觸墊240’上。
如第2C圖所示，形成一包覆層26於該第一承載件20與該第二承載件24(或該支撐件25)上並填入該開口201中，使該包覆層26包覆該些第一電子元件21,21’,21”、該第二電子元件22、及該些導電元件23。之後，移除該支撐件25。
於本實施例中，形成該包覆層26之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材(molding compound)，且該包覆層26具有相對之第一表面26a與第二表面26b，使該第二承載件24嵌設於該包覆層26之第一表面26a，且該些電性接觸墊240外露於該包覆層26之第一表面26a(例如，該些電性接觸墊240之表面齊平該包覆層26之第一表面26a)，俾供後續於該些電性接觸墊240之外露表面上形成有如銲球之銲錫材料(圖略)，以接置於如電路板或另一線路板之電子裝置。
再者，如第2C’圖所示，該導電元件23’可為環狀電路板(ring tape circuit board)或長條狀電路板，其藉由銲錫材料23a結合於該線路層200與該電性接觸墊240上，以增加該第一承載件20與該第二承載件24之間的間距(gap)，使該第一與第二承載件20,24之間有足夠空間接置該第一電子元件21。或者，如第2C”圖所示，該導電元件23”亦可為銅核心球(Cu core ball)或如銅材或金材之金屬件(如柱狀、塊狀或針狀)等。
又，如第2C’圖所示，該第二電子元件22亦可藉由如銲線(bonding wire)或夾條(clip bar)之導電體220電性連接至該第一承載件20之線路層200。於其它態樣中，如第5A圖所示，該導電體220可電性連接該第一承載件20之線路層200與該第二承載件24之線路540，且該線路540係電性連接該電性接觸墊240’；或者，如第5B圖所示，該導電體220可電性連接該第一承載件20之側面線路500與該第二電子元件22，其中，該導電體220例如為導電膠或銲錫材料。
另外，如第2C”圖所示，該第二承載件24’復包含至少一板體241，其可與該些電性接觸墊240,240’相分離或相連結，並可接地，以提供電磁干擾(electromagnetic interference，簡稱EMI)屏蔽(shielding)的效果。
因此，本發明係藉由將接置在第二承載件24之該第二電子元件22(如被動元件)容置於該第一承載件20之開口201中，以減少該電子封裝結構2的高度，而能符合輕薄短小之需求。
再者，該第二承載件24’不僅能提供EMI屏蔽的效果，且若該第二承載件24,24’為導線架或金屬板，可提高該電子封裝結構2之散熱效率。
又，一般主動元件與被動元件係設於同一基板上，因而可藉由基板之線路直接相互電性連接。然而，本發明之電子封裝結構2由於該第二電子元件22(被動元件)之設置與該第一電子元件21(主動元件)之設置係分別位於不 同承載件上，因而無法以同一承載件之線路直接電性連接，故藉由該導電體220之設計，可以減少該第一承載件20與該第二承載件24之佈線範圍(例如減少I/O數)，且減少直流阻抗與交流阻抗。若如第2C圖所示，該第一電子元件21係藉由該導電元件23與電性接觸墊240，再經由該第二承載件24之線路(圖略)電性連接該電性接觸墊240’與第二電子元件22，其中，該電性接觸墊240,240’之間的線路(圖略)長於第5A圖所示之線路540。
第4圖係為本發明之電子封裝結構4之第二實施例的剖面示意圖。本實施例與第一實施例大致相同，主要之差異在於封裝製程，故以下僅說明相異處，而不再贅述相同處。
如第4圖所示，於第2B圖之製程之前，可先於該第一承載件20之第二側20b上形成用以包覆該些第一電子元件21’,21”之封裝層47，且該封裝層47未填滿該開口201，之後才進行第2B至2C圖之製程，以得到如第4圖所示之電子封裝結構4。
於本實施例中，形成該封裝層47之材質係為聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、環氧樹脂(expoxy)或封裝材(molding compound)。應可理解地，該包覆層26之材質與該封裝層47之材質可相同或不相同。
透過前述製程，本發明提供一種電子封裝結構2,4，其包括：一第一承載件20、複數第一電子元件21,21’,21”、複數導電元件23,23’,23”、一第二承載件24,24’、一第 二電子元件22以及一包覆層26。
所述之第一承載件20係具有至少一開口201。
所述之第一電子元件21,21’,21”係設於該第一承載件20上並電性連接該第一承載件20。
所述之導電元件23,23’,23”係設於該第一承載件20上並電性連接該第一承載件20。
所述之第二承載件24,24’係結合至該些導電元件23上以堆疊並電性連接至該第一承載件20。
所述之第二電子元件22係設於該第二承載件24,24’上並容置於該開口201中。
所述之包覆層26係形成於該第一承載件20與該第二承載件24,24’上且包覆該第一電子元件21(及該第一電子元件21’,21”)、第二電子元件22與導電元件23,23’,23”。
於一實施例中，該開口201完全位於該第一承載件20之邊緣20c內。
於一實施例中，該開口201位於該第一承載件20之一側邊(其中一邊緣20c)。
於一實施例中，該開口201位於該第一承載件20之角落處。
於一實施例中，該第一電子元件21,21’,21”係為封裝件、主動元件、被動元件或其三者組合。
於一實施例中，該導電元件23,23’,23”係為銲球、銅核心球、金屬件或電路板。
於一實施例中，該第一電子元件21係位於該第一承載件20與該第二承載件24之間。
於一實施例中，該第二電子元件22係為封裝件、主動元件、被動元件或其三者組合。
於一實施例中，該第二電子元件22係電性連接該第一承載件20及/或第二承載件24,24’。
於一實施例中，該第一承載件20及第二承載件24,24’係為線路結構、導線架、晶圓、或具有金屬佈線之載板。
於一實施例中，該第二承載件24’包含至少一板體241，以作為電磁干擾屏蔽。
於一實施例中，該電子封裝結構4復包括包覆部分該第一電子元件21’,21”之封裝層47。
綜上所述，本發明之電子封裝結構及其製法，係藉由該開口之設計，使該第二電子元件(如被動元件)能容置於該開口中，以降低該電子封裝結構的高度，而能符合輕薄短小之需求。
再者，該第二承載件不僅能提供EMI屏蔽的效果，且能提高該電子封裝結構之散熱效率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧電子封裝結構
20‧‧‧第一承載件
201‧‧‧開口
21,21’,21”‧‧‧第一電子元件
22‧‧‧第二電子元件
23‧‧‧導電元件
24‧‧‧第二承載件
240,240’‧‧‧電性接觸墊
26‧‧‧包覆層
26a‧‧‧第一表面
26b‧‧‧第二表面

Claims (24)

  1. 一種電子封裝結構，係包括：第一承載件，係具有開口；第一電子元件，係接置並電性連接至該第一承載件上；複數導電元件，係接置並電性連接至該第一承載件上；第二承載件，係結合至該些導電元件上以電性連接至該第一承載件；第二電子元件，係設於該第二承載件上並容置於該第一承載件之開口中；以及包覆層，係形成於該第一承載件與該第二承載件上且包覆該第一電子元件、第二電子元件與導電元件。
  2. 如申請專利範圍第1項所述之電子封裝結構，其中，該開口位於該第一承載件之邊緣內。
  3. 如申請專利範圍第1項所述之電子封裝結構，其中，該開口位於該第一承載件之側邊。
  4. 如申請專利範圍第1項所述之電子封裝結構，其中，該開口位於該第一承載件之角落處。
  5. 如申請專利範圍第1項所述之電子封裝結構，其中，該第一電子元件及第二電子元件係為封裝件、主動元件、或被動元件。
  6. 如申請專利範圍第1項所述之電子封裝結構，其中，該導電元件係為銲球、銅核心球、金屬件或電路板。
  7. 如申請專利範圍第1項所述之電子封裝結構，其中，該第一承載件及第二承載件係為線路結構、導線架、晶圓、或具有金屬佈線之載板。
  8. 如申請專利範圍第1項所述之電子封裝結構，其中，該第一電子元件係位於該第一承載件與該第二承載件之間。
  9. 如申請專利範圍第1項所述之電子封裝結構，其中，該第二電子元件係電性連接該第一承載件及/或第二承載件。
  10. 如申請專利範圍第9項所述之電子封裝結構，其中，該第二電子元件係藉由導電體電性連接至該第一承載件。
  11. 如申請專利範圍第1項所述之電子封裝結構，其中，該第二承載件包含至少一板體，以作為電磁干擾屏蔽。
  12. 如申請專利範圍第1項所述之電子封裝結構，復包括包覆該第一電子元件之封裝層。
  13. 一種電子封裝結構之製法，係包括：提供一具有開口之第一承載件，其中，該第一承載件上接置並電性連接有第一電子元件；提供一第二承載件，以將該第一承載件透過複數導電元件結合並電性連接至該第二承載件上，且令至少一第二電子元件容置於該第一承載件之開口中並設於該第二承載件上；以及形成包覆層於該第一承載件與該第二承載件上，以令該包覆層包覆該第一電子元件、第二電子元件與該些 導電元件。
  14. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該開口位於該第一承載件之邊緣內。
  15. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該開口位於該第一承載件之側邊。
  16. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該開口位於該第一承載件之角落處。
  17. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該第一電子元件及第二電子元件係為封裝件、主動元件、或被動元件。
  18. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該導電元件係為銲球、銅核心球、金屬件或電路板。
  19. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該第一承載件及第二承載件係為線路結構、導線架、晶圓、或具有金屬佈線之載板。
  20. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該第一電子元件係位於該第一承載件與該第二承載件之間。
  21. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該第二電子元件係電性連接該第一承載件及/或第二承載件。
  22. 如申請專利範圍第21項所述之電子封裝結構之製法，其中，該第二電子元件係藉由導電體電性連接至該第一 承載件。
  23. 如申請專利範圍第13項所述之電子封裝結構之製法，其中，該第二承載件包含至少一板體，以作為電磁干擾屏蔽。
  24. 如申請專利範圍第13項所述之電子封裝結構之製法，復包括於形成該包覆層之前，形成用以包覆該第一電子元件之封裝層。
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