TW202306079A - 包括堆疊晶片結構的半導體封裝 - Google Patents
包括堆疊晶片結構的半導體封裝 Download PDFInfo
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- TW202306079A TW202306079A TW111124510A TW111124510A TW202306079A TW 202306079 A TW202306079 A TW 202306079A TW 111124510 A TW111124510 A TW 111124510A TW 111124510 A TW111124510 A TW 111124510A TW 202306079 A TW202306079 A TW 202306079A
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Abstract
本發明提供一種半導體封裝,包含:封裝基底,包含具有接合襯墊的上部表面;下部半導體晶片,安置於封裝基底的上部表面上,其中下部半導體晶片的上部表面包含含有連接襯墊的連接邊緣區域及包含含有虛設凸塊的壩結構的開放邊緣區域;接合線,具有下部半導體晶片的上部表面上方的第一高度且連接接合襯墊及連接襯墊;上部半導體晶片,使用晶片間接合層安置於下部半導體晶片的上部表面上;以及模製部分,位於封裝基底上且實質上包圍下部半導體晶片及上部半導體晶片。
Description
相關申請案的交叉引用
本申請案主張2021年7月22日在韓國智慧財產局申請的韓國專利申請案第10-2021-0096420號的優先權,所述申請案的主題以全文引用的方式併入本文中。
本發明概念大體上是關於半導體封裝,且更特定言之,是關於包含堆疊晶片結構的半導體封裝。
電子裝置的消費者需求顯著擴增且變得愈來愈有競爭性。因此,對於較大功能性、減小大小及重量以及較長電池供電操作壽命的需求增加。為了解決此類需求,現代及新興的電子裝置中所包含的半導體封裝在維持或減小總實體大小及/或功率消耗的同時必須能夠處理愈來愈大量的資料。
因此,包含多個半導體晶片的半導體封裝內的較高的整合度為必需的,且此半導體封裝在愈來愈有限的可用的空間量中通常包含有效配置半導體晶片的堆疊半導體結構。
本發明概念的實施例提供在封裝基底上有效配置多個半導體晶片的同時具有維持的可靠性的半導體封裝。
根據本發明概念的態樣,半導體封裝可包含:封裝基底,包含上部表面;接合襯墊,配置於封裝基底的上部表面上;下部半導體晶片,安置於封裝基底的上部表面上,其中下部半導體晶片的上部表面包含連接邊緣區域及開放邊緣區域;連接襯墊,配置於連接邊緣區域中的下部半導體晶片的上部表面上;接合線,分別連接接合襯墊及連接襯墊;壩結構,包含安置於開放邊緣區域中的虛設凸塊及在虛設凸塊中的相鄰者之間延伸的虛設線;上部半導體晶片,安置於下部半導體晶片的上部表面上;晶片間接合層,位於下部半導體晶片與上部半導體晶片之間;以及模製部分,位於封裝基底上且實質上包圍下部半導體晶片及上部半導體晶片。
根據本發明概念的另一態樣,半導體封裝可包含:封裝基底,包含具有接合襯墊的上部表面;下部半導體晶片,安置於封裝基底的上部表面上,其中下部半導體晶片的上部表面包含含有連接襯墊的連接邊緣區域及包含壩結構的開放邊緣區域;接合線,具有下部半導體晶片的上部表面上方的第一高度且連接接合襯墊及連接襯墊;上部半導體晶片,使用晶片間接合層安置於下部半導體晶片的上部表面上;以及模製部分,位於封裝基底上且實質上包圍下部半導體晶片及上部半導體晶片,其中壩結構包含安置於開放邊緣區域中的虛設凸塊及在虛設凸塊中的相鄰者之間延伸且具有下部半導體晶片的上部表面上方的第二高度的虛設線。
根據本發明概念的另一態樣,半導體封裝可包含:封裝基底,包含含有接合襯墊的上部表面;下部半導體晶片,安置於封裝基底的上部表面上,其中下部半導體晶片的上部表面包含含有連接襯墊的連接邊緣區域及包含壩結構的開放邊緣區域;間隔件晶片,安置於封裝基底的上部表面上;上部半導體晶片,安置於下部半導體晶片的上部表面及間隔件晶片的上部表面上;晶片間接合層,位於上部半導體晶片與下部半導體晶片及間隔件晶片之間;接合線,分別連接接合襯墊及連接襯墊;以及模製部分,位於封裝基底上且實質上包圍下部半導體晶片、間隔件晶片以及上部半導體晶片,其中壩結構包含至少兩個虛設凸塊及連接至少兩個虛設凸塊的至少一個虛設線。
貫穿書面描述及圖式,相同附圖標號及標記用於指示相同或類似元件、組件、方法步驟以及/或特徵。貫穿書面描述,可使用某些幾何術語來強調關於本發明概念的某些實施例的元件、組件以及/或特徵之間的相對關係。所屬領域中具有通常知識者將認識到,此類幾何術語在本質上是相對的,在描述性關係中是任意的及/或是針對所示出實施例的態樣。幾何術語可包含例如:高度/寬度;垂直/水平;頂部/底部;較高/較低;較近/較遠;較厚/較薄;接近/遠離;上方/下方;在…下方/在…上方;上部/下部;中心/側面;包圍;上覆/下伏等等。
圖(FIG.)1為根據本發明概念的實施例的半導體封裝10的橫截面側視圖,及圖2為沿線I-I'截取的半導體封裝10的平面圖。
參考圖1及圖2,半導體封裝10可包含:封裝基底100;第一(或下部)半導體晶片210,安置於封裝基底100上;間隔件晶片220S;以及第二(或上部)半導體晶片300,安置於下部半導體晶片210及間隔件晶片220S上。在本文中,圖2特定示出封裝基底100上的下部半導體晶片210及間隔件晶片220S的安置,其中上部半導體晶片300的配置僅以點線輪廓繪示。
封裝基底100可包含主體101;上部(或接合)襯墊103,位於主體101的上部表面上;以及下部襯墊105,位於主體101的下部表面上。封裝基底100亦可包含可用於不同地連接上部襯墊103及下部襯墊105的佈線圖案及連接通孔(圖1及圖2中未繪示)。(在此上下文中,術語「連接」意謂著電連接)。在一些實施例中,上部襯墊103中的至少一者及下部襯墊105中的至少一者可用作接地襯墊。
封裝基底100可不同地組態且包含以下各者中的至少一者:印刷電路板(printed circuit board;PCB)、陶瓷基底、插入件、重佈層(redistribution layer;RDL)等。在一些實施例中,封裝基底100可包含多層PCB。在一些實施例中,封裝基底100的主體101可包含諸如苯酚樹脂、環氧樹脂、聚醯亞胺、阻燃劑4(frame retardant 4;FR4)、四官能環氧基、聚苯醚、環氧基/聚苯醚、雙馬來醯亞胺三嗪(bismaleimide triazine;BT)、氰酸酯、聚醯亞胺、液晶聚合物等至少一種材料。此外,上部襯墊103、下部襯墊105、佈線圖案以及/或連接通孔中的一或多者可包含諸如銅(Cu)、鎳(Ni)、鋁(Al)、鈹銅等至少一種金屬。
一或多個外部連接端子110可分別形成於封裝基底100的下部襯墊105上。各外部連接端子110可包含例如以下各者中的至少一者:焊球、導電凸塊、導電膏、球狀柵格陣列(ball grid array;BGA)、引線柵格陣列(lead grid array;LGA)以及接腳柵格陣列(pin grid array;PGA)。
下部半導體晶片210可包含具有主動(或上部)表面及相對非主動(或下部)表面的半導體基底211。(值得注意的是,相關術語「上部」及「下部」可參考在下部半導體晶片210的製造處理期間及在封裝基底100上安裝下部半導體晶片210期間下部半導體晶片210「翻轉」之前的半導體基底211的不同表面。)(在此上下文中,術語「安裝」意謂著電連接及/或機械組裝中的至少一種)。
在一些實施例中,半導體基底211的上部表面可包含(例如,填充)各種被動元件(例如,電阻器、電容器以及/或電感器)及/或主動元件(例如,電晶體)。就此而言,半導體基底211的下部表面上的一或多個連接襯墊213可不同地連接。
在一些實施例中,在封裝基底100上安裝下部半導體晶片210可藉由使用第一黏著層217將半導體基底211的上部表面與封裝基底100的上部表面接合來實現。就此而言,下部半導體晶片210可使用一或多個接合線215不同地連接至封裝基底100。舉例而言,接合線215可用於分別使下部半導體晶片210的連接襯墊213與封裝基底100的上部襯墊103相互連接。
類似於下部半導體晶片210,上部半導體晶片300可包含含有主動表面及相對非主動表面以及連接襯墊313的半導體基底311。此外,類似於下部半導體晶片210,上部半導體晶片300可由線315不同地連接至封裝基底100。舉例而言,線315可使上部半導體晶片300的連接襯墊313與封裝基底100的上部襯墊103相互連接。
因此,上部半導體晶片300可使用晶片間接合層317接合至下部半導體晶片210的上部表面及間隔件晶片220S的上部表面。在一些實施例中,可首先將晶片間接合層317應用於上部半導體晶片300的下部表面,且接著上部半導體晶片300的下部表面可接合至下部半導體晶片210的上部表面以及間隔件晶片220S的上部表面。
在一些實施例中,晶片間接合層317可包含以下各者中的至少一者:黏著樹脂、不導電膜(non-conductive film;NCF)、直接黏著膜(direct adhesive film;DAF)以及/或膜覆線(film over wire;FOW)。此處,黏著樹脂層可包含以下各者中的至少一者:雙酚型環氧樹脂、酚醛清漆型環氧樹脂、苯酚樹脂、尿素樹脂、蜜胺樹脂、不飽和聚酯樹脂以及間甲酚樹脂。晶片間接合層317可具有相對恆定厚度,使得晶片間接合層實質上覆蓋連接連接襯墊213的接合線215的至少某一部分(例如,上部部分)。
間隔件晶片220S可安置為下部半導體晶片210的附加下部結構以進一步支撐且穩定上部半導體晶片300。此處,間隔件晶片220S可比下部半導體晶片210佔據相對更小的側面積。然而,類似於下部半導體晶片210,間隔件晶片220S可使用第二黏著層227接合至封裝基底100的上部表面。在一些實施例中,間隔件晶片220S可包含與用於製造下部半導體晶片210的半導體基底211的材料實質上類似的材料。舉例而言,間隔件晶片220S可包含矽(Si)基底。
在一些實施例中,兩個或大於兩個第一黏著層217、第二黏著層227以及晶片間接合層317可包含一或多種類似材料。
圖1及圖2的半導體封裝10可更包含實質上包圍下部半導體晶片210、間隔件晶片220S以及上部半導體晶片300的模製部分500。因此,模製部分500可保護下部半導體晶片210、間隔件晶片220S以及上部半導體晶片300免受外部的衝擊以及污染。在一些實施例中,模製部分500可藉由將適當數量的未固化樹脂注入於封裝基底100上且隨後固化樹脂而形成。舉例而言,包含將機械按壓力施加於所模製的材料的按壓步驟的轉移模製製程可用於形成模製部分500。然而,依據在處理條件中的變化(例如,在注入模製樹脂與按壓模製樹脂之間的延遲時間、在不同溫度及/或壓力下模製樹脂的黏度等),某一量的注入模製樹脂可錯誤地干擾(例如,在非所要侵入時)半導體封裝10內的其他元件、組件以及/或所述其他元件、組件之間的空間。
舉例而言,模製部分500可包含環氧基模製樹脂、聚醯亞胺基模製樹脂、環氧樹脂模製化合物(epoxy molding compound;EMC)以及/或高k環氧樹脂模製化合物。且此類不同材料可在形成模製部分500期間根據可變的處理條件作出不同反應。
圖3為圖1中所指示的區域『A1』的放大橫截面圖,圖4A為圖2中所指示的區域『A2』的放大平面圖以及圖4B為區域A2的橫截面圖。
參考圖3,在形成模製部分500的方法步驟期間,與模製部分500相關聯的未固化(注入)樹脂可在下部半導體晶片210的面向間隔件晶片220的一個側面上浪湧或膨脹(例如由箭頭『R』在圖3中所指示的方向上)以使上部半導體晶片300與下部半導體晶片210之間的晶片間接合層317的某一部分位移,且潛在地覆蓋上部半導體晶片300的下部表面的某一部分。隨著模製樹脂侵入非預期位置,有可能在模製部分500的後續處理期間可機械加壓或損壞上部半導體晶片300至實體損壞點。亦即,隨後用於形成模製部分500的施加機械壓力可損壞上部半導體晶片300的精密特徵。
參考圖2及圖4A,下部半導體晶片210的上部表面可包含配置於一或多個「連接邊緣區域」(例如,下部半導體晶片210的接近包含至少一個連接襯墊213的下部半導體晶片210的邊緣(或橫向側壁)的上部表面的區)中的連接襯墊213。因此,為了連接安置於連接邊緣區域中的一或多個連接襯墊213,接合線215可自接近連接邊緣區域的封裝基底100向上延伸。因此,上升以連接連接襯墊213的接合線215的實體存在可充當阻擋(或阻礙)與模製部分500相關聯的樹脂的流動的障礙物。
在一些對比中,不含連接襯墊213的下部半導體晶片210的上部表面的其他邊緣區域可理解為「開放邊緣區域」(或線自由區域)。不同於連接邊緣區域,開放邊緣區域(open edge regions;OPA)允許與模製部分500相關聯的樹脂易於流入內部空間中,藉此潛在地造成如上文所描述的損壞(例如開裂)。
為了防止此結果,半導體封裝10可更包含安置於下部半導體晶片210的上部表面的一或多個開放邊緣區域OPA中的壩結構250。在一些實施例中,壩結構250可包含兩個或大於兩個虛設凸塊254及至少一個虛設線255,其中虛設凸塊254可實質上沿下部半導體晶片210的外部邊緣配置於下部半導體晶片210的上部表面上,且虛設線255可在虛設凸塊254中的相鄰者之間延伸。
如圖3及圖4A中所示出,在不存在開放邊緣區域OPA內的壩結構250的情況下,在形成模製部分500期間(如由箭頭R所指示)引入的材料(例如,樹脂)可流入諸如由第二邊界BD2所指示的內部空間中。相反,開放邊緣區域OPA內的壩結構250的存在可導致樹脂流的停滯,使得僅由第一邊界BD1定界的有限內部空間(例如,在下部半導體晶片210的外部邊緣與壩結構250之間的有限內部空間)將由樹脂覆蓋。
就此而言,圖4A及圖4B的壩結構250可有效地阻擋在開放邊緣區域內的虛設凸塊254及虛設線255的安置以外的任何進一步樹脂流入(在方向R上)。
此外,就此而言,與半導體封裝10的諸如接合線215的某些主動線相比較,可將虛設線255理解為非主動線。然而,在一些實施例中,壩結構250可在沒有獨立及附加製程的要求下連同接合線215(例如,使用接合製程)而製造。因此,虛設線255及虛設凸塊254可包含與接合線215相同的材料。
舉例而言,如圖4A及圖4B中所示出,接合線215可自與連接襯墊213相關聯的各別導電凸塊214抽出。且虛設線255及虛設凸塊254可例如使用類似毛細管方法而形成,但本發明概念的實施例不限於此。此處,虛設線255及虛設凸塊254可包含例如金(Au)、銅(Cu)以及鋁(Al)中的至少一者。
如圖4B中所繪示,連接襯墊213可經由在半導體基底211的上部表面上形成的鈍化層219而選擇性地暴露。此後,導電凸塊214可形成於連接襯墊213或鈍化層219上。(在一些實施例中,連接襯墊213可為半導體基底211的佈線層的一部分,圖4B中未繪示)。因此,在一些實施例中,壩結構250可直接形成於鈍化層219上。
在一些實施例中,一或多個壩結構250可配置於與連接襯墊213的配置的圖案一致的圖案中(例如,平行於下部半導體晶片210的外部邊緣的行)。
相鄰虛設凸塊254之間的間距P(例如,在水平方向上量測的距離)可在約0.1微米至約30微米的範圍內。各虛設凸塊254的直徑D可在約0.1密耳至約20密耳的範圍內。(此處,術語「密耳」表示1/1000吋或約25.4微米)。
在一些實施例中,虛設線255的第二高度H2可與接合線215的第一高度H1實質上相同。(此處,「高度」可理解為自任意選擇的水平面的豎直方向上量測的距離)。在一些實施例中,虛設線255的第二高度H2可在接合線215的第一高度H1的約80%至120%的範圍內。舉例而言,當自下部半導體晶片210的上部表面量測時,虛設線255的第二高度H2可在約1密耳至約10密耳的範圍內。
在一些實施例中,下部半導體晶片210可為處理器晶片及/或記憶體晶片。舉例而言,下部半導體晶片210可包含以下各者中的至少一者:微處理器、圖形處理器、信號處理器、網路處理器、晶片組、音訊編解碼器、視訊編解碼器、應用程式處理器或晶片系統。替代地,下部半導體晶片210可為驅動一或多個記憶體裝置的控制晶片。
在一些實施例中,上部半導體晶片300可為揮發性記憶體晶片(例如,動態隨機存取記憶體(random access memory;RAM)(dynamic random access memory;DRAM)、靜態RAM(static random access memory;SRAM)、閘流體RAM(thyristor random access memory;TRAM)、零電容器RAM(zero capacitor random access memory;ZRAM)以及/或雙電晶體RAM(twin transistor random access memory;TTRAM))及/或非揮發性記憶體晶片(例如,快閃記憶體、磁性RAM(magnetic random access memory;MRAM)、自旋轉移力矩MRAM(spin-transfer torque magnetic random access memory;STT-MRAM)、鐵電RAM(ferroelectric random access memory;FRAM)、相位變化RAM(phase change random access memory;PRAM)、電阻RAM(resistive random access memory;RRAM)、奈米管RRAM、聚合物RAM、奈米浮置閘極記憶體、全息記憶體、分子電子學記憶體以及/或絕緣體電阻變化記憶體)。
如上文所提及,上部半導體晶片300可由晶片間接合層317接合至下部半導體晶片210及間隔件晶片220S的上部表面,且上部半導體晶片300可經安置以覆蓋下部半導體晶片210及間隔件晶片220S的上部表面的至少各別部分,但本發明概念的範疇不限於此。替代地,不由上部半導體晶片300覆蓋的一或多個附加半導體晶片可安置於封裝基底100上。
此外,如上文所提及,壩結構250的安置可有效地防止與模製部分500相關聯的材料(例如,樹脂)的流入深入地侵入下部半導體晶片210的邊緣區域之中的開放邊緣區域中。如下文將進一步強調,壩結構250可使用各種材料及結構不同地組態。
圖5為可包含於本發明概念的實施例中的下部半導體晶片200的平面圖,圖6A為圖5中所指示的區域『B1』的橫截面圖,以及圖6B為圖5中所指示的區域『B2』的橫截面圖。
下部半導體晶片200可包含與主動區域實質上重疊的居中安置的裝置區域200D以及用於電連接主動區域中的各種元件及/或組件的佈線層。下部半導體晶片200亦可包含實質上包圍裝置區域200D的周邊區域200E。連接襯墊213可配置於下部半導體晶片200的上部表面的一或多個連接邊緣區域中。亦即,連接襯墊213可沿裝置區域200D的接近周邊區域200E的一或多個外部邊緣不同地配置。
就此而言,可自沿裝置區域200D的一或多個側面或拐角限定的某些開放邊緣區域實質上忽略連接襯墊213。舉例而言,圖5的拐角區域B1為第一開放邊緣區域(OPA1),且側面區域B2為第二開放邊緣區域(OPA2),其中第一壩結構250'可形成於第一開放邊緣區域OPA1中,且第二壩結構250"可形成於第二開放區域OPA2中。就此而言,第一壩結構250'及第二壩結構250"可具有極為不同的結構。
參考圖6A,第一壩結構250'可包含第一虛設凸塊254'的配置,所述第一虛設凸塊254'包含沿下部半導體晶片200的一個側面在第一水平方向上延伸的第一部分及沿下部半導體晶片200的另一側面在與第一水平方向相交的第二水平方向上延伸的第二部分。此外,第一壩結構250'包含在第一虛設凸塊254'中的相鄰者之間分別延伸的第一虛設線255'。
參考圖6B,第二壩結構250"可包含沿下部半導體晶片200的一個側面的一部分配置的第二虛設凸塊254"的線性配置。此處,然而,第二虛設凸塊254"中的各者可包含自上部表面豎直地延伸的突起。如此組態,虛設線不需要包含於第二壩結構250"中,但可阻擋或充分阻礙與模製部分相關聯的樹脂流入第二開口區OPA2中。
圖7為示出可包含於本發明概念的實施例的下部半導體晶片200A中的壩結構250A的平面圖。
迄今為止,為了基本描述的清楚起見,已假設各種壩結構僅包含組成元件(例如,凸塊及線)的一或多個線性(例如,直線)配置。然而,不需要總是如此,且本發明概念的其他實施例可包含相對更複雜的組成元件配置。
參考圖7,除其中另外的描述之外,下部半導體晶片200A假設與圖5的下部半導體晶片200A實質上類似。就此而言,下部半導體晶片200A可包含壩結構250A,所述壩結構250A包含以Z字形圖案配置的第一虛設凸塊254a及第二虛設凸塊254b,且由虛設線255以Z字形圖案連接。舉例而言,第一虛設凸塊254a可配置於沿裝置區域200D的外部邊緣延伸的第一行中,且第二虛設凸塊254b可配置於在周邊區域200E中與第一虛設凸塊254a的配置平行的方向上延伸的第二行中。
亦即,第一虛設凸塊254a及第二虛設凸塊254b可相對於開放邊緣區域在阻擋或阻礙與模製部分相關聯的樹脂的可能侵入的方向上替代地安置於兩行中。如圖7中所示出,一或多個虛設線255可在第一虛設凸塊254a及第二虛設凸塊254b之中以Z字形圖案來回延伸以形成壩結構250A。
圖8A為示出可包含於根據本發明概念的實施例的下部半導體晶片200B中的另一壩結構250B的平面圖,及圖8B為下部半導體晶片200B的橫截面圖。
此處,類似於圖7的壩結構250A,壩結構250B可包含配置於沿裝置區域200D的邊緣的第一行中的第一虛設凸塊254a及沿周邊區域200E的邊緣配置於與第一行平行的第二行中的第二虛設凸塊254b。
然而,在圖8A及圖8B所示出的實施例中,第一虛設凸塊254a中的各者可分別安置於虛設襯墊253的配置中的一者上。就此而言,虛設襯墊253可在製造下部半導體晶片200B期間連同連接襯墊213(例如,使用相同半導體製造製程)而形成。此處,然而,虛設襯墊253不需要連接至主動區域、佈線層或接合線。相反,虛設襯墊253可經設置以改良第一虛設凸塊254a的接合強度。因此,與直接接合至鈍化層219相比較,第一虛設凸塊254a可更牢固地接合。如圖8A及圖8B中所繪示,第一虛設凸塊254a可與虛設線連接,但第二虛設凸塊254b可不由虛設線255連接。在一些實施例中,因此,配置於平行行中的第一虛設凸塊254a及第二虛設凸塊254b可仍然具有不同的各別形狀。
圖9A及圖9B為示出可併入於根據本發明概念的實施例的下部半導體晶片200C及下部半導體晶片200C'中的各種壩結構的各別平面圖。
參考圖9A,下部半導體晶片200C可包含雙行壩結構。此處,雙行壩結構可包含:第一壩結構250a,包含配置於裝置區域200D內的第一行中的第一虛設凸塊254a及連接第一虛設凸塊254a中的相鄰者的第一虛設線255a;及第二壩結構250b,包含配置於平行於周邊區域200E內的第一行的第二行中的第二虛設凸塊254b及連接第二虛設凸塊254b中的相鄰者的第二虛設線255b。
參考圖9B,下部半導體晶片200C'可包含單行壩結構。此處,單行壩結構可包含僅配置於周邊區域200E中的行中的第二虛設凸塊254b及連接第二虛設凸塊254b中的相鄰者的第二虛設線255b。
與本發明概念的實施例一致的各種壩結構可有利地應用於各種半導體封裝。就此而言,現將關於圖10、圖11、圖12、圖13、圖14、圖15、圖16以及圖17描述一些示例性半導體封裝。
圖10為根據本發明概念的實施例的半導體封裝10A的橫截面側視圖,及圖11為沿線IV-IV'截取的半導體封裝10A的平面圖。
參考圖10及圖11,半導體封裝10A可包含:封裝基底100;下部半導體晶片210,安置於封裝基底100上;以及上部半導體晶片300,安置於下部半導體晶片210上。此處,儘管下部半導體晶片210繪示為具有比上部半導體晶片300的側面積小的側面積,但本發明概念的實施例不限於此,且在其他實施例中,上部半導體晶片300的側面積可大於下部半導體晶片210的側面積。
如圖11中所繪示,半導體封裝10A可更包含安置於下部半導體晶片210的上部表面的開放邊緣區域OPA中的單行壩結構250。亦即,壩結構250可包含配置於沿下部半導體晶片210的上部表面的一個側面的外部邊緣的行中的虛設凸塊254及連接虛設凸塊254中的相鄰者的虛設線255。在一些實施例中,虛設線255及/或虛設凸塊254可包含用於形成接合線215的相同材料(例如金(Au)、銅(Cu)以及鋁(Al))。
圖12為根據本發明概念的實施例的半導體封裝10B的橫截面側視圖,及圖13為沿線V-V'截取的半導體封裝10B的平面圖。
參考圖12及圖13,除包含形成晶片堆疊結構400的堆疊的多個半導體晶片411之外,半導體封裝10B可與先前所描述實施例實質上類似。
因此,半導體封裝10B可包含封裝基底100及安置於封裝基底100上的晶片堆疊結構400。在晶片堆疊結構400內,兩個或大於兩個半導體晶片411可以逐步方式豎直堆疊。在一些實施例中,半導體晶片411中的各者可為記憶體晶片(例如,NAND快閃記憶體晶片及/或DRAM晶片)。晶片間黏著層417可不同地插入於形成晶片堆疊結構411的半導體晶片中的相鄰者之間。此處,晶片間黏著層417可與不導電黏著層317相同或與不導電黏著層317(例如,直接黏著膜(DAF)、膜覆線(FOW)等)實質上類似。形成晶片堆疊結構411的半導體晶片中的各者可包含安置於其上部表面上的連接襯墊413,使得相鄰半導體晶片可堆疊於暴露的連接襯墊413上。在一些實施例中,如圖13中所示出,晶片堆疊結構400可更包含安置於連接襯墊413上的導電凸塊414。相鄰半導體晶片411與上部襯墊103之間的連接襯墊413可由接合線415連接。亦即,與前述描述一致,接合線415可用於將晶片堆疊結構411中的半導體晶片中的更向上安置的一者上的連接襯墊413連接至形成晶片結構411的半導體晶片之中的最低半導體晶片及/或封裝基底100的上部襯墊103上的連接襯墊413。
如圖13中所繪示,半導體封裝10B亦可包含安置於形成具有開放邊緣區域OPA(例如,不含連接襯墊413的區)的晶片堆疊結構411的半導體晶片之中的半導體晶片的上部表面上的至少一個雙行壩結構250。
如同前述實施例,圖12及圖13的壩結構250可配置於有效地阻礙或阻擋與模製部分500相關聯的樹脂的流入的方向上,以便保護形成晶片堆疊結構411的半導體晶片中的相鄰者之間的空間。此外,虛設線255及/或虛設凸塊254可包含用於形成接合線415的相同材料。
圖14為根據本發明概念的實施例的半導體封裝10C的橫截面圖,及圖15為沿線VI-VI'截取的半導體封裝10C的平面圖。
此處,半導體封裝10C可包含:封裝基底100;第一下部半導體晶片210及第二下部半導體晶片220,安置於封裝基底100上;以及上部半導體晶片300,安置於第一下部半導體晶片210及第二下部半導體晶片220的上部表面上。
類似於第一下部半導體晶片210,第二下部半導體晶片220可包含具有主動表面及相對非主動表面的半導體基底221及連接襯墊223。第二下部半導體晶片220可使用黏著層227接合至封裝基底100的上部表面。
第一下部半導體晶片210及第二下部半導體晶片220的連接襯墊213及連接襯墊223可由接合線215及接合線225分別連接至封裝基底100的上部襯墊103。值得注意的是,第一下部半導體晶片210及第二下部半導體晶片220可充當穩定支撐上部半導體晶片300的下部結構。晶片間接合層317可安置於上部半導體晶片300的下部表面上,且上部半導體晶片300可使用晶片間接合層317接合至第一下部半導體晶片210及第二下部半導體晶片220的上部表面。
如圖15中所繪示,第一下部半導體晶片210及第二下部半導體晶片220中的各者可包含一或多個開放邊緣區域(例如,第一開放邊緣區域OPA1及第二開放邊緣區域OPA2)。第一開放區域OPA1可為在第二下部半導體晶片220的鄰近側面之間延伸的拐角開放邊緣區域,而第二開放區域OPA2可為沿第一下部半導體晶片210的單個側面部分地延伸的線性開放邊緣區域。
因此,單行拐角壩結構250_1(類似於圖5的壩結構250')可設置於第一開放邊緣區域OPA1中,且單行壩結構250_2(類似於圖5的壩結構250")可設置於第二開放區域中。然而,所屬領域具有通常知識者應瞭解第一壩結構250_1及第二壩結構中的一者或兩者可替代地以Z字形圖案、雙行圖案等組態。
圖16為根據本發明概念的實施例的半導體封裝10D的橫截面圖,及圖17為沿線VII-VII'截取的半導體封裝10D的平面圖。
參考圖16及圖17,半導體封裝10D可包含安置於間隔件晶片230S及第二下部半導體晶片220A的堆疊組合的上部表面以及第一下部半導體晶片210的上部表面上的上部晶片堆疊結構400。此處,第二下部半導體晶片220A可使用焊料球227及底填充材料207而非(或除)接合線連接至封裝基底100。
因此,半導體封裝10D可包含:封裝基底100;第一下部半導體晶片210及第二下部半導體晶片220A,安置於封裝基底100上;間隔件晶片230S;安置於第二下部半導體晶片220A的上部表面上;以及上部半導體晶片400,安置於第一下部半導體晶片210及間隔件晶片230S的上部表面上。
值得注意的是,鑒於針對第一下部半導體晶片210及第二下部半導體晶片220A的不同安裝高度可相對較大,可藉由使用安置於第二下部半導體晶片220A的上部表面上的間隔件晶片230S來減少此差異。就此而言,間隔件晶片230S可使用黏著層237安置於第二下部半導體晶片220A的主動表面上。使用此方法,第二下部半導體晶片220A及間隔件晶片230S的堆疊組合的高度可與第一下部半導體晶片210的高度實質上類似。
上部半導體晶片400可由晶片間接合層317接合至第一下部半導體晶片210的主動表面及間隔件晶片230S的上部表面。上部半導體晶片400可經安置以覆蓋第一下部半導體晶片210的主動表面及間隔件晶片230S的上部表面。
上部半導體晶片400可為類似於先前關於圖12所描述的晶片堆疊結構。
如圖17中所繪示,半導體封裝10D可更包含安置於第一下部半導體晶片210的上部表面的開放邊緣區域OPA中的壩結構250。壩結構250可為如上文所描述的單行壩結構。
自前述內容,所屬領域中具通常知識者可易於瞭解在半導體封裝內的半導體晶片的開放邊緣區域(例如,接合線自由區)中提供一或多個壩結構可極大地減小或消除與與模製部分相關聯的非所要材料的流入相關聯的缺陷的風險。此壩結構可在大小、幾何以及組態中發生變化,但可通常自開放邊緣區域內(或接近開放邊緣區域)的虛設凸塊的一或多個配置組態,其中在一些實施例中,虛設凸塊可由虛設線連接。因此,可顯著地改良半導體封裝的總可靠性。
雖然上文已示出且描述實例實施例,但對於所屬領域中具通常知識者將顯而易見的是可在不脫離如所附申請專利範圍所限定的本發明概念的範疇的情況下作出許多修改及改變。
10、10A、10B、10C、10D:半導體封裝
100:封裝基底
101:主體
103:上部襯墊、接合襯墊
105:下部襯墊
110:外部連接端子
200、200A、200B、200C、200C':下部半導體晶片
200D:裝置區域
200E:周邊區域
207:底填充材料
210:下部半導體晶片
211、221、311:半導體基底
213、223、313、413:連接襯墊
214、414:導電凸塊
215:接合線
217:第一黏著層
219:鈍化層
220、220A:第二下部半導體晶片
220S、230S:間隔件晶片
225:接合線
227:焊料球、黏著層
237:黏著層
250、250A、250B:壩結構
250':第一壩結構
250":第二壩結構
250a:第一壩結構
250b:第二壩結構
250_1:單行拐角壩結構
250_2:單行壩結構
253:虛設襯墊
254:虛設凸塊
254'、254a:第一虛設凸塊
254"、254b:第二虛設凸塊
255:虛設線
255':第一虛設線
255a:第一虛設線
255b:第二虛設線
300:上部半導體晶片
315、415:線
317:晶片間接合層
400:晶片堆疊結構
411:半導體晶片
417:晶片間黏著層
500:模製部分
A1、A2、B1、B2:區域
BD1:第一邊界
BD2:第二邊界
D:直徑
H1:第一高度
H2:第二高度
OPA:開放邊緣區域
OPA1:第一開放區域
OPA2:第二開放區域
P:間距
R:方向
I-I'、II-II'、III-III'、IV-IV'、V-V'、VI-VI'、VII-VII':線
在考慮以下詳細描述以及隨附圖式後,可更清楚地理解本發明概念的製造及使用,在隨附圖式中:
圖1為根據本發明概念的實施例的半導體封裝的橫截面圖,圖2為沿線I-I'截取的圖1的半導體封裝的平面(或俯視)圖,圖3為圖1中所指示的區域『A1』的放大橫截面圖,圖4A為圖2中所指示的區域『A2』的放大平面圖,以及圖4B為沿圖4A的線II-II'截取的區域A2的橫截面圖。
圖5為可包含於本發明概念的各種實施例中的下部半導體晶片的平面圖。
圖6A為圖5中所指示的區域『B1』的放大橫截面圖,及圖6B為圖5中所指示的區域『B2』的放大橫截面圖。
圖7為示出可包含於本發明概念的各種實施例的下部半導體晶片中的壩結構的平面圖。
圖8A為示出可包含於本發明概念的各種實施例的下部半導體晶片中的壩結構的平面圖,及圖8B為沿線III-III'截取的圖8A的下部半導體晶片的橫截面圖。
圖9A及圖9B為示出可包含於本發明概念的各種實施例的下部半導體晶片中的各種壩結構的各別平面圖。
圖10為根據本發明概念的實施例的半導體封裝的橫截面圖,及圖11為沿線IV-IV'截取的圖10的半導體封裝的平面圖。
圖12為根據本發明概念的實施例的半導體封裝的橫截面圖,及圖13為沿線V-V'截取的圖12的半導體封裝的平面圖。
圖14為根據本發明概念的實施例的半導體封裝的橫截面圖,及圖15為沿線VI-VI'截取的圖14的半導體封裝的平面圖。
圖16為根據本發明概念的實施例的半導體封裝的橫截面圖,及圖17為沿線VII-VII'截取的圖16的半導體封裝的平面圖。
10:半導體封裝
100:封裝基底
103:上部襯墊、接合襯墊
210:第一下部半導體晶片
215:接合線
220S:間隔件晶片
300:上部半導體晶片
A2:區域
OPA:開放邊緣區域
I-I':線
Claims (20)
- 一種半導體封裝,包括: 封裝基底,包含上部表面; 接合襯墊,配置於所述封裝基底的所述上部表面上; 下部半導體晶片,安置於所述封裝基底的所述上部表面上,其中所述下部半導體晶片的上部表面包含連接邊緣區域及開放邊緣區域; 連接襯墊,配置於所述連接邊緣區域中的所述下部半導體晶片的所述上部表面上; 接合線,分別連接所述接合襯墊及所述連接襯墊; 壩結構,包含安置於所述開放邊緣區域中的虛設凸塊及在所述虛設凸塊中的相鄰者之間延伸的虛設線; 上部半導體晶片,安置於所述下部半導體晶片的所述上部表面上; 晶片間接合層,位於所述下部半導體晶片與所述上部半導體晶片之間;以及 模製部分,位於所述封裝基底上且實質上包圍所述下部半導體晶片及所述上部半導體晶片。
- 如請求項1所述的半導體封裝,其中所述虛設凸塊沿所述下部半導體晶片的所述上部表面的邊緣配置於所述開放邊緣區域中。
- 如請求項1所述的半導體封裝,其中所述壩結構包含與所述接合線相同的材料。
- 如請求項1所述的半導體封裝,其中所述虛設凸塊配置於至少一個行中。
- 如請求項4所述的半導體封裝,其中所述虛設凸塊配置於兩個平行行中,且所述壩結構更包含以Z字形圖案在虛設凸塊之間交替地延伸的虛設線。
- 如請求項4所述的半導體封裝,其中配置於所述開放邊緣區域中的所述虛設凸塊與配置於所述連接邊緣區域中的所述連接襯墊對準。
- 如請求項1所述的半導體封裝,其中所述虛設凸塊以0.1微米至30微米的範圍內的間距分離。
- 如請求項1所述的半導體封裝,其中所述虛設凸塊中的各者具有0.1密耳至20密耳的範圍內的直徑。
- 一種半導體封裝,包括: 封裝基底,包含具有接合襯墊的上部表面; 第一下部半導體晶片,安置於所述封裝基底的所述上部表面上,其中所述第一下部半導體晶片的上部表面包含含有連接襯墊的連接邊緣區域及包含壩結構的開放邊緣區域; 接合線,具有所述第一下部半導體晶片的所述上部表面上方的第一高度且連接所述接合襯墊及所述連接襯墊; 上部半導體晶片,使用晶片間接合層安置於所述第一下部半導體晶片的所述上部表面上;以及 模製部分,位於所述封裝基底上且實質上包圍所述第一下部半導體晶片及所述上部半導體晶片, 其中所述壩結構包含安置於所述開放邊緣區域中的虛設凸塊,及在所述虛設凸塊中的相鄰者之間延伸且具有所述第一下部半導體晶片的所述上部表面上方的第二高度的虛設線。
- 如請求項9所述的半導體封裝,更包括安置於所述封裝基底的所述上部表面上的第二下部半導體晶片、在所述上部半導體晶片與所述第二下部半導體晶片之間延伸的所述晶片間接合層, 其中所述開放邊緣區域沿所述第一下部半導體晶片的所述上部表面的鄰近於所述第二下部半導體晶片的邊緣安置。
- 如請求項9所述的半導體封裝,其中所述虛設線的所述第二高度為所述接合線的所述第一高度的80%至120%。
- 如請求項9所述的半導體封裝,其中所述第二高度在所述第一下部半導體晶片的所述上部表面上方1密耳至10密耳的範圍內。
- 如請求項9所述的半導體封裝,其中所述第一下部半導體晶片的所述上部表面包含由周邊區域包圍的裝置區域; 所述虛設凸塊之中的第一虛設凸塊配置於安置於所述裝置區域中的第一行中;且 所述虛設凸塊之中的第二虛設凸塊配置於平行於所述第一行且安置於所述周邊區域中的第二行中。
- 如請求項13所述的半導體封裝,其中所述虛設線之中的第一虛設線在所述第一虛設凸塊中的各別者之間延伸。
- 如請求項14所述的半導體封裝,其中所述虛設線之中的第二虛設線在所述第二虛設凸塊中的各別者之間延伸。
- 如請求項9所述的半導體封裝,其中所述第一下部半導體晶片包含半導體基底,所述半導體基底包含主動區域及電連接至所述主動區域的佈線層;以及 所述第一下部半導體晶片的所述上部表面包含與所述主動區域及所述佈線層重疊的裝置區域及包圍所述裝置區域的周邊區域。
- 如請求項16所述的半導體封裝,其中所述開放邊緣區域整體安置於所述裝置區域中。
- 如請求項16所述的半導體封裝,其中所述開放邊緣區域至少部分地安置於所述周邊區域中。
- 一種半導體封裝,包括: 封裝基底,包含含有接合襯墊的上部表面; 下部半導體晶片,安置於所述封裝基底的所述上部表面上,其中所述下部半導體晶片的上部表面包含含有連接襯墊的連接邊緣區域及包含壩結構的開放邊緣區域; 間隔件晶片,安置於所述封裝基底的所述上部表面上; 上部半導體晶片,安置於所述下部半導體晶片的所述上部表面及所述間隔件晶片的所述上部表面上; 晶片間接合層,位於所述上部半導體晶片與所述下部半導體晶片及所述間隔件晶片之間; 接合線,分別連接所述接合襯墊及所述連接襯墊;以及 模製部分,位於所述封裝基底上且實質上包圍所述下部半導體晶片、所述間隔件晶片以及所述上部半導體晶片, 其中所述壩結構包含至少兩個虛設凸塊及連接所述至少兩個虛設凸塊中的至少一個虛設線。
- 如請求項19所述的半導體封裝,其中所述上部半導體晶片為包含多個半導體晶片的晶片堆疊結構。
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KR100265461B1 (ko) | 1997-11-21 | 2000-09-15 | 윤종용 | 더미본딩와이어를포함하는반도체집적회로소자 |
TWI267972B (en) | 2005-02-05 | 2006-12-01 | Himax Tech Ltd | Substrate with slot |
KR20120035297A (ko) | 2010-10-05 | 2012-04-16 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
JP2014049733A (ja) | 2012-09-04 | 2014-03-17 | Fujitsu Semiconductor Ltd | 半導体装置及び半導体装置の製造方法 |
US20170238416A1 (en) | 2016-02-17 | 2017-08-17 | Multek Technologies Limited | Dummy core restrict resin process and structure |
JP6783648B2 (ja) | 2016-12-26 | 2020-11-11 | 新光電気工業株式会社 | 配線基板、半導体装置 |
CN108695284A (zh) * | 2017-04-07 | 2018-10-23 | 晟碟信息科技(上海)有限公司 | 包括纵向集成半导体封装体组的半导体设备 |
-
2021
- 2021-07-22 KR KR1020210096420A patent/KR20230016089A/ko unknown
-
2022
- 2022-02-25 US US17/680,877 patent/US11961824B2/en active Active
- 2022-06-20 CN CN202210699359.7A patent/CN115700920A/zh active Pending
- 2022-06-30 TW TW111124510A patent/TW202306079A/zh unknown
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Publication number | Publication date |
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US11961824B2 (en) | 2024-04-16 |
US20230028943A1 (en) | 2023-01-26 |
CN115700920A (zh) | 2023-02-07 |
KR20230016089A (ko) | 2023-02-01 |
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