JP6783648B2 - 配線基板、半導体装置 - Google Patents
配線基板、半導体装置 Download PDFInfo
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- JP6783648B2 JP6783648B2 JP2016251599A JP2016251599A JP6783648B2 JP 6783648 B2 JP6783648 B2 JP 6783648B2 JP 2016251599 A JP2016251599 A JP 2016251599A JP 2016251599 A JP2016251599 A JP 2016251599A JP 6783648 B2 JP6783648 B2 JP 6783648B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
図1は、第1の実施の形態に係る半導体装置を例示する図であり、図1(a)は平面図、図1(b)は図1(a)のA−A線に沿う部分拡大断面図である。但し、図1(a)は主としてパッドの配置を示しており、図1(b)に示す構成要素の一部は図示が省略されている。
第1の実施の形態の変形例では、ダミーパッドの配置のバリエーションを示す。なお、第1の実施の形態の変形例において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
第2の実施の形態では、ダミーパッド18の配置が第1の実施の形態とは異なる形態を示す。なお、第2の実施の形態において、既に説明した実施の形態と同一構成部についての説明は省略する場合がある。
10 配線基板
11 配線層
12 絶縁層
12a 絶縁層12の上面
12x ビアホール
13 パッド
13v ビア配線
14 ニッケルめっき層
15 金属層
18 ダミーパッド
21、22、23 半導体チップ
30 電極
40 バンプ
50 アンダーフィル樹脂
Claims (9)
- 絶縁層の上面において、半導体チップ接続用の外部接続端子として使用される複数のパッドが配置されたパッド配置領域が画定され、
前記パッド配置領域は、複数の前記パッドが所定密度で配置された第1領域と、複数の前記パッドが前記第1領域の所定密度よりも低密度で配置された第2領域と、を含み、
前記第2領域のみ、外部接続端子として使用されないダミーパッドが少なくとも1つ配置され、
前記ダミーパッドは、少なくとも前記第2領域の最外周に位置する前記パッドの外側、かつ前記半導体チップの外形よりも外側に位置し、
前記パッド及び前記ダミーパッドの表面には、めっき層が形成され、前記めっき層はニッケルを含む配線基板。 - 前記第2領域の最外周に位置するパッドと前記ダミーパッドとが千鳥状に配置されている請求項1に記載の配線基板。
- 前記第2領域の最外周に位置するパッドと前記ダミーパッドとの距離が、前記第2領域内で隣接する前記パッド同士の距離よりも短い請求項1又は2に記載の配線基板。
- 前記ダミーパッドのピッチが、前記第2領域内で隣接する前記パッドのピッチよりも狭い請求項1乃至3の何れか一項に記載の配線基板。
- 少なくとも前記第2領域の最外周に位置するパッドの間、及び第2領域の最外周よりも内側に位置するパッドの間にも前記ダミーパッドを配置した請求項1乃至4の何れか一項に記載の配線基板。
- 前記ダミーパッドは、前記第2領域の最外周に位置するパッドに沿った細長状のパターンに形成されている請求項1に記載の配線基板。
- 前記第2領域の最外周に位置するパッドの外側に、複数列のダミーパッドが配置されている請求項1乃至5の何れか一項に記載の配線基板。
- 前記第2領域内で隣接する前記パッドのピッチは、前記第1領域内で隣接する前記パッドのピッチよりも広い請求項1乃至7の何れか一項に記載の配線基板。
- 請求項1乃至8の何れか一項に記載の配線基板と、
前記配線基板の複数の前記パッドに接続された半導体チップと、
前記配線基板と前記半導体チップとの間に充填された樹脂と、を有し、
前記樹脂は、前記ダミーパッドを被覆している半導体装置。
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US12027493B2 (en) * | 2019-11-04 | 2024-07-02 | Xilinx, Inc. | Fanout integration for stacked silicon package assembly |
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