TW202230666A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202230666A
TW202230666A TW110135251A TW110135251A TW202230666A TW 202230666 A TW202230666 A TW 202230666A TW 110135251 A TW110135251 A TW 110135251A TW 110135251 A TW110135251 A TW 110135251A TW 202230666 A TW202230666 A TW 202230666A
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Taiwan
Prior art keywords
support substrate
semiconductor package
redistribution
disposed
capacitor
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Application number
TW110135251A
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English (en)
Inventor
姜明杉
高永燦
金廷錫
文炅墩
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南韓商三星電子股份有限公司
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Application filed by 南韓商三星電子股份有限公司 filed Critical 南韓商三星電子股份有限公司
Publication of TW202230666A publication Critical patent/TW202230666A/zh

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Abstract

一種半導體封裝包括其中設置有連接配線的支撐基板。至少一個電容器設置於支撐基板上。電容器具有自支撐基板的上表面暴露出的第一電極及第二電極。重佈線配線層覆蓋支撐基板的上表面。重佈線配線層具有分別電性連接至連接配線以及第一電極及第二電極的重佈線配線。半導體晶片設置於重佈線配線層上。半導體晶片具有電性連接至重佈線配線的晶片接墊以及設置於支撐基板的下表面上且電性連接至連接配線的外連接件。

Description

半導體封裝以及半導體封裝之製造方法
[優先權聲明]
本申請案基於35 U.S.C. § 119主張於2020年12月18日在韓國智慧財產局（Korean Intellectual Property Office，KIPO）中提出申請的韓國專利申請案第10-2020-0178164號的優先權，所述韓國專利申請案的內容全文併入本案供參考。
本揭露是有關於半導體，且更具體地，是有關於一種半導體封裝以及一種製造所述半導體封裝的方法。
在扇出封裝中作為應用處理器的解耦電容器安裝的電容器可以著落側電容器（Land-Side Capacitor，LSC）的形式製造。由於LSC型電容器設置於上面設置有焊料球的外表面上，因此電容器可能需要相對薄。因此，在電容器的表面安裝期間可能會出現裂紋（crack）。另外，此種電容器的電容可能受到限制。
一種半導體封裝包括其中設置有連接配線的支撐基板以及設置於支撐基板上的至少一個電容器。電容器包括自支撐基板的上表面暴露出的第一電極及第二電極。重佈線配線層覆蓋支撐基板的上表面。重佈線配線層具有分別電性連接至連接配線以及第一電極及第二電極的重佈線配線。半導體晶片設置於重佈線配線層上。半導體晶片具有電性連接至重佈線配線的晶片接墊以及設置於支撐基板的下表面上且電性連接至連接配線的外連接件。
一種半導體封裝包括支撐基板，所述支撐基板具有穿透過所述支撐基板的空腔。至少一個電容器設置於支撐基板的空腔中。電容器具有自支撐基板的上表面暴露出的第一電極及第二電極。密封層填充空腔且覆蓋支撐基板的下表面。重佈線配線層覆蓋支撐基板的上表面。重佈線配線層具有分別電性連接至支撐基板的連接配線以及第一電極及第二電極的重佈線配線。半導體晶片設置於重佈線配線層上。半導體晶片具有分別電性連接至重佈線配線的晶片接墊以及設置於密封層的下表面上且分別電性連接至連接配線的外連接件。
一種半導體封裝包括混合堆疊基板，所述混合堆疊基板包括具有連接配線的支撐基板以及穿透過支撐基板的空腔。至少一個電容器設置於支撐基板的空腔中。所述至少一個電容器包括自支撐基板的上表面暴露出的第一電極及第二電極。重佈線配線層覆蓋支撐基板的上表面，且具有分別電性連接至連接配線以及第一電極及第二電極的重佈線配線。半導體晶片設置於混合堆疊基板上。半導體晶片包括電性連接至重佈線配線的晶片接墊。位於混合堆疊基板的下表面上的外連接件電性連接至連接配線。
一種半導體封裝包括封裝基板。混合堆疊基板藉由連接件安裝於封裝基板上。半導體晶片安裝於混合堆疊基板上。混合堆疊基板包括支撐基板，所述支撐基板具有分別電性連接至連接件的連接配線。至少一個被動元件設置於支撐基板中。電容器的表面自支撐基板的上表面暴露出。重佈線配線層覆蓋支撐基板的上表面，且具有分別電性連接至連接配線及被動元件的重佈線配線。
一種半導體封裝可包括混合堆疊基板，所述混合堆疊基板具有其中嵌置有至少一個電容器的支撐基板以及堆疊於支撐基板上且具有重佈線配線的重佈線配線層，所述重佈線配線分別電性連接至電容器的第一電極及第二電極以及支撐基板的連接配線。至少一個半導體晶片安裝於混合堆疊基板上。外連接件設置於混合堆疊基板的下表面上。
在下文中，將參照附圖詳細闡釋本揭露的示例性實施例。
圖1是示出根據本揭露示例性實施例的半導體封裝的剖視圖。圖2是示出圖1中的部分「A」的放大剖視圖。
參照圖1及圖2，半導體封裝10可包括混合堆疊基板100、安裝於混合堆疊基板100上的至少一個半導體晶片300以及設置於混合堆疊基板100的外表面上的外連接件500。半導體封裝10可更包括設置於混合堆疊基板100上且覆蓋半導體晶片300的模製件400。混合堆疊基板100可包括作為核心基板的支撐基板110及堆疊於支撐基板110上的重佈線配線層140。
在本揭露的示例性實施例中，半導體封裝10可包括作為支撐半導體晶片300的基礎基板提供的混合堆疊基板100。混合堆疊基板100可包括連接配線120及重佈線配線，連接配線120設置於其中半導體晶片300用作與半導體晶片300的電性連接路徑的區域之外的扇出區上。因此，半導體封裝10可被設置成扇出封裝（fan-out package）。半導體封裝10可被設置成上面堆疊有第二封裝的單位封裝（unit package）。
此外，半導體封裝10可被設置成系統級封裝（System-In-Package，SIP）。舉例而言，半導體晶片可包括包含邏輯電路的邏輯晶片及/或記憶體晶片。邏輯晶片可為控制記憶體晶片的控制器。記憶體晶片可包括例如動態隨機存取記憶體（dynamic random access memory，DRAM）、靜態隨機存取記憶體（static random access memory，SRAM）、快閃、相變隨機存取記憶體（phase-change random access memory，PRAM）、電阻式隨機存取記憶體（resistive random access memory，ReRAM）、鐵電隨機存取記憶體（ferroelectric random access memory，FeRAM）、磁性隨機存取記憶體（magnetic random access memory，MRAM）或類似物等各種記憶體電路。
在本揭露的示例性實施例中，混合堆疊基板100可包括上面設置有例如電容器200等被動元件的支撐基板110。重佈線配線層140可堆疊於支撐基板110上。
舉例而言，支撐基板110可具有彼此相對的第一表面（上表面）112與第二表面（下表面）114。支撐基板110可在其中間區中具有空腔116。空腔116可自支撐基板110的第一表面112延伸至第二表面114。
支撐基板110可為藉由嵌置跡線基板（embedded trace substrate，ETS）方法形成的無核心基板。在此種情形中，支撐基板110可包括多個絕緣層及位於所述絕緣層中的電路層。作為另一選擇，支撐基板可為核心多層式基板（core multilayered substrate）。在此種情形中，核心多層式基板可包括核心層以及堆疊於核心層的上表面與下表面二者上的電路層。
如圖1中所示，支撐基板110可包括多個堆疊的絕緣層120a及120b以及在所述絕緣層中作為電性導體提供的連接配線122。多個連接配線122可自支撐基板110的第一表面112至第二表面114穿透過支撐基板110，以用作電性連接路徑。
舉例而言，支撐基板110可包括第一絕緣層120a及堆疊於第一絕緣層120a上的第二絕緣層120b。連接配線122可包括第一金屬配線122a、第一接觸件122b、第二金屬配線122c、第二接觸件122d及第三金屬配線122e。第一金屬配線122a可設置於支撐基板110的第一表面112上（例如，設置於第一絕緣層120a的下表面中），且第一金屬配線122a的至少一部分可自第一表面112暴露出。第三金屬配線122e可設置於支撐基板110的第二表面114上（例如，設置於第二絕緣層120b的上表面中），且第三金屬配線122e的至少一部分可自第二表面114暴露出。如本文中所使用的片語「A自B暴露出」可意指B不完全覆蓋A，A的各個部分藉由B內的一或多個開口暴露至一或多個其他層。可理解，核心基板100的絕緣層及核心連接配線的數目及佈置可能不限於此。
在本揭露的示例性實施例中，電容器200可設置於支撐基板110的空腔116內。電容器200的側壁可與空腔116的內側壁間隔開。因此，電容器200的側壁與空腔116的內側壁之間可形成有間隙。舉例而言，支撐基板110可具有數個或數十個空腔116，且空腔116中的每一者中可設置有一個電容器200。作為另一選擇，一個空腔116內可設置有多個電容器200。
如圖2中所示，電容器200可具有第一電極210a及第二電極210b。電容器200的上表面202自支撐基板110的上表面112暴露出。電容器200的下表面204自支撐基板110的下表面114暴露出。設置於電容器200的上表面202上的第一電極210a及第二電極210b的表面可與支撐基板110的上表面112共面。
電容器200可用作用於使半導體晶片300的電壓穩定化的解耦電容器。電容器200可包括多層陶瓷電容器（multilayer ceramic capacitor，MLCC）、矽電容器等。電容器200可具有數百奈法拉（nanofarad，nF）的電容。多層陶瓷電容器的實例可為垂直堆疊的三端子型低電感晶片電容器（low inductance chip capacitor，LICC）、多端子型低等效串聯電感（equivalent series inductance，ESL）MLCC、具有其中電極僅在下面的結構的MLCC等。
舉例而言，電容器200的厚度T1可大於或等於支撐基板110的厚度T2。因此，電容器200的與第一表面202相對的第二表面204可與支撐基板110的第二表面114共面或者被定位成高於支撐基板110的第二表面114。電容器200的厚度T1可在50微米至250微米的範圍內。電容器200的寬度W1可在450微米至900微米的範圍內。電容器200的第一電極210a及第二電極210b的寬度可在150微米至300微米的範圍內。
在本揭露的示例性實施例中，混合堆疊基板100可更包括密封層130，密封層130設置於支撐基板110的第二表面114上且覆蓋電容器200。密封層130可填充電容器200的側壁與空腔116的內側壁之間的間隙。因此，密封層130可覆蓋電容器200的第二表面204、支撐基板110的第二表面114及空腔116的內側壁。
舉例而言，密封層130可包含例如環氧樹脂等熱固性樹脂、例如聚醯亞胺等熱塑性樹脂、包括例如無機填料等加強材料的樹脂等。舉例而言，密封層可包含例如味之素構成膜（Ajinomoto Build-up Film，ABF）等絕緣膜、例如弗朗克功能調節劑4（Frankel’s function regulator-4，FR-4）等複合材料、例如雙馬來醯亞胺三嗪（Bismaleimide Triazine，BT）等樹脂等。密封層可包含例如環氧模製化合物（Epoxy Molding Compound，EMC）等模製材料、例如感光成像包封體（Photo Imageable Encapsulant，PIE）等感光性絕緣材料等。
在本揭露的示例性實施例中，重佈線配線層140可設置於支撐基板110的第一表面112及電容器200的第一表面202上。重佈線配線層140可包括分別電性連接至電容器200的第一電極210a及第二電極210b以及連接配線122的重佈線配線152。
舉例而言，重佈線配線層140可包括第一下部絕緣層150a及第一重佈線配線152a，第一下部絕緣層150a設置於支撐基板110的上表面112上且具有分別暴露出電容器200的第一電極210a及第二電極210b以及連接配線122的第一金屬配線122a的第一開口，第一重佈線配線152a設置於第一下部絕緣層上且經由第一開口分別電性連接至第一電極210a及第二電極210b以及第一金屬配線122a。
重佈線配線層140可包括第二下部絕緣層150b及第二重佈線配線152b，第二下部絕緣層150b設置於第一下部絕緣層150a上且具有暴露出第一重佈線配線152a的第二開口，第二重佈線配線152b經由第二開口分別電性連接至第一重佈線配線152a。
重佈線配線層140可包括第三下部絕緣層150c及第三重佈線配線152c，第三下部絕緣層150c設置於第二下部絕緣層150b上且具有暴露出第二重佈線配線152b的第三開口，第三重佈線配線152c經由第三開口分別電性連接至第二重佈線配線152b。
重佈線配線層140可包括設置於第三下部絕緣層150c上的保護圖案，以暴露出第三重佈線配線152c的至少部分。在此種情形中，第三重佈線配線152c的藉由保護圖案暴露出的部分上可形成有例如凸塊下金屬（Under Bump Metallurgy，UBM）等凸塊接墊。第三重佈線配線152c的上面形成有凸塊接墊的部分可用作接合接墊。
舉例而言，第一下部絕緣層至第三下部絕緣層可包括聚合物層、介電層等。第一下部絕緣層至第三下部絕緣層可包含感光性絕緣材料（感光成像介電質（Photo Imageable Dielectric，PID））、例如ABF等絕緣膜等。第一重佈線配線至第三重佈線配線可包含鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、鉑（Pt）或前述金屬中的至少一者的合金。
因此，混合堆疊基板100可包括支撐基板110及重佈線配線層140以用作高密度中介層，支撐基板110中嵌置有例如電容器200等被動元件，重佈線配線層140堆疊於支撐基板100上且具有分別電性連接至電容器200的第一電極210a及第二電極210b的重佈線配線152。
在本揭露的示例性實施例中，半導體晶片300可安裝於混合堆疊基板100的重佈線配線層140上。半導體晶片300可以倒裝晶片接合方式安裝於重佈線配線層140上。在此種情形中，半導體晶片300可安裝於重佈線配線層140上，進而使得半導體晶片300的晶片接墊310面對重佈線配線層140。半導體晶片300的晶片接墊310可藉由作為導電連接件的導電凸塊320電性連接至例如重佈線配線層140的第三重佈線配線152c等接合接墊。舉例而言，導電凸塊320可包括微凸塊（micro bump）（u凸塊（uBump））。
模製件400可設置於重佈線配線層140上且可覆蓋半導體晶片300。舉例而言，模製件400可包含環氧模製化合物（EMC）。
在本揭露的示例性實施例中，外連接件500可設置於位於支撐基板110的下表面114上的密封層130的下表面上，且可分別電性連接至連接配線122。
連接配線122的第三金屬配線122e可藉由形成於密封層130中的開口暴露出。例如UBM等凸塊接墊可形成於第三金屬配線122e的藉由開口暴露出的部分上。外連接件500可安裝於密封層130的外表面上。外連接件500可分別設置於第三金屬配線122e上的凸塊接墊上。外連接件500可藉由形成於密封層130中的開口分別電性連接至連接配線122。舉例而言，外連接件500可包括焊料球。焊料球可具有在300微米至500微米的範圍內的直徑。
半導體封裝10可藉由焊料球安裝於模組基板上，以構成記憶體模組。
如上所述，半導體封裝10可包括混合堆疊基板100、安裝於混合堆疊基板100上的所述至少一個半導體晶片300及設置於混合堆疊基板100的外表面上的外連接件500，混合堆疊基板100具有支撐基板110及重佈線配線層140，支撐基板110中嵌置有所述至少一個電容器200，重佈線配線層140堆疊於支撐基板110上且具有分別電性連接至電容器200的第一電極210a及第二電極210b以及支撐基板110的連接配線122的重佈線配線152。
因此，由於電容器200設置於支撐基板110的空腔116中，因此電容器200可具有較常規的著落側電容器（LSC）型電容器的厚度大的厚度。因此，可減少或防止在電容器200的表面安裝期間可能出現的缺陷。此外，可在不使用積體被動裝置（integrated passive device，IPD）或超薄電容器的情況下增加電容，以藉此降低電容器的成本。
此外，由於電容器200設置於支撐基板110中的所期望位置處，因此可減少與半導體晶片300的連接路徑，以增強例如迴路電感（loop inductance）等電性效能。
在下文中，將闡釋製造圖1中的半導體封裝的方法。
圖3至圖13是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。
參照圖3至圖5，可製備其中形成有多個支撐基板110的面板，可在支撐基板110的空腔116內設置至少一個電容器200，且然後，密封層130可覆蓋電容器200。
在本揭露的示例性實施例中，可使用支撐基板110作為用於製造具有扇出面板級封裝配置的半導體封裝的電性連接的支撐框架。
舉例而言，面板可包括上面形成有支撐基板110的框架區FR及至少局部地環繞框架區FR的切割道區（例如，切割區CA）。如稍後所述，可沿劃分框架區FR的切割區CA鋸切面板，以形成各別的支撐基板110。
支撐基板110可具有彼此相對的第一表面112與第二表面114。支撐基板110可在框架區FR的中間區中具有空腔116。如稍後所述，空腔116可具有用於接納至少一個電容器的區域。
支撐基板110可為藉由嵌置跡線基板（ETS）方法形成的無核心基板。在此種情形中，支撐基板110可包括多個絕緣層及位於所述絕緣層中的電路層。作為另一選擇，支撐基板可為核心多層式基板。在此種情形中，核心多層式基板可包括堆疊於核心層的上表面與下表面二者上的核心層及電路層。
如圖3中所示，支撐基板110可包括多個堆疊的絕緣層120a及120b以及在所述絕緣層中作為電性導體提供的連接配線122。多個連接配線122可自支撐基板110的第一表面112至第二表面114穿透過支撐基板110，以用作電性連接路徑。
舉例而言，支撐基板110可包括第一絕緣層120a及堆疊於第一絕緣層120a上的第二絕緣層120b。連接配線122可包括第一金屬配線122a、第一接觸件122b、第二金屬配線122c、第二接觸件122d及第三金屬配線122e。第一金屬配線122a可設置於支撐基板110的第一表面112上（例如，設置於第一絕緣層120a的下表面中），且第一金屬配線122a的至少一部分可自第一表面112暴露出。第三金屬配線122e可設置於支撐基板110的第二表面114上（例如，設置於第二絕緣層120b的上表面中），且第三金屬配線122e的至少一部分可自第二表面114暴露出。可理解，支撐基板110的絕緣層及核心連接配線的數目及佈置可能不限於此。
如圖4中所示，可將面板設置於障壁帶（barrier tape）（或作為另一選擇，載帶（carrier tape））20上，且可將所述至少一個電容器200設置於支撐基板110的空腔116內。
可將支撐基板110的第一表面112黏合於障壁帶20上。舉例而言，支撐基板110可具有數個或數十個空腔116，且可在空腔116中的每一者中設置一個電容器200。如稍後所述，可執行單體化或鋸切製程來鋸切面板，以完成扇出面板級封裝。在本揭露的一些示例性實施例中，可在一個空腔116內設置多個電容器200。
電容器200可具有第一電極210a及第二電極210b。電容器200的第一表面202可面對障壁帶20。設置於電容器200的第一表面202中的第一電極210a及第二電極210b的表面可與支撐基板110的第一表面112共面。
可將電容器200設置於支撐基板110的空腔116內。電容器200的側壁可與空腔116的內側壁間隔開。因此，可在電容器200的側壁與空腔116的內側壁之間形成間隙。
舉例而言，電容器200的厚度可大於或等於支撐基板110的厚度。因此，電容器200的與第一表面202相對的第二表面204可與支撐基板110的第二表面114共面或者被定位成高於支撐基板110的第二表面114。電容器200可包括多層陶瓷電容器（MLCC）、矽電容器或類似物。電容器200的厚度可在50微米至250微米的範圍內。電容器200的寬度可在450微米至900微米的範圍內。電容器200的第一電極210a及第二電極210b的寬度可在150微米至300微米的範圍內。
如圖5中所示，可在支撐基板110的第二表面114上形成密封層130，且密封層130可覆蓋電容器200。密封層130可至少局部地填充電容器200的側壁與空腔116的內側壁之間的間隙。因此，密封層130可覆蓋電容器200的第二表面204、支撐基板110的第二表面114及空腔116的內側壁。
舉例而言，密封層130可包含例如環氧樹脂等熱固性樹脂、例如聚醯亞胺等熱塑性樹脂、包括例如無機填料等加強材料的樹脂等。舉例而言，密封層可包含例如味之素構成膜（ABF）等絕緣膜、例如FR-4等複合材料、例如雙馬來醯亞胺三嗪（BT）等樹脂等。密封層可包含例如環氧模製化合物（EMC）等模製材料、例如感光成像包封體（PIE）等感光性絕緣材料等。
參照圖6至圖9，可在支撐基板110的第一表面112及電容器200的第一表面202上形成重佈線配線層140。重佈線配線層140可包括分別電性連接至電容器200的第一電極210a及第二電極210b以及連接配線122的重佈線配線152。重佈線配線層140可為扇出封裝的前重佈線配線層。
如圖6及圖7中所示，在移除障壁帶20之後，可將圖5中的結構顛倒，且可將密封層130黏合於載體基板C上。然後，第一下部絕緣層150a可覆蓋支撐基板110的第一表面112及電容器200的前表面202，且然後，可對第一下部絕緣層150a進行圖案化以形成第一開口151a，第一開口151a分別暴露出電容器200的第一電極210a及第二電極210b以及核心連接配線120的第一金屬配線122a。
舉例而言，第一下部絕緣層150a可包括聚合物層、介電層等。第一下部絕緣層150a可包括PID、例如ABF等絕緣膜等。可藉由氣相沈積製程、旋轉塗佈製程等形成第一下部絕緣層150a。
如圖8中所示，可在第一下部絕緣層150a上形成第一重佈線配線152a。第一重佈線配線152a可分別藉由第一開口接觸第一電極210a及第二電極210b以及第一金屬配線122a。可藉由在第一下部絕緣層150a的一部分上及第一開口中形成晶種層、對晶種層進行圖案化以及執行電鍍製程來形成第一重佈線配線152a。因此，第一重佈線配線152a的至少部分可經由第一開口接觸第一電極210a及第二電極210b以及第一金屬配線122。
舉例而言，可藉由濺鍍製程形成晶種層。晶種層可包括合金層，所述合金層包含鈦/銅（Ti/Cu）、鈦/鈀（Ti/Pd）、鈦/鎳（Ti/Ni）、鉻/銅（Cr/Cu）或其組合。第一重佈線配線可包含鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、鉑（Pt）或其合金。
如圖9中所示，可在第一下部絕緣層150a上形成第二下部絕緣層150b，且然後，可對第二下部絕緣層150b進行圖案化以形成分別暴露出第一重佈線配線152a的第二開口。然後，可在第二下部絕緣層150b上形成第二下部重佈線配線152b。第二重佈線配線152b可經由第二開口分別接觸第一重佈線配線152a。
相似地，可在第二下部絕緣層150b上形成第三下部絕緣層150c，且然後，可對第三下部絕緣層150c進行圖案化以形成分別暴露出第二重佈線配線152b的第三開口。然後，可在第三下部絕緣層150c上形成第三重佈線配線152c。第三重佈線配線152c可經由第三開口分別接觸第二重佈線配線152b。
然後，可在第三下部絕緣層150c上形成保護圖案，以暴露出第三重佈線配線152c的至少部分。在此種情形中，可在第三重佈線配線152c的藉由保護圖案暴露出的部分上形成例如凸塊下金屬（UBM）等凸塊接墊。第三重佈線配線152c的上面形成有凸塊接墊的部分可用作接合接墊。
因此，重佈線配線層140可設置於支撐基板110的第一表面112上，且可包括分別電性連接至第一電極210a及第二電極210b以及連接配線122的重佈線配線152。可理解，下部絕緣層及重佈線配線層的重佈線配線的數目、大小、佈置等是被示例性地示出，且因此，本發明不必限於此。
因此，可形成混合堆疊基板100，混合堆疊基板100包括支撐基板110及重佈線配線層140，支撐基板110具有例如電容器200等被動元件，重佈線配線層140堆疊於支撐基板100上且具有分別電性連接至電容器200的第一電極210a及第二電極210b的重佈線配線152。
參照圖10及圖11，可在重佈線配線層140上安裝半導體晶片300，且可在重佈線配線層140上形成模製件400，且模製件400可覆蓋半導體晶片300。
如圖10中所示，可以倒裝晶片接合方式在重佈線配線層140上安裝半導體晶片300。半導體晶片300可包括基板及設置於基板的前表面302（例如，基板的主動表面）上的晶片接墊310。半導體晶片300的晶片接墊310可面對重佈線配線層140。可藉由導電凸塊320將半導體晶片300的晶片接墊310電性連接至例如重佈線配線層140的第三重佈線配線152c等接合接墊。舉例而言，導電凸塊320可包括微凸塊（u凸塊）。
如圖11中所示，可在重佈線配線層140上形成模製件400，且模製件400可覆蓋半導體晶片300。舉例而言，模製件400可包括環氧模製化合物（EMC）。
參照圖12及圖13，可在密封層130的下表面上設置外連接件500，且外連接件500可分別電性連接至連接配線122。
如圖12中所示，在移除載體基板C之後，可局部地移除支撐基板110的第二表面114上的密封層130，以形成暴露出連接配線122的第三金屬配線122e的開口131。可在第三金屬配線122e上形成例如UBM等凸塊接墊。
如圖13中所示，可將外連接件500安裝於密封層130的外表面上。可經由開口131將外連接件500分別電性連接至連接配線122。舉例而言，外連接件500可包括焊料球。
然後，可執行鋸切製程以形成各別的混合堆疊基板100，以完成包括安裝於混合堆疊基板100上的半導體晶片300的扇出面板級封裝。
圖14是示出根據本揭露示例性實施例的半導體封裝的剖視圖。除附加的下部重佈線配線層以外，半導體封裝可與參照圖1闡述的半導體封裝實質上相同或相似。因此，相同的參考編號將用於指代相同或類似的元件，且在已省略對元件的詳細說明的情況下，可假定所述元件至少相似於說明書中其他地方已闡述的對應元件。
參照圖14，半導體封裝11的混合堆疊基板100可更包括設置於密封層130的下表面上的下部重佈線配線層。下部重佈線配線層可包括分別電性連接至支撐基板110的連接配線122的下部重佈線配線162。
在本揭露的示例性實施例中，下部重佈線配線層可包括經由形成於密封層130中的開口分別電性連接至第三金屬配線122e的下部重佈線配線162。
下部重佈線配線層可包括設置於密封層130上的保護圖案160，以暴露出下部重佈線配線162的至少部分。在此種情形中，可在下部重佈線配線162的藉由保護圖案暴露出的部分上形成例如UBM等凸塊接墊。下部重佈線配線162的上面形成有凸塊接墊的部分可用作例如封裝接墊等著落接墊（landing pad）。
外連接件500可設置於下部重佈線層的外表面上的封裝接墊上。舉例而言，外連接件500可包括焊料球。半導體封裝11可藉由焊料球安裝於模組基板上，以形成記憶體模組。
因此，焊料球可自由地設置於混合堆疊基板100的整個下表面之上，以藉此增加設計自由度。
在下文中，將闡釋製造圖14中的半導體封裝的方法。
圖15是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。
參照圖15，首先，可執行與參照圖3至圖5闡述的製程相同或相似的製程，以形成覆蓋設置於支撐基板110的空腔116內的電容器200的密封層130，且可在密封層130上形成下部重佈線配線層。下部重佈線配線層可包括電性連接至支撐基板110的連接配線的下部重佈線配線162。
在本揭露的示例性實施例中，可對密封層130進行圖案化以形成分別暴露出連接配線122的第三金屬配線122e的開口。然後，可在密封層130上形成下部重佈線配線162，以經由所述開口分別接觸第三金屬配線122e。
可藉由在密封層130的一部分上及開口中形成晶種層、對晶種層進行圖案化及執行電鍍製程來形成下部重佈線配線162。因此，可經由開口將下部重佈線配線162電性連接至第二金屬配線122b。
然後，可在密封層130上形成保護圖案160，以暴露出下部重佈線配線162的至少部分。在此種情形中，可藉由隨後的鍍覆製程在下部重佈線配線162的藉由保護圖案暴露出的部分上形成例如UBM等凸塊接墊。下部重佈線配線162的上面形成有凸塊接墊的部分可用作例如封裝接墊等著落接墊。
然後，可執行與參照圖6至圖13闡述的製程相同或相似的製程，以形成圖14中的半導體封裝。
圖16是示出根據本揭露示例性實施例的半導體封裝的剖視圖。除附加的中介層及附加的第二封裝以外，半導體封裝可與參照圖14闡述的半導體封裝實質上相同或相似。因此，相同的參考編號將用於指代相同或類似的元件，且在已省略對元件的詳細說明的情況下，可假定所述元件至少相似於說明書中其他地方已闡述的對應元件。
參照圖16，半導體封裝12可包括第一封裝、堆疊於第一封裝上的中介層600及堆疊於中介層600上的第二封裝700。第一封裝可包括混合堆疊基板100、安裝於混合堆疊基板100上的至少一個半導體晶片300、在混合堆疊基板100上覆蓋半導體晶片300的模製件400以及設置於混合堆疊基板100的下表面上的外連接件500。第一封裝可與參照圖1闡述的單位封裝實質上相同或相似。
在本揭露的示例性實施例中，第二封裝700可藉由中介層600堆疊於第一封裝上。
中介層600可藉由第一導電連接件550堆疊於第一封裝上。中介層600可包括中介層基板610以及設置於中介層基板610的上表面及下表面上的第一連接接墊612及第二連接接墊614。第一連接接墊612與第二連接接墊614可藉由中介層600的內配線彼此電性連接。
第一導電連接件550可穿透模製件400的至少一部分。開口可設置於模製件400中，以暴露出重佈線配線層140的第三重佈線配線152c，且第一導電連接件550可設置於開口中且電性連接至第三重佈線配線152c。第一導電連接件550可自模製件400的上表面突出。中介層600的第二連接接墊614可分別接觸自模製件400的上表面突出的第一導電連接件550。舉例而言，第一導電連接件可包含導電材料（例如焊料球、導電柱等）。
在本揭露的示例性實施例中，第二封裝700可藉由第二導電連接件650堆疊於中介層600上。舉例而言，第二導電連接件可包括焊料球、導電凸塊等。第二導電連接件650可夾置於中介層600的第一連接接墊612與第二封裝基板670的第二接合接墊714之間。因此，第一封裝與第二封裝700可藉由第一導電連接件550、中介層600及第二導電連接件650彼此電性連接。
第二半導體晶片720及第三半導體晶片730可藉由黏合膜堆疊於第二封裝基板710上。接合配線740可將第二半導體晶片720及第三半導體晶片730的晶片接墊722及732連接至第二封裝基板710的第一接合接墊712。第二半導體晶片720及第三半導體晶片730可藉由接合配線740電性連接至第二封裝基板710。
儘管第二封裝700包括藉由打線接合（wire bonding）方法安裝的兩個半導體晶片，然而應理解，第二封裝的半導體晶片的數目、安裝方法等不必限於二個。
熱匯（heat sink）可設置於第二封裝700上，以將熱量自第一封裝及第二封裝發散至環境。熱匯可藉由熱介面材料（thermal interface material，TIM）貼合於第二封裝700上。
在下文中，將闡釋製造圖16中所示半導體封裝的方法。
圖17是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。
參照圖17，首先，可執行與參照圖3至圖13闡述的製程相同或相似的製程以形成第一封裝，且可在第一封裝上堆疊中介層600以形成下部封裝（中介層疊層封裝（interposer Package-on-Package，i-POP））。
在本揭露的示例性實施例中，可移除模製件400的至少一部分以形成暴露出重佈線配線層140的第三重佈線配線152c的開口，且可在所述開口中設置第一導電連接件550。可將第一導電連接件550電性連接至第三重佈線配線152c。第一導電連接件550可自模製件400的上表面突出。舉例而言，第一導電連接件可包含導電材料（例如焊料球、導電柱等）。
然後，可藉由第一導電連接件550將中介層600堆疊於模製件400上。中介層600可包括中介層基板610以及設置於中介層基板610的上表面及下表面上的第一連接接墊612及第二連接接墊614。中介層600的第二連接接墊614可分別接觸自模製件400的上表面突出的第一導電連接件550。
然後，可藉由第二導電連接件650將第二封裝700堆疊於中介層600上。舉例而言，第二導電連接件650可包括焊料球、導電凸塊等。第二導電連接件650可夾置於中介層600的第一連接接墊612與第二封裝基板670的第二接合接墊714之間。因此，第一封裝與第二封裝700可藉由第一導電連接件550、中介層600及第二導電連接件650彼此電性連接。
圖18是示出根據本揭露示例性實施例的半導體封裝的剖視圖。除與電容器的電極的電性連接以外，半導體封裝可與參照圖14闡述的半導體封裝實質上相同或相似。因此，相同的參考編號將用於指代相同或類似的元件，且在已省略對元件的詳細說明的情況下，可假定所述元件至少相似於說明書中其他地方已闡述的對應元件。
參照圖18，半導體封裝13的混合堆疊基板100可更包括設置於密封層130的下表面上的下部重佈線配線層。下部重佈線配線層可包括分別電性連接至支撐基板110的連接配線122的第一下部重佈線配線162。下部重佈線配線層可包括分別電性連接至電容器200的第一電極210a及第二電極210b的第二下部重佈線配線163。
在本揭露的示例性實施例中，第二下部重佈線配線163可經由形成於密封層130中的開口電性連接至設置於電容器200的下表面204上的第一電極210a及第二電極210b。
在本揭露的示例性實施例中，開口可形成於密封層130中，以分別暴露出設置於電容器200的下表面204上的第一電極210a及第二電極210b。第二下部重佈線配線162可經由開口電性連接至設置於電容器200的下表面204上的第一電極210a及第二電極210b。第二下部重佈線配線163可電性連接至支撐基板110的第三金屬配線122e。
因此，電容器200的第一電極210a及第二電極210b可分別電性連接至支撐基板110的連接配線122及重佈線配線層140的重佈線配線152。
圖19是示出根據本揭露示例性實施例的半導體封裝的剖視圖。除附加的封裝基板以外，半導體封裝可與參照圖14闡述的半導體封裝實質上相同或相似。因此，相同的參考編號將用於指代相同或類似的元件，且在已省略對元件的詳細說明的情況下，可假定所述元件至少相似於說明書中其他地方已闡述的對應元件。
參照圖19，半導體封裝14可包括封裝基板800、安裝於封裝基板800上的混合堆疊基板100以及安裝於混合堆疊基板100上的半導體晶片300。半導體封裝14可包括設置於混合堆疊基板100上的覆蓋半導體晶片300的模製件400。混合堆疊基板可與參照圖14闡述的混合堆疊基板實質上相同或相似。
在本揭露的示例性實施例中，半導體封裝14可物理連接至及/或電性連接至主板，以用作電子裝置的晶片相關組件。電子裝置可為網路系統。半導體封裝14可為作為晶片相關組件的BGA封裝。
為緩衝半導體晶片300的晶片接墊與主板的安裝接墊之間的節距差異，包括安裝於其上的半導體晶片300的混合堆疊基板100可安裝並封裝於封裝基板800上，且最終，封裝基板800可安裝於主板上以被設置為網路系統的晶片相關組件。
在本揭露的示例性實施例中，混合堆疊基板100可藉由連接件500安裝於封裝基板800上。
舉例而言，封裝基板800可包括例如高密度印刷電路板（high-density printed circuit board，HDI PCB）等核心多層式基板。封裝基板可包括核心層810以及堆疊於核心層810的上表面與下表面二者上的電路層812a及812b。保護層814a及814b（例如阻焊層）可形成於電路層的最外層上。電路層中的每一者可包括電路圖案。通孔815可形成於核心層810中，且電路層812a及812b中的電路圖案可藉由通孔815彼此電性連接。應領會，用作封裝基板的核心多層式基板是以實例的方式闡述，且本發明不必限於此。
因此，封裝基板800的電路圖案可藉由連接件500電性連接至混合堆疊100的連接配線122。
半導體封裝14可藉由封裝連接端子安裝於主板上。封裝連接端子可包括設置於封裝基板800的下表面上的外部連接端子上的焊料球。
半導體封裝可包括例如邏輯裝置或記憶體裝置等半導體裝置。半導體封裝可包括：邏輯裝置，例如中央處理單元（central processing unit，CPU）、主處理單元（main processing unit，MPU）或應用處理器（application processor，AP）或類似物；以及揮發性記憶體裝置，例如DRAM裝置、高頻寬記憶體（high bandwidth memory，HBM）裝置；或者非揮發性記憶體裝置，例如快閃記憶體裝置、PRAM裝置、MRAM裝置、ReRAM裝置或類似物。
前述內容是對本揭露示例性實施例的例示。儘管已闡述幾個示例性實施例，然而熟習此項技術者將容易領會，在不本質上背離本揭露的新穎教導內容及態樣的情況下，可在示例性實施例中作出諸多修改。
10、11、12、13、14:半導體封裝 20:障壁帶 100:混合堆疊基板 110:支撐基板 112:第一表面/上表面 114:第二表面/下表面 116:空腔 120a:第一絕緣層/絕緣層 120b:第二絕緣層/絕緣層 122:連接配線 122a:第一金屬配線 122b:第一接觸件 122c:第二金屬配線 122d:第二接觸件 122e:第三金屬配線 130:密封層 131:開口 140:重佈線配線層 150a:第一下部絕緣層 150b:第二下部絕緣層 150c:第三下部絕緣層 151a:第一開口 152:重佈線配線 152a:第一重佈線配線 152b:第二重佈線配線 152c:第三重佈線配線 160:保護圖案 162:下部重佈線配線/第一下部重佈線配線 163:第二下部重佈線配線 200:電容器 202:第一表面/上表面 204:下表面/第二表面 210a:第一電極 210b:第二電極 300:半導體晶片 302:前表面 310:晶片接墊 320:導電凸塊 400:模製件 500:外連接件/連接件 550:第一導電連接件 600:中介層 610:中介層基板 612:第一連接接墊 614:第二連接接墊 650:第二導電連接件 700:第二封裝 710:第二封裝基板 712:第一接合接墊 714:第二接合接墊 720:第二半導體晶片 722、732:晶片接墊 730:第三半導體晶片 740:接合配線 800:封裝基板 810:核心層 812a、812b:電路層 814a、814b:保護層 815:通孔 A:部分 C:載體基板 FR:框架區 T1、T2:厚度 W1:寬度
由於當結合附圖考量時藉由參照以下詳細說明會更佳地理解本揭露及其諸多隨附態樣，因此將容易獲得對本揭露及其諸多隨附態樣的更完整領會，在附圖中： 圖1是示出根據本揭露示例性實施例的半導體封裝的剖視圖。 圖2是示出圖1中的部分「A」的放大剖視圖。 圖3至圖13是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。 圖14是示出根據本揭露示例性實施例的半導體封裝的剖視圖。 圖15是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。 圖16是示出根據本揭露示例性實施例的半導體封裝的剖視圖。 圖17是示出根據本揭露示例性實施例的製造半導體封裝的方法的剖視圖。 圖18是示出根據本揭露示例性實施例的半導體封裝的剖視圖。 圖19是示出根據本揭露示例性實施例的半導體封裝的剖視圖。
10:半導體封裝
100:混合堆疊基板
110:支撐基板
112:第一表面/上表面
114:第二表面/下表面
116:空腔
120a:第一絕緣層/絕緣層
120b:第二絕緣層/絕緣層
122:連接配線
122a:第一金屬配線
122b:第一接觸件
122c:第二金屬配線
122d:第二接觸件
122e:第三金屬配線
130:密封層
140:重佈線配線層
150a:第一下部絕緣層
150b:第二下部絕緣層
150c:第三下部絕緣層
151a:第一開口
152:重佈線配線
152a:第一重佈線配線
152b:第二重佈線配線
152c:第三重佈線配線
200:電容器
202:第一表面/上表面
204:下表面/第二表面
210a:第一電極
210b:第二電極
300:半導體晶片
302:前表面
310:晶片接墊
320:導電凸塊
400:模製件
500:外連接件/連接件
A:部分

Claims (20)

  1. 一種半導體封裝，包括： 支撐基板，包括設置於所述支撐基板上的連接配線； 至少一個電容器，設置於所述支撐基板上，所述至少一個電容器具有自所述支撐基板的上表面暴露出的第一電極及第二電極； 重佈線配線層，覆蓋所述支撐基板的所述上表面，所述重佈線配線層具有分別電性連接至所述連接配線以及所述第一電極及所述第二電極的重佈線配線； 半導體晶片，設置於所述重佈線配線層上，所述半導體晶片具有電性連接至所述重佈線配線的晶片接墊；以及 外連接件，設置於所述支撐基板的下表面上且電性連接至所述連接配線。
  2. 如請求項1所述的半導體封裝，其中所述支撐基板包括空腔，且所述至少一個電容器設置於所述空腔中。
  3. 如請求項2所述的半導體封裝，其中所述至少一個電容器的上表面自所述支撐基板的所述上表面暴露出。
  4. 如請求項2所述的半導體封裝，其中所述空腔穿透過所述支撐基板，且 所述半導體封裝更包括： 密封層，至少局部地填充所述空腔且覆蓋所述支撐基板的下表面。
  5. 如請求項4所述的半導體封裝，其中所述外連接件設置於所述密封層的下表面上，且所述外連接件經由形成於所述密封層中的開口分別電性連接至所述連接配線。
  6. 如請求項4所述的半導體封裝，更包括： 下部重佈線配線層，設置於所述密封層的下表面上，所述下部重佈線配線層包括電性連接至所述連接配線的下部重佈線配線。
  7. 如請求項6所述的半導體封裝，其中所述外連接件設置於所述下部重佈線配線層上，且所述外連接件分別電性連接至所述下部重佈線配線層的所述下部重佈線配線。
  8. 如請求項1所述的半導體封裝，其中所述至少一個電容器的厚度大於或等於所述支撐基板的厚度。
  9. 如請求項1所述的半導體封裝，更包括： 模製件，設置於所述重佈線配線層上且覆蓋所述半導體晶片。
  10. 如請求項9所述的半導體封裝，更包括： 多個導電連接件，穿透過所述模製件的至少一部分，所述導電連接件分別電性連接至所述重佈線配線層的所述重佈線配線。
  11. 一種半導體封裝，包括： 支撐基板，包括穿透過所述支撐基板的空腔； 至少一個電容器，設置於所述支撐基板的所述空腔內，所述至少一個電容器具有自所述支撐基板的上表面暴露出的第一電極及第二電極； 密封層，至少局部地填充所述空腔且覆蓋所述支撐基板的下表面； 重佈線配線層，覆蓋所述支撐基板的所述上表面，所述重佈線配線層具有分別電性連接至所述支撐基板以及所述第一電極及所述第二電極的重佈線配線； 半導體晶片，設置於所述重佈線配線層上，所述半導體晶片具有分別電性連接至所述重佈線配線的晶片接墊；以及 外連接件，設置於所述密封層的下表面上且電性連接至所述支撐基板。
  12. 如請求項11所述的半導體封裝，其中所述至少一個電容器的所述第一電極及所述第二電極的表面與所述支撐基板的所述上表面共面。
  13. 如請求項11所述的半導體封裝，其中所述至少一個電容器的上表面自所述支撐基板的所述上表面暴露出。
  14. 如請求項11所述的半導體封裝，其中所述半導體晶片藉由夾置於所述晶片接墊與所述重佈線配線之間的導電凸塊安裝於所述重佈線配線層上。
  15. 如請求項11所述的半導體封裝，其中所述至少一個電容器的厚度大於或等於所述支撐基板的厚度。
  16. 如請求項11所述的半導體封裝，其中所述至少一個電容器的厚度在50微米至250微米的範圍內。
  17. 如請求項11所述的半導體封裝，其中所述外連接件經由形成於所述密封層中的開口分別電性連接至所述支撐基板。
  18. 如請求項11所述的半導體封裝，更包括： 下部重佈線配線層，設置於所述密封層的下表面上，所述下部重佈線配線層具有電性連接至所述支撐基板的下部重佈線配線。
  19. 如請求項18所述的半導體封裝，其中所述外連接件設置於所述下部重佈線配線層上，且所述外連接件分別電性連接至所述下部重佈線配線層的所述下部重佈線配線。
  20. 如請求項11所述的半導體封裝，更包括： 多個導電連接件，分別電性連接至所述重佈線配線層的所述重佈線配線；以及 中介層，藉由所述導電連接件設置於所述密封層上。
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JP2010171414A (ja) * 2008-12-26 2010-08-05 Ngk Spark Plug Co Ltd 部品内蔵配線基板の製造方法
US9204552B2 (en) * 2012-01-26 2015-12-01 Ibiden Co., Ltd. Printed wiring board
KR101420526B1 (ko) * 2012-11-29 2014-07-17 삼성전기주식회사 전자부품 내장기판 및 그 제조방법
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