CN110364513A - 半导体芯片和包括半导体芯片的半导体封装 - Google Patents

半导体芯片和包括半导体芯片的半导体封装 Download PDF

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CN110364513A
CN110364513A CN201910212737.2A CN201910212737A CN110364513A CN 110364513 A CN110364513 A CN 110364513A CN 201910212737 A CN201910212737 A CN 201910212737A CN 110364513 A CN110364513 A CN 110364513A
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chip
semiconductor
semiconductor chip
substrate
redistribution lines
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CN110364513B (zh
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吴承桓
吴琼硕
金吉洙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

半导体封装可以包括封装基板、位于封装基板上的第一半导体芯片以及位于第一半导体芯片上的第二半导体芯片。第一半导体芯片包括：芯片基板，包括第一表面和与第一表面相对的第二表面；多个第一芯片焊盘，位于封装基板和芯片基板的第一表面之间，并且将第一半导体芯片电连接到封装基板；多个第二芯片焊盘，设置于芯片基板的第二表面上，并且位于第二半导体芯片与芯片基板的第二表面之间；多个再分布线，位于芯片基板的第二表面上，再分布线电连接至第二半导体芯片；多个接合线，将再分布线电连接至封装基板。

Description

半导体芯片和包括半导体芯片的半导体封装
相关申请的交叉引用
本申请要求于2018年3月26日在韩国知识产权局递交的韩国专利申请No.10-2018-0034454的优先权，其全部内容通过引用合并在此。
技术领域
本发明的构思涉及一种半导体芯片和包括半导体芯片的半导体封装，更具体地，涉及一种包括再分布层的半导体芯片和包括该半导体芯片的半导体封装。
背景技术
半导体器件由于其小尺寸、多功能性和/或低制造成本而广泛用于电子工业中。半导体器件可以包括用于存储数据的存储器件、用于处理数据的逻辑器件以及用于同时操作各种功能的混合器件。
随着电子工业的先进发展，半导体器件越来越需要高集成度。随着电子工业的先进发展，半导体器件越来越需要高速度。为了满足半导体器件中高集成度和/或高速度的要求，已经进行了各种研究。
发明内容
本发明构思的一些实施例提供了一种具有增加的热辐射能力的半导体封装。
本发明构思的一些实施例提供了一种具有改善的电特性的半导体封装。
本发明构思的一些实施例提供了一种包括再分布层在内的半导体芯片。
本发明构思的目的不限于上述目的，并且根据以下描述，本领域技术人员将清楚地理解上文未提及的其它目的。
根据一些示例性实施例，半导体封装可以包括：封装基板；位于封装基板上的第一半导体芯片；以及位于第一半导体芯片上的第二半导体芯片。第一半导体芯片可以包括：芯片基板，包括第一表面和与第一表面相对的第二表面；多个第一芯片焊盘，位于封装基板和芯片基板的第一表面之间，并且将第一半导体芯片电连接到封装基板；多个第二芯片焊盘，设置于第二表面上，并且位于第二半导体芯片与第二表面之间；以及多个再分布线，位于第二表面上，再分布线电连接至第二半导体芯片。多个第一接合线，将所述再分布线电连接到所述封装基板。
根据一些示例性实施例，半导体封装可以包括：封装基板；位于封装基板上的第一半导体芯片；以及位于第一半导体芯片上的第二半导体芯片。第一半导体芯片可以包括：芯片基板，包括第一表面和与所述第一表面相对的第二表面；多个第一芯片焊盘，位于所述封装基板和所述芯片基板的第一表面之间，并且所述第一芯片焊盘将所述第一半导体芯片的多个内部电路电连接到所述封装基板；多个第二芯片焊盘，设置在所述第二表面上，并且位于所述第二半导体芯片和所述第二表面之间；多个再分布线，位于所述第二表面上，所述再分布线电连接到所述第二半导体芯片；以及多个接合线，将所述再分布线电连接到所述封装基板。
根据一些示例性实施例，半导体器件可以包括：封装基板；位于封装基板上的第一半导体芯片；以及第二半导体芯片，设置在所述第一半导体芯片上并与所述第一半导体芯片电连接。第一半导体芯片包括：芯片基板，包括第一表面和与所述第一表面相对的第二表面；集成电路区，包括与所述芯片基板的所述第一表面相邻的多个内部电路；多个第一芯片焊盘，位于所述芯片基板的所述第一表面处，所述第一芯片焊盘电连接到所述内部电路；以及多个再分布线，位于所述芯片基板的所述第二表面上，所述再分布线通过连接构件电连接到所述封装基板。再分布线可以与集成电路区间隔开。
附图说明
图1示出了图示根据本发明构思的示例性实施例的半导体封装的平面图。
图2A示出了沿图1的线I-I’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。
图2B示出了图示图2A的部分A的放大图。
图3示出了沿图1的线I-I’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。
图4示出了图示根据本发明构思的示例性实施例的半导体封装的平面图。
图5示出了沿图4的线II-II’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。
图6示出了沿图4的线II-II’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。
图7示出了图示根据本发明构思的示例性实施例的半导体封装的平面图。
图8示出了沿图7的线III-III’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。
图9A至图9H示出了图示根据本发明构思的示例性实施例的制造半导体封装的方法的横截面图。
具体实施方式
如本文所使用的，被描述为“电连接”的项目被配置为使得电信号可以从一个项目传递到另一个项目。因此，物理连接到无源电绝缘组件(例如，印刷电路板的预浸料层、连接两个器件的电绝缘粘合剂、电绝缘的底部填充物或模具层等)的无源导电组件(例如，导线、焊盘、内部电线等)不与该组件电连接。此外，彼此“直接连接”的项目可以通过一个或多个导体(例如，导线、焊盘、内部电线、通孔等)连接，并且可以形成相同的电节点。因此，直接连接的组件不包括通过有源元件(例如，晶体管或二极管)连接(尽管这种连接可以形成电连接)的组件。直接连接的元件可以直接物理连接(例如，彼此接触)。
图1示出了图示根据本发明构思的示例性实施例的半导体封装的平面图。图2A示出了沿图1的线I-I’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。图2B示出了图示图2A的部分A的放大图。
参考图1、图2A和图2B，半导体封装1000可以包括：封装基板100、第一半导体芯片200、第二半导体芯片300a、第三半导体芯片300b以及模制层400。
第一半导体芯片200可以设置在封装基板100上。封装基板100可以是或者包括例如印刷电路板(PCB)。封装基板100可以包括第一焊盘101和第二焊盘103。第一焊盘101和第二焊盘103可以设置在封装基板100的顶表面上。第一焊盘101可以沿第一方向和与第一方向交叉的第二方向彼此间隔开。第二焊盘103可以沿着封装基板100的边缘彼此间隔开。外部端子105可以设置在封装基板100的底表面上，封装基板100的底表面与封装基板100的顶表面相对。外部端子105可以附接到封装基板100的底表面上。外部端子105可以将封装基板100电连接至外部装置。外部端子105可以包括例如焊料凸点或焊料球。
第一半导体芯片200可以包括基板(例如，芯片基板)201、集成电路区IC、第一芯片焊盘203、第二芯片焊盘205、第一绝缘层207、再分布线209和第二绝缘层211。基板201可以是或者包括例如硅基板、锗基板或硅锗基板。基板201可以具有第一表面201a和与第一表面201a相对的第二表面201b。可以通过第一表面201a比第二表面201b更靠近封装基板100的方式来配置基板201。
集成电路区IC可以设置在基板201中，并且设置在基板201的第一表面201a上。集成电路区IC可以包括多个内部电路。在一些示例中，内部电路可以包括：设置在基板201中且设置在基板201的第一表面201a上的晶体管TR、接触通孔CV、顺序堆叠在基板201的第一表面201a上的多个层间介电层10、设置在层间介电层10中的金属线M、以及穿透层间介电层10并且电连接设置在不同层间介电层10中的金属线M的通孔V。在一些示例中，内部电路可以包括驱动器电路、接收器电路、收发器电路、控制电路、电源电路等中的至少一个。接触通孔CV可以将至少一个晶体管TR(例如，其源极/漏极区域)电连接到金属线M。晶体管TR可以是控制电路和/或电源电路的组成部分。在一些实施例中，第一半导体芯片200可以是半导体逻辑芯片。
第一芯片焊盘203可以设置在基板201的第一表面201a上。例如，第一芯片焊盘203可以设置在相对于基板201的第一表面201a的顶层处的层间介电层10上。第一芯片焊盘203可以沿第一方向和与第一方向交叉的第二方向彼此间隔开。第一芯片焊盘203可以与集成电路区IC中的内部电路接触。例如，第一芯片焊盘203可以电连接到晶体管TR。例如，第一芯片焊盘203中的每一个可以通过通孔V、金属线M和接触通孔CV电连接到至少一个晶体管TR。
第二芯片焊盘205可以设置在基板201的第二表面201b上。在一些示例中，第二芯片焊盘205可以设置在再分布线209的一部分上，并且可以接触再分布线209的所述部分。第二芯片焊盘205可以沿第一方向和与第一方向交叉的第二方向彼此间隔开。在第一半导体芯片200中，第二芯片焊盘205可以与集成电路区IC间隔开。例如，在第一半导体芯片200中，第二芯片焊盘205可以不电连接到集成电路区IC的晶体管TR。
第一绝缘层207可以设置在基板201的第二表面201b上。第一绝缘层207可以覆盖基板201的第二表面201b，并且暴露第二芯片焊盘205的顶表面。在一些示例中，第一绝缘层207可以覆盖基板201的第二表面201b，并且暴露再分布线209的顶表面。第一绝缘层207可以包括单个层或多个层。第一绝缘层207可以包括例如氧化硅层、氮化硅层和氮氧化硅层中的一个或多个。
再分布线209可以设置在基板201的第二表面201b上。再分布线209可以彼此间隔开。再分布线209可以部分地覆盖第一绝缘层207的顶表面。再分布线209可以对应地电连接到第二芯片焊盘205。例如，再分布线209可以以一一对应地接触并电连接到第二芯片焊盘205。在基板201的第二表面201b上，再分布线209可以具有从第二芯片焊盘205朝向基板201的侧表面延伸的线性形状。在基板201的第二表面201b上，再分布线209中的每一个可以一端与第二芯片焊盘205接触，另一端与基板201的侧表面相邻。例如，再分布线209的另一端可以与第二芯片焊盘205间隔开，并且位于基板201的边缘上。再分布线209可以各自包括单个金属层或多个金属层。再分布线209可以包括例如铝(Al)、镍(Ni)和钴(Co)的中的一种或多种。
在第一半导体芯片200中，再分布线209可以与集成电路区IC间隔开。例如，在第一半导体芯片200中，再分布线209可以不电连接到集成电路区IC的晶体管TR。图1示例性地示出了再分布线209的数量和布置，但是本发明构思不限于所示出的情况。
在一些实施例中，第一半导体芯片200的有源表面可以包括第一芯片焊盘203中的每一个的一个表面，并且第一半导体芯片200的无源表面可以包括第二芯片焊盘205中的每一个的一个表面和再分布线209中的每一个的一个表面。例如，第一半导体芯片200的有源表面可以表示其上设置有与集成电路区IC的内部电路电连接的第一芯片焊盘203的第一表面，并且第一半导体芯片200的无源表面可以表示其上设置有与集成电路区IC的内部电路电连接的第二芯片焊盘205的与第一表面相对的第二表面。例如，第一芯片焊盘203可以被形成为与集成电路区IC的内部电路相邻，并且第二芯片焊盘205可以被形成为与集成电路区IC的内部电路间隔开。
第二绝缘层211可以设置在再分布线209和第一绝缘层207上。第二绝缘层211可以部分地暴露再分布线209。例如，第二绝缘层211可以暴露再分布线209的一端，所述一端与第二芯片焊盘205接触。在一些示例中，第二绝缘层211可以暴露再分布线209的所述另一端，所述另一端被设置为与基板201的侧表面相邻。第二绝缘层211可以包括单个层或多个层。第二绝缘层211可以包括例如氧化硅层、氮化硅层或氮氧化硅层。
接合线230可以设置在再分布线209的所述另一端和封装基板100的第二焊盘103之间，从而将再分布线209电连接到第二焊盘103。例如，封装基板100和第一半导体芯片200可以不通过接合线230彼此电连接。接合线230可以包括例如金(Au)。
封装基板100和第一半导体芯片200之间可以设置有端子(或连接构件)240。例如，端子240可以设置在第一芯片焊盘203和第一焊盘101之间。端子240可以与第一芯片焊盘203接触。端子240可以电连接到集成电路区IC的内部电路(例如，晶体管TR)。例如，端子240可以将第一半导体芯片200电连接到封装基板100。
第二半导体芯片300a和第三半导体芯片300b可以设置在第一半导体芯片200上。例如，第二半导体芯片300a和第三半导体芯片300b可以设置在基板201的第二表面201b上。第二半导体芯片300a和第三半导体芯片300b可以彼此水平间隔开。第二半导体芯片300a和第三半导体芯片300b中的每一个可以与第二芯片焊盘205竖直地重叠。第二半导体芯片300a和第三半导体芯片300b中的每一个可以包括一个表面301和与所述一个表面301相对的另一表面302。第二半导体芯片300a和第三半导体芯片300b中的每一个的所述一个表面301可以比所述另一表面302更靠近第一半导体芯片200。在一些实施例中，第二半导体芯片300a和第三半导体芯片300b可以是半导体存储器芯片。
连接构件(或端子)310可以设置在第一半导体芯片200与第二半导体芯片300a和第三半导体芯片300b中的每一个之间。例如，连接构件310可以设置在第二芯片焊盘205和第二半导体芯片300a和第三半导体芯片300b中的每一个的所述一个表面301之间。每个连接构件310可以接触再分布线209的所述一端。在一些示例中，连接构件310可以接触第二芯片焊盘205。连接构件310可以是例如是焊料凸点或焊料球。
在一些实施例中，第二半导体芯片300a和第三半导体芯片300b可以通过连接构件310、再分布线209和接合线230电连接到封装基板100。在一些示例中，第二半导体芯片300a和第三半导体芯片300b可以通过连接构件310、第二芯片焊盘205、再分布线209和接合线230电连接到封装基板100。在一些实施例中，第二半导体芯片300a和第三半导体芯片300b可以通过连接构件310、再分布线209、接合线230和封装基板100电连接到第一半导体芯片200的晶体管TR。在一些实施例中，第二半导体芯片300a和第三半导体芯片300b可以通过连接构件310、第二芯片焊盘205、再分布线209、接合线230和封装基板100电连接到第一半导体芯片200的晶体管TR。在这样的配置中，设置在第一半导体芯片200上的晶体管TR可以驱动第二半导体芯片300a和第三半导体芯片300b中包括的内部电路。
根据本发明构思的一些实施例，第一半导体芯片200可以通过连接构件310、再分布线209和接合线230(并且可选地，可以包括第二芯片焊盘205)电连接到第二半导体芯片300a和第三半导体芯片300b，而无需在第一半导体芯片200和第二半导体芯片300a和第三半导体芯片300b中的每一个之间设置任何其它结构。因此，可以在第一半导体芯片200和第二半导体芯片300a之间以及在第一半导体芯片200和第三半导体芯片300b之间实现最小传输距离。此外，第一半导体芯片200可以容易地辐射由其产生的热。
模制层400可以设置在封装基板100上。模制层400可以覆盖接合线230以及第一半导体芯片200、第二半导体芯片300a和第三半导体芯片300b，并且可以设置在封装基板100和第一半导体芯片200之间的空间中、第一半导体芯片200和第二半导体芯片300a之间的空间中以及第一半导体芯片200和第三半导体芯片300b之间的空间中。例如，模制层400可以包括绝缘聚合材料(例如，环氧树脂模制塑料)。
图3示出了沿图1的线I-I’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。在下面的实施例中，出于简洁描述的目的，省略与以上参考图1、图2A和图2B讨论的技术特征重复的技术特征。
参考图3，半导体封装2000可以包括封装基板100、第一半导体芯片200、第二半导体芯片300a、第三半导体芯片300b、多个第四半导体芯片600、以及模制层400。第二半导体芯片300a和第三半导体芯片300b中的每一个可以包括通孔320。通孔320可以设置在第二半导体芯片300a和第三半导体芯片300b内。多个第四半导体芯片600可以竖直堆叠在第二半导体芯片300a和第三半导体芯片300b中的每一个上。其它通孔320可以包括在第四半导体芯片600中，但不包括在顶部的第四半导体芯片600中。通孔320可以设置在第四半导体芯片600内。在一些实施例中，多个第四半导体芯片600可以是半导体存储器芯片。
焊料球330可以设置在第二半导体芯片300a与覆于其上的第四半导体芯片600之间的空间中、第三半导体芯片300b与覆于其上的第四半导体芯片600之间的空间中以及竖直相邻的第四半导体芯片600之间的空间中。第二半导体芯片300a和第四半导体芯片600(其中芯片300a和芯片600彼此竖直地重叠)可以通过焊料球330和通孔320彼此电连接，并且第三半导体芯片300b和第四半导体芯片600(其中芯片300b和芯片600彼此竖直地重叠)可以通过焊料求330和通孔320彼此电连接。
图4示出了图示根据本发明构思的示例性实施例的半导体封装3000的平面图。图5示出了沿图4的线II-II’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装。在下面的实施例中，出于简洁描述的目的，省略与以上参考图1、图2A和图2B讨论的技术特征重复的技术特征。此外，为了简化图示，图4省略了图1中所示的第二芯片焊盘205。
参考图4和图5，粘合剂层340可以插入在第一半导体芯片200与第二半导体芯片300a和第三半导体芯片300b中的每一个之间。第二半导体芯片300a和第三半导体芯片300b可以通过粘合剂层340粘附到第一半导体芯片200上。粘合剂层340可以与第二半导体芯片300a和第三半导体芯片300b中的每一个的一个表面301、再分布线209的一端以及第二绝缘层211的一部分接触。在一些示例中，粘合剂层340可以与第二半导体芯片300a和第三半导体芯片300b中的每一个的一个表面301、第二芯片焊盘205、以及第二绝缘层211的一部分接触。粘合剂层340可以是例如环氧树脂、硅基绝缘层或带。
第二半导体芯片300a和第三半导体芯片300b中的每一个可以包括第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306。第二半导体芯片300a的第一侧表面303可以与第三半导体芯片300b相邻，并且第三半导体芯片300b的第一侧表面303可以与第二半导体芯片300a相邻。例如，第二半导体芯片300a和第三半导体芯片300b的第一侧表面303可以彼此相邻并且彼此面对。
第三芯片焊盘350可以设置在第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面302上。第三芯片焊盘350可以设置在第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面(例如，有源表面)302上。例如，第二半导体芯片300a和第三半导体芯片300b中的每一个的有源表面302可以电连接到第二半导体芯片300a和第三半导体芯片300b中的每一个的内部电路。相反，第二半导体芯片300a和第三半导体芯片300b中的每一个可以包括所述一个表面，例如，其上没有设置内部电路的无源表面301。当在平面图中观察时，在第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面302上，第三芯片焊盘350可以沿着第二侧表面304、第三侧表面305和第四侧表面306布置。在第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面302上，第三芯片焊盘350可以不沿第一侧表面303布置。例如，在第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面302上，除了第一侧表面303之外，第三芯片焊盘350可以与第二侧表面304、第三侧表面305和第四侧表面306相邻。虽然图5示例性地示出了沿第二侧表面304、第三侧表面305和第四侧表面306布置的第三芯片焊盘350，但是本发明构思不限于所示出的。例如，第三芯片焊盘350可以沿第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306布置。
连接构件310可以设置在再分布线209的所述另一端与第二半导体芯片300a和第三半导体芯片300b中的每一个的所述另一表面302之间。当在平面图中观察时，连接构件310可以设置在第三芯片焊盘350和再分布线209的所述另一端之间，同时跨越第二半导体芯片300a和第三半导体芯片300b中的每一个的第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306中的至少一个。连接构件310可以与第三芯片焊盘350和再分布线209的所述另一端接触。连接构件310可以是例如接合线。
在一些实施例中，在第二半导体芯片300a和第三半导体芯片300b以狭窄空间彼此间隔开的情况下，当在平面图中观察时，连接构件310可以既不跨越第二半导体芯片300a和第三半导体芯片300b中的每一个的第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306全部，也不压在这些侧表面上。
例如，当在平面图中观察时，连接构件310可以将第三芯片焊盘350连接到再分布线209的所述另一端，同时跨越第二半导体芯片300a的第二侧表面304、第三侧表面305和第四侧表面306。当在平面图中观察时，连接构件310可以不跨越第二半导体芯片300a的第一侧表面303。例如，当在平面图中观察时，连接构件310可以将第三芯片焊盘350连接到再分布线209的所述另一端，同时跨越第三半导体芯片300b的第二侧表面304、第三侧表面305和第四侧表面306。当在平面图中观察时，连接构件310可以不跨越第三半导体芯片300b的第一侧表面303。
图6示出了沿图4的线II-II’截取的横截面图，其图示了根据本发明构思的示例性实施例的包括多个第四半导体芯片600在内的半导体封装4000。在下面的实施例中，出于简洁描述的目的，省略与以上参考图4和图5讨论的技术特征重复的技术特征。
参考图6，第二绝缘层211可以设置在再分布线209和第一绝缘层207上。在一些示例中，第二绝缘层211可以设置在再分布线209、第二芯片焊盘205和第一绝缘层207上。例如，第二绝缘层211可以覆盖第二芯片焊盘205、第一绝缘层207和再分布线209的一部分。第二绝缘层211可以部分地暴露再分布线209的另一端。
粘合剂层340可以插入在第一半导体芯片200与第二半导体芯片300a和第三半导体芯片300b中的每一个之间。第二半导体芯片300a和第三半导体芯片300b可以通过粘合剂层340粘附到第一半导体芯片200上。粘合剂层340可以与第二绝缘层211以及第二半导体芯片300a和第三半导体芯片300b中的每一个的一个表面301接触。
连接构件310可以设置在再分布线209的所述另一端与第二半导体芯片300a和第三半导体芯片300b中的每一个的另一表面302之间，并且将所述另一端与所述另一表面302电连接。
多个第四半导体芯片600可以竖直堆叠在第二半导体芯片300a和第三半导体芯片300b中的每一个上。竖直堆叠的第四半导体芯片600可以通过至少一个粘合剂层340彼此粘附。可以提供粘合剂层340以将多个第四半导体芯片600中的一个或多个芯片600附接到其下面的第二半导体芯片300a上，并且可以提供粘合剂层340以将多个第四半导体芯片600中的一个或多个芯片600附接到其下面的第三半导体芯片300b上。
堆叠在第二半导体芯片300a上的第四半导体芯片600可以顺序地偏移，以暴露分别设置在第二半导体芯片300a和第四半导体芯片600的顶表面上的第三芯片焊盘350和第四芯片焊盘360。例如，堆叠在第二半导体芯片300a上的第四半导体芯片600可以顺序地朝向堆叠在第三半导体芯片300b上的第四半导体芯片600偏移。堆叠在第三半导体芯片300b上的第四半导体芯片600可以顺序地偏移，以暴露分别设置在第三半导体芯片300b和第四半导体芯片600的顶表面上的第三芯片焊盘350和第四芯片焊盘360。例如，堆叠在第三半导体芯片300b上的第四半导体芯片600可以顺序地朝向堆叠在第二半导体芯片300a上的第四半导体芯片600偏移。
第一接合线370可以将彼此竖直相邻的第三芯片焊盘350和第四芯片焊盘360电连接，并且还将彼此竖直相邻的第四芯片焊盘360电连接。
图7示出了图示根据本发明构思的示例性实施例的半导体封装5000的平面图。图8示出了沿图7的线III-III’截取的横截面图，其图示了根据本发明构思的示例性实施例的半导体封装5000。在下面的实施例中，出于简洁描述的目的，省略与以上参考图4和图5讨论的技术特征重复的技术特征。此外，为了简化图示，图7省略了图1中所示的第二芯片焊盘205。
参考图7和图8，半导体封装5000可以包括：封装基板100、第一半导体芯片200、第二半导体芯片300以及模制层400。第二半导体芯片300可以设置在第一半导体芯片200上。粘合剂层340可以插入在第一半导体芯片200和第二半导体芯片300之间，因此可以将第二半导体芯片300附接到第一半导体芯片200上。在一些实施例中，第二半导体芯片300可以是半导体存储器芯片。
第三芯片焊盘350可以设置在第二半导体芯片300的另一表面302(例如，有源表面)上。在第二半导体芯片300的另一表面302上，第三芯片焊盘350可以沿着第二半导体芯片300的侧表面布置。例如，在第二半导体芯片300的另一表面302上，第三芯片焊盘350可以沿着第二半导体芯片300的第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306布置。
连接构件310可以设置在第二半导体芯片300的另一表面302和再分布线209的所述另一端之间。连接构件310可以与第三芯片焊盘350和再分布线209的所述另一端接触。连接构件310可以是例如接合线。当在平面图中观察时，连接构件310可以将第三芯片焊盘350连接到再分布线209的所述另一端，同时跨越第二半导体芯片300的第一侧表面303、第二侧表面304、第三侧表面305和第四侧表面306。
图9A至图9H示出了图示根据本发明构思的示例性实施例的制造半导体封装的方法的横截面图。
参考图9A，基板201可以被设置为包括集成电路区IC。基板201可以是例如裸晶片。基板201可以是例如硅基板、锗基板或硅锗基板。基板201可以具有彼此相对的第一表面201a和第二表面201b。基板201可以包括沿第一方向和与第一方向交叉的第二方向彼此间隔开的器件区DR，并且还包括限定器件区DR的划线区(scribe region)SR。基板201的器件区DR可以是其中形成半导体芯片的区域。
将图9A与图2B一起参考，集成电路区IC可以形成在基板201的每个器件区DR中。集成电路区IC可以形成在基板201中，且形成在基板201的第一表面201a上。集成电路区IC可以包括晶体管TR、多个层间介电层10、金属线M、接触通孔CV和通孔VI。晶体管TR可以设置在基板201中，并且设置在基板201的第一表面201a上。例如，晶体管TR可以是控制电路、驱动器电路、接收器电路、收发器电路和/或电源电路的组成部分。多个层间介电层10可以顺序地形成在基本201的第一表面201a上。金属线M可以形成在多个层间介电层10上和它们之间。通孔V可以形成在多个层间介电层10之间，并且可以将形成在不同层间介电层10上的金属线M电连接。接触通孔CV可以将至少一个晶体管TR(例如，其源极/漏极区域)电连接到金属线M。
第一芯片焊盘203可以形成在基板201的器件区DR中。第一芯片焊盘203可以形成在基板201的第一表面201a(即，有源表面)上。例如，第一芯片焊盘203可以形成在集成电路区IC上的顶部的层间介电层10上。第一芯片焊盘203可以被形成为沿第一方向和与第一方向交叉的第二方向彼此间隔开。端子240可以形成在第一芯片焊盘203上。
返回参考图9A，端子240可以电连接到第一芯片焊盘203。端子240可以包括例如铜(Cu)、银(Ag)、铂(Pt)、铝(Al)和铜(Cu)中的一种或多种。端子240可以通过溅射工艺、诸如脉冲电镀或直流电镀之类的电镀工艺、焊接工艺或附接工艺来形成。
支撑件500可以设置在基板201的第一表面201a上。支撑件500可以覆盖第一芯片焊盘203和端子240。支撑件500可以是用于处理基板201的晶片支撑系统。支撑件500可以包括粘合剂材料，例如，环氧树脂、硅基绝缘层或带。
参考图9B，第二芯片焊盘205可以形成在基板201的器件区DR中。第二芯片焊盘205可以形成在基板201的第二表面201b(即，无源表面)上。第二芯片焊盘205可以被形成为沿第一方向和与第一方向交叉的第二方向彼此间隔开。
第一绝缘层207可以形成在基板201的第二表面201b上。可以通过形成覆盖第二芯片焊盘205和基板201的第二表面201b的绝缘层(未示出)并对其进行图案化来形成第一绝缘层207。当图案化绝缘层时，第二芯片焊盘205的顶表面可以通过第一绝缘层207暴露。第一绝缘层207可以由单个层或多个层形成。第一绝缘层207可以包括例如氧化硅层、氮化硅层和氮氧化硅层中的一个或多个。
参考图9C，金属层510可以形成在基板201的第二表面201b上。金属层510可以被形成为覆盖第二芯片焊盘205的顶表面和第一绝缘层207的顶表面。金属层510可以由单个层或多个层形成。金属层510可以包括例如铝(Al)、镍(Ni)和钴(Co)的中的一种或多种。
光刻胶图案PR可以形成在金属层510上。光刻胶图案PR可以部分地暴露金属层510。光刻胶图案PR的形状可以与以上参考图1和图2A讨论的再分布线209的形状相同。
参考图9D，光刻胶图案PR可以用作蚀刻掩模以部分地蚀刻金属层510，这可以使得形成再分布线209。可以部分地蚀刻金属层510以暴露第一绝缘层207的顶表面的一部分。例如，可以采用干法或湿法刻蚀工艺来作为刻蚀工艺。再分布线209可以形成在基板201的器件区DR中。如图1中所示，再分布线209可以被形成为与第二芯片焊盘205相对应。在基板201的第二表面201b上，再分布线209可以具有从第二芯片焊盘205朝向基板201的划线区SR延伸的线性形状。再分布线209可以具有分别与第二芯片焊盘205的顶表面接触的一端。在基板201的第二表面201b上，再分布线209可以具有与基板201的划线区SR相邻的另一端。在蚀刻工艺之后，可以去除光刻胶图案PR。
参考图9E，第二绝缘层211可以形成在基板201的第二表面201b上。第二绝缘层211可以被形成为覆盖再分布线209和第一绝缘层207的通过再分布线209暴露的顶表面。第二绝缘层211可以由单个层或多个层形成。第二绝缘层211可以包括例如氧化硅层、氮化硅层和氮氧化硅层中的一个或多个。
参考图9F，可以对第二绝缘层211执行蚀刻工艺，从而暴露再分布线209的所述一端和所述另一端。例如，可以在第二绝缘层211上形成蚀刻掩模图案(未示出)，并且可以在第二绝缘层211中的通过蚀刻掩模图案暴露的部分上蚀刻第二绝缘层211。除了再分布线209的所述一端和所述另一端之外，第二绝缘层211可以覆盖再分布线209的其余部分。
参考图9G，可以沿着基板201的划线区SR执行切割工艺。切割工艺可以顺序地切割形成在基板201的划线区SR上的第二绝缘层211、第一绝缘层207和支撑件500。因此，可以形成多个第一半导体芯片200。第一半导体芯片200中的每一个可以包括基板201、集成电路区IC、第一芯片焊盘203、第二芯片焊盘205、第一绝缘层207、再分布线209和第二绝缘层211。在一些实施例中，第一半导体芯片200可以是半导体逻辑芯片。
在切割工艺之后，可以对覆盖端子240和第一芯片焊盘203的支撑件500执行去除工艺。备选地，可以在切割工艺之前去除支撑件500。
在示例实施例中，可以在形成第二芯片焊盘205之前形成再分布线209。例如，第二芯片焊盘205可以设置在再分布线209的第一端(例如，所述一端)上。在这种情况下，参考图9E，第二绝缘层211可以被形成为覆盖再分布线209的一些部分、第二芯片焊盘205和第一绝缘层207的通过再分布线209暴露的顶表面，并且参考图9F，可以对第二绝缘层211执行蚀刻工艺，从而暴露再分布线209的第二端(例如，所述另一端)。例如，可以在第二绝缘层211上形成蚀刻掩模图案(未示出)，并且可以在第二绝缘层211中的通过蚀刻掩模图案暴露的部分上蚀刻第二绝缘层211。第二绝缘层211可以覆盖第二芯片焊盘205和再分布线209中的除了再分布线209的第二端之外的其余部分。
参考图9H，可以制备封装基板100。封装基板100可以是例如印刷电路板(PCB)。封装基板100可以包括第一焊盘101和第二焊盘103。第一焊盘101和第二焊盘103可以设置在封装基板100的顶表面上。
外部端子105可以形成在封装基板100的底表面上。外部端子105可以包括焊料球或焊料凸块。外部端子105的形成顺序不限于上面所提及的。
第一半导体芯片200可以堆叠在封装基板100上。端子240可以被设置为与第一焊盘101相对应。第一半导体芯片200可以以倒装芯片接合方式安装在封装基板100上。
第二半导体芯片300a和第三半导体芯片300b可以堆叠在第一半导体芯片200上。形成在第二半导体芯片300a和第三半导体芯片300b中的每一个的一个表面301上的连接构件310可以被设置为与再分布线209的所述一端和第二芯片焊盘205的顶表面相对应。第二半导体芯片300a和第三半导体芯片300b可以以倒装芯片接合方式安装在第一半导体芯片200上。在这种情况下，连接构件310可以包括例如焊料凸块或焊料球。备选地，如图4和图5所示，第二半导体芯片300a和第三半导体芯片300b可以以导线接合方式安装在第一半导体芯片200上。在这种情况下，连接构件310可以包括例如接合线。在一些实施例中，第二半导体芯片300a和第三半导体芯片300b可以是半导体存储器芯片。
接合线230可以形成在封装基板100和基板201的第二表面201b之间。例如，接合线230可以被形成为从再分布线209的所述另一端延伸到封装基板100的第二焊盘103上。接合线230可以包括例如金(Au)。
参考图2A，模制层400可以形成在封装基板100上。模制层400可以覆盖第一半导体芯片200、第二半导体芯片300a、第三半导体芯片300b和接合线230，并且可以填充封装基板100和第一半导体芯片200之间的空间、第一半导体芯片200和第二半导体芯片300a之间的空间、以及第一半导体芯片200和第三半导体芯片300b之间的空间。模制层400可以包括例如绝缘聚合材料(例如，环氧树脂模塑料)。
根据一些示例性实施例，顺序堆叠在封装基板上的第一半导体芯片和第二半导体芯片可以通过将第一半导体芯片和第二半导体芯片彼此电连接的连接构件、通过与连接构件接触且设置在第一半导体芯片中的与第二半导体芯片相连的一个表面(即，无源表面)上的再分布线以及通过在再分布线和封装基板之间的接合线来彼此电连接，而无需在第一半导体芯片和第二半导体芯片之间设置任何其它附加结构。因此，可以最小化或减小第一半导体芯片和第二半导体芯片之间的传输距离，并且可以容易地辐射在第一半导体芯片中产生的热。
尽管已经结合附图中示出的本发明构思的实施例描述了本发明，但是本领域技术人员将理解的是，可以在不脱离本发明构思的技术精神和基本特征的情况下进行各种改变和修改。对于本领域技术人员来说显而易见的是，在不脱离本发明构思的范围和精神的情况下可以对其进行各种替换、修改和改变。因此，所有这种修改旨在被包括在如在权利要求中限定的本发明的范围内。

Claims (20)

1.一种半导体封装，包括：
封装基板；
第一半导体芯片，位于所述封装基板上；以及
第二半导体芯片，位于所述第一半导体芯片上，
其中，所述第一半导体芯片包括：
芯片基板，包括第一表面和与所述第一表面相对的第二表面；
多个第一芯片焊盘，位于所述封装基板和所述芯片基板的所述第一表面之间并且将所述第一半导体芯片电连接到所述封装基板；
多个第二芯片焊盘，设置在所述芯片基板的所述第二表面上，并且位于所述第二半导体芯片和所述芯片基板的所述第二表面之间；
多个再分布线，位于所述芯片基板的所述第二表面上，所述再分布线电连接到所述第二半导体芯片；以及
多个第一接合线，将所述多个再分布线电连接到所述封装基板。
2.根据权利要求1所述的半导体封装，其中，所述多个第二芯片焊盘与所述第二半导体芯片竖直地重叠，以及
其中，所述多个再分布线对应地连接到所述多个第二芯片焊盘。
3.根据权利要求2所述的半导体封装，其中，所述第二半导体芯片包括与所述第一半导体芯片相邻的第一表面和与所述第二半导体芯片的所述第一表面相对的第二表面，以及
其中，所述多个再分布线通过设置在所述多个第二芯片焊盘和所述第二半导体芯片的所述第一表面之间的多个连接构件电连接到所述第二半导体芯片。
4.根据权利要求2所述的半导体封装，其中：
所述再分布线从所述第二芯片焊盘向所述芯片基板的侧表面延伸，
所述再分布线的第一端与所述第二芯片焊盘接触，以及
在所述芯片基板的所述第二表面上，所述再分布线的与所述第一端相对的第二端与所述芯片基板的所述侧表面相邻。
5.根据权利要求4所述的半导体封装，其中，所述第二半导体芯片包括与所述第一半导体芯片相邻的第一表面和与所述第二半导体芯片的所述第一表面相对的第二表面，以及
其中，所述多个再分布线通过设置在所述第二半导体芯片的所述第二表面和所述多个再分布线的所述第二端之间的多个连接构件电连接到所述第二半导体芯片。
6.根据权利要求1所述的半导体封装，其中，所述第二半导体芯片包括穿透所述第二半导体芯片的通孔，以及
其中，所述半导体封装还包括：
第三半导体芯片，位于所述第二半导体芯片上，所述第三半导体芯片通过所述通孔电连接到所述第二半导体芯片；以及
焊料球，位于所述第二半导体芯片和所述第三半导体芯片之间，所述焊料球电连接到所述通孔。
7.根据权利要求1所述的半导体封装，还包括：
第三半导体芯片，位于所述第二半导体芯片上；以及
多个第二接合线，将所述第二半导体芯片电连接到所述第三半导体芯片。
8.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片还包括与所述芯片基板的所述第一表面相邻的集成电路区，
其中，包括在所述集成电路区中的内部电路电连接到所述多个第一芯片焊盘中的对应第一芯片焊盘，以及
其中，所述再分布线与所述集成电路区间隔开。
9.根据权利要求1所述的半导体封装，还包括：多个端子，设置在所述封装基板和所述芯片基板的所述第一表面之间，并且通过所述多个第一芯片焊盘将所述第一半导体芯片电连接到所述封装基板。
10.根据权利要求1所述的半导体封装，其中，所述再分布线通过包括焊料球、焊料凸块或接合线在内的连接构件电连接到所述第二半导体芯片。
11.一种半导体封装，包括：
封装基板；
第一半导体芯片，位于所述封装基板上；以及
第二半导体芯片，位于所述第一半导体芯片上，
其中，所述第一半导体芯片包括：
芯片基板，包括第一表面和与所述第一表面相对的第二表面；
多个第一芯片焊盘，位于所述封装基板和所述芯片基板的所述第一表面之间，并且所述多个第一芯片焊盘将所述第一半导体芯片的多个内部电路电连接到所述封装基板；
多个第二芯片焊盘，设置在所述芯片基板的所述第二表面上，并且位于所述第二半导体芯片和所述芯片基板的所述第二表面之间；
多个再分布线，位于所述芯片基板的所述第二表面上，所述再分布线电连接到所述第二半导体芯片；以及
多个接合线，将所述多个再分布线电连接到所述封装基板。
12.根据权利要求11所述的半导体封装，还包括：多个端子，设置在所述封装基板和所述芯片基板的所述第一表面之间，并且将所述第一半导体芯片的所述多个第一芯片焊盘电连接到所述封装基板。
13.根据权利要求12所述的半导体封装，其中，所述内部电路包括在集成电路区的与所述芯片基板的所述第一表面相邻的部分中，以及
其中，所述多个端子与所述第一半导体芯片的内部电路接触。
14.根据权利要求11所述的半导体封装，其中，位于所述芯片基板的所述第二表面上的所述多个第二芯片焊盘与所述第二半导体芯片竖直地重叠，以及
其中，所述多个再分布线对应地连接到所述多个第二芯片焊盘。
15.根据权利要求14所述的半导体封装，其中，所述第二半导体芯片包括与所述第一半导体芯片相邻的第一表面和与所述第一表面相对的第二表面，
其中，所述多个再分布线通过多个连接构件电连接到所述第二半导体芯片，
其中，所述连接构件设置在所述第二芯片焊盘和所述第二半导体芯片的所述第一表面之间，以及
其中，所述连接构件包括焊料球或焊料凸块。
16.根据权利要求14所述的半导体封装，其中：
所述再分布线从所述第二芯片焊盘向所述芯片基板的侧表面延伸，
所述再分布线的第一端与所述第二芯片焊盘接触，以及
在所述芯片基板的所述第二表面上，所述再分布线的第二端与所述芯片基板的所述侧表面相邻。
17.根据权利要求16所述的半导体封装，其中，所述第二半导体芯片包括与所述第一半导体芯片相邻的第一表面和与所述第二半导体芯片的所述第一表面相对的第二表面，
其中，所述再分布线通过多个连接构件电连接到所述第二半导体芯片，
其中，所述连接构件设置在所述第二半导体芯片的所述第二表面和所述再分布线的所述第二端之间，以及
其中，所述连接构件包括接合线。
18.一种半导体器件，包括：
封装基板；
第一半导体芯片，位于所述封装基板上；以及
第二半导体芯片，设置在所述第一半导体芯片上并与所述第一半导体芯片电连接，
其中，所述第一半导体芯片包括：
芯片基板，包括第一表面和与所述第一表面相对的第二表面；
集成电路区，包括与所述芯片基板的所述第一表面相邻的多个内部电路；
多个第一芯片焊盘，位于所述芯片基板的所述第一表面处，所述多个第一芯片焊盘电连接到所述内部电路；以及
多个再分布线，位于所述芯片基板的所述第二表面上，所述多个再分布线通过多个连接构件电连接到所述封装基板，
其中，所述再分布线与所述集成电路区间隔开。
19.根据权利要求18所述的半导体器件，其中，所述多个再分布线包括与位于所述芯片基板的所述第二表面处的第二芯片焊盘接触的第一端以及与所述第一端相对的第二端，并且所述多个再分布线的所述第二端与所述芯片基板的侧表面相邻。
20.根据权利要求19所述的半导体器件，其中，所述第二半导体芯片包括与所述第一半导体芯片相邻的第一表面和与所述第二半导体芯片的所述第一表面相对的第二表面，
其中，所述多个再分布线通过多个连接构件电连接到所述第二半导体芯片，以及
其中，所述连接构件设置在所述第二芯片焊盘和所述第二半导体芯片的所述第一表面之间，或者
其中，所述连接构件设置在所述第二半导体芯片的所述第二表面和所述再分布线的所述第二端之间。
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