CN110690192A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN110690192A
CN110690192A CN201910603873.4A CN201910603873A CN110690192A CN 110690192 A CN110690192 A CN 110690192A CN 201910603873 A CN201910603873 A CN 201910603873A CN 110690192 A CN110690192 A CN 110690192A
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Prior art keywords
insulating layer
semiconductor substrate
sidewall
semiconductor device
semiconductor
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CN201910603873.4A
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English (en)
Inventor
李周益
金东完
申硕浩
韩正勳
朴商五
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110690192A publication Critical patent/CN110690192A/zh
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Abstract

提供了一种半导体装置，所述半导体装置可以包括半导体基底和位于半导体基底上的连接基体柱。绝缘层可以位于半导体基底上，绝缘层可以包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的限定开口的侧壁包括位于比连接基体柱的最上部分低的水平处的水平台阶。

Description

半导体装置
本发明要求于2018年7月5日在韩国知识产权局提交的第10-2018-0078250号韩国专利申请的权益，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思涉及一种半导体装置，具体地，涉及一种半导体芯片以及包括该半导体芯片的半导体封装件，更具体地，涉及一种包括连接凸块的半导体芯片以及包括该半导体芯片的半导体封装件。
背景技术
为了满足小型化、多功能和高性能电子产品的要求，半导体封装件需要变薄、量轻并具有高速度和高性能。因此，对于实现具有高存储器带宽的系统的半导体芯片以及包括该半导体芯片的半导体封装件的需求正在增加。由于存储器带宽与数据传输速度和数据传输线的数量成比例，因此存储器带宽可用通过提高存储器工作速度或增加数据传输线的数量来提高。因此，会增加附着到半导体芯片的连接凸块的数量和密度。
发明内容
根据本发明构思的实施例可以提供一种包括增加的数量和密度的多个连接凸块的半导体芯片以及包括该半导体芯片的半导体封装件。依照这些实施例，半导体装置可以包括半导体基底和位于半导体基底上连接基体柱。绝缘层可以位于半导体基底上，绝缘层可以包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的限定开口的侧壁包括位于比连接基体柱的最上部分低的水平处的水平台阶。
在一些实施例中，半导体装置可以包括半导体基底。微凸块结构可以位于半导体基底上，连接基体柱可以包括在微凸块结构中，绝缘层可以位于半导体基底上，绝缘层可以包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的位于开口的第一侧上的侧壁包括下侧壁和上侧壁，其中，下侧壁相对于半导体基底以第一角度朝向连接基体柱向下倾斜，上侧壁位于下侧壁上方并相对于半导体基底以不同于第一角度的第二角度朝向连接基体柱向下倾斜。
在一些实施例中，半导体装置可以包括半导体封装主板、位于半导体封装主板上的处理器芯片、插入器、缓冲器芯片以及高带宽动态随机存取存储器芯片。插入器可以位于处理器芯片与半导体封装主板之间，其中，处理器芯片可以直接安装在插入器上。缓冲器芯片可以直接安装在与处理器芯片分隔开的插入器上，其中，所述缓冲器芯片可以包括位于缓冲器芯片上的第一连接基体柱，其中，第一连接基体柱可以具有第一纵横比，绝缘层可以位于缓冲器芯片上，其中，绝缘层包括位于绝缘层中的开口，第一连接基体柱通过开口延伸，其中，绝缘层的限定开口的侧壁可以包括水平台阶，所述水平台阶位于相对于绝缘层的从缓冲器芯片以最大距离突出的部分凹入的水平处。高带宽动态随机存取存储器芯片可以安装在缓冲器芯片上，其中，高带宽动态随机存取存储器芯片可以包括具有比第一纵横比低的第二纵横比的第二连接基体柱。
附图说明
通过下面结合附图的详细描述，将更清楚地理解发明构思的实施例，在附图中：
图1是示出根据实施例的半导体芯片的剖视图；
图2A至图2J是示出根据实施例的半导体芯片的连接凸块的放大剖视图；
图3A至图3D是示出根据实施例的半导体芯片的连接凸块的放大平面图；
图4是示出根据实施例的包括半导体芯片的半导体封装件的剖视图；
图5A和图5B是示出根据实施例的半导体封装件中包括的半导体芯片的连接凸块的放大剖视图；
图6A至图6C是示出根据实施例的半导体芯片的连接凸块的放大剖视图；
图7A至图7C是顺序地示出根据实施例的制造半导体芯片的方法的剖视图；
图8A至图8C是顺序地示出根据实施例的制造半导体芯片的方法的剖视图；
图9A至图9G是顺序地示出根据实施例的制造半导体封装件的方法的剖视图；并且
图10是示出包括根据实施例的半导体封装件的系统的剖视图。
具体实施方式
图1是示出根据实施例的半导体芯片100的剖视图。
参照图1，半导体芯片100可以包括半导体基底110以及设置在作为半导体基底110的上表面的有效表面上的连接垫(pad，也称为焊盘)120。
在本说明书中，半导体基底的上表面和下表面可以分别表示半导体基底的有效表面和无效表面。也就是说，即使当半导体基底的有效表面在最终产品中设置在无效表面下方时，半导体基底的有效表面也可以被称为半导体基底的上表面，半导体基底的无效表面也可以被称为半导体基底的下表面。此外，术语“上表面”和“下表面”可以分别应用于设置在有效表面上的元件和设置在无效表面上的元件。
半导体基底110可以包括例如硅(Si)。可选择地，半导体基底110可以包括诸如锗(Ge)的半导体元件，或者可以包括诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)或磷化铟(InP)的化合物半导体。半导体基底110可以包括有效表面以及与有效表面相对的无效表面。半导体器件可以设置在半导体芯片100中，其中，半导体器件包括各种类型的多个单独器件并且设置在有效表面上。
半导体芯片100可以是，例如，中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或者应用处理器(AP)芯片。半导体芯片100可以是，例如，动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、闪存芯片、电可擦除可编程只读存储器(EEPROM)芯片、相变随机存取存储器(PRAM)芯片、磁随机存取存储器(MRAM)芯片或电阻随机存取存储器(RRAM)芯片。
在一些实施例中，半导体芯片100可以是包括串并行转换电路的缓冲器芯片。缓冲器芯片可以设置在存储器芯片与控制器芯片之间。缓冲器芯片可以使从存储器芯片接收的数据信号串行化以将串行化的数据信号传输至控制器芯片，并且可以使从控制器芯片接收的数据信号并行化并将并行化数据信号传输至存储器芯片。
连接垫120可以包括导电材料。例如，连接垫120可以包括镍(Ni)、铝(Al)、铜(Cu)、金(Au)、银(Ag)、铂(Pt)和钨(W)中的至少一种。在图1中，连接垫120示出为掩埋在半导体基底110中，但是不限于此。在一些实施例中，连接垫120可以从半导体基底110的上表面突出。
绝缘层140可以设置在半导体基底110的上表面上。绝缘层140可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140可以包括，例如，光敏聚酰亚胺(PSPI)。绝缘层140可以包括与半导体基底110相邻的第一水平部分(图2A的140P1)和位于第一水平部分140P1上的第二水平部分(图2A的140P2)。第一水平部分140P1和第二水平部分140P2可以是绝缘层140的设置为一体的部分。第一水平部分140P1可以是在绝缘层140的下部处构成一个层的部分，第二水平部分140P2可以是在第一水平部分140P1上构成另一层的部分。下面将参照图2A至图2J详细描述绝缘层140的形状。
钝化层(图2A的130或者图2B的130a)可以设置在半导体基底110的上表面与绝缘层140之间。钝化层130或130a可以包括，例如，诸如氧化物或氮化物的无机材料。例如，钝化层130或130a可以包括氧化硅和氮化硅中的至少一种。在一些实施例中，绝缘层的第一水平部分的侧壁与钝化层两者均可以与连接垫的一部分叠置。将参照图2A和图2B详细描述钝化层130或130a。
连接凸块160可以附着到连接垫120并且可以包括导电柱156和覆盖导电柱156的上表面的导电盖158。这里，连接凸块也可以称为微凸块结构，导电柱也可以称为连接基体柱。
导电柱156可以包括，例如，Ni、Cu、钯(Pd)、Pt和Au中的至少一种。导电盖158可包括，例如，锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、Cu、Ag、Au、锌(Zn)和铅(Pb)中的至少一种。中间层可以设置在导电柱156与导电盖158之间。中间层可以包括通过导电柱156的金属材料与导电盖158的金属材料之间的反应产生的中间金属化合物。
图2A至图2J是示出根据实施例的半导体芯片的连接凸块的放大剖视图。详细地，图2A和图2B是示出图1的部分A的放大剖视图，图2C至图2J是示出与图1的部分A对应的部分的放大剖视图。在下面参照图2B至图2J给出的描述中，可以省略与参照图1和图2A给出的描述重复的描述。
参照图1和图2A，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。
连接凸块160可以包括设置在连接垫120上的导电柱156和覆盖导电柱156的上表面的导电盖158。
在一些实施例中，导电柱156可以包括基体柱152和覆盖基体柱152的上表面的覆盖柱154。基体柱152可以包括，例如，Cu。覆盖柱154可以包括，例如，Ni、Cu、Pd、Pt和Au中的至少一种。在一些实施例中，覆盖柱154可以包括Ni。在一些其他实施例中，覆盖柱154可以具有多层结构，所述多层结构包括包含Ni的第一层以及覆盖第一层并包含Cu的第二层。
导电盖158可以将半导体芯片100结合至外部装置以将半导体芯片100电连接至外部装置。导电盖158可以包括，例如，Sn、In、Bi、Sb、Cu、Ag、Au、Zn和Pb中的至少一种。
绝缘层140可以设置在半导体基底110的上表面上。绝缘层140可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140可以与连接凸块160分隔开并且可以围绕连接凸块160。钝化层130可以设置在半导体基底110的上表面与绝缘层140之间。
绝缘层140可以包括与半导体基底110相邻的第一水平部分140P1和位于第一水平部分140P1上的第二水平部分140P2。第一水平部分140P1和第二水平部分140P2可以是绝缘层140的设置为一体的部分。第一水平部分140P1可以是在绝缘层140的下部处构成一个层的部分，第二水平部分140P2可以是在第一水平部分140P1上构成另一层的部分。在图2A中，绝缘层140示出为包括构成两个层的第一水平部分140P1和第二水平部分140P2，但是不限于此。在其他实施例中，绝缘层140可以包括构成三层或更多层的三个或更多个水平部分。
第二水平部分140P2的宽度可以具有比第一水平部分140P1的宽度的值小的值。第一水平部分140P1和第二水平部分140P2可以具有位于其间的台阶高度，使得绝缘层140在从第二水平部分140P2的上表面140H2至第一水平部分140P1的上表面140H1的方向上凹入。
也就是说，绝缘层140可以包括两者之间具有台阶高度并构成不同层的第一水平部分140P1和第二水平部分140P2。
第一水平部分140P1的侧表面140S1和第二水平部分140P2的侧表面140S2可以均在与半导体基底110的上表面垂直的方向上延伸。第一水平部分140P1的侧表面140S1和钝化层130的侧表面130S可以在与半导体基底110的上表面垂直的方向上对齐。第二水平部分140P2的侧表面140S2可以将第二水平部分140P2的上表面140H2连接至第一水平部分140P1的上表面140H1。导电柱156的上表面可以在与半导体基底110的上表面垂直的方向上位于比绝缘层140的最上表面(即，第二水平部分140P2的上表面140H2)高的水平上。
第二水平部分140P2的侧表面140S2可以比第一水平部分140P1的侧表面140S1更远离连接凸块160。因此，两个第二水平部分140P2的彼此面对且具有连接凸块160位于其间的侧表面140S2之间的宽度可以比两个第一水平部分140P1的彼此面对且具有连接凸块160位于其间的侧表面140S1之间的宽度大。此外，第二水平部分140P2的侧表面140S2与导电柱156之间的最宽空间可以是第一水平部分140P1的侧表面140S1与导电柱156之间的最宽空间的大约两倍。
在根据实施例的半导体芯片100中，连接凸块160的导电柱156与绝缘层140之间的间隔可以具有随着与半导体基底110的距离增大而增大的值。因此，在将粘合层(图9C至图9G的20)与半导体芯片100分离的工艺中，防止了粘合层20的一部分残留在导电柱156与绝缘层140之间的空间中，其中，粘合层在制造半导体芯片100的工艺和/或制造包括半导体芯片100的半导体封装件的工艺中将半导体芯片100固定到载体基底(图9C至图9G的10)。
具体地，由于绝缘层140包括具有位于其间的台阶高度并构成不同层的第一水平部分140P1和第二水平部分140P2，因此导电柱156与第一水平部分140P1的侧表面140S1之间的具有相对窄宽度的空间的高度可以设定得比导电柱156与绝缘层140之间的空间的高度相对小。因此，用于保护半导体基底110的绝缘层140可以覆盖半导体基底110的上表面的相对大部分，此外，可以宽裕地保证导电柱156与绝缘层140之间的空间，从而防止由于粘合层20的一部分残留而出现的缺陷。因此，确保了半导体芯片100的可靠性。
参照图2B，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。绝缘层140可以设置在半导体基底110的上表面上。绝缘层140可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140可以与连接凸块160分隔开并且可以围绕连接凸块160。
在图2B中，取代图2A的钝化层130，示出了钝化层130a。钝化层130a可以设置在半导体基底110的上表面与绝缘层140之间。钝化层130a可以从半导体基底110的上表面与绝缘层140之间的空间延伸到连接垫120与导电柱156之间的空间。钝化层130a可以覆盖半导体基底110的上表面的除了连接垫120的上表面的一部分之外的全部部分。
导电柱156可以与连接垫120的上表面的、未被钝化层130a覆盖的部分接触。
钝化层130a可以覆盖半导体基底110的上表面的未被绝缘层140和导电柱156覆盖的部分以及连接垫120的上表面的未被绝缘层140和导电柱156覆盖的部分。
参照图2C，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。在图2C中，取代图2A中的钝化层130和绝缘层140，示出了钝化层130b和绝缘层140a。
绝缘层140a可以设置在半导体基底110的上表面上。绝缘层140a可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140a可以与连接凸块160分隔开并且可以围绕连接凸块160。钝化层130b可以设置在半导体基底110的上表面与绝缘层140a之间。
绝缘层140a可以包括作为与半导体基底110相邻的下部的第一水平部分140P1a和位于第一水平部分140P1a上的第二水平部分140P2a。第一水平部分140P1a和第二水平部分140P2a可以是绝缘层140a的设置为一体的部分。第一水平部分140P1a可以是在绝缘层140a的下部处构成一个层的部分，第二水平部分140P2a可以是在第一水平部分140P1a上构成另一层的部分。在图2C中，绝缘层140a示出为包括构成两个层的第一水平部分140P1a和第二水平部分140P2a，但是不限于此。在其他实施例中，绝缘层140a可以包括构成三层或更多层的三个或更多个水平部分。
第二水平部分140P2a的近似宽度可以具有比第一水平部分140P1a的近似宽度的值小的值。第一水平部分140P1a和第二水平部分140P2a中的每个的宽度可以随着与半导体基底110的距离增大而减小。第一水平部分140P1a的近似宽度可以表示第一水平部分140P1a的平均宽度，第二水平部分140P2a的近似宽度可以表示第二水平部分140P2a的平均宽度。第一水平部分140P1a和第二水平部分140P2a可以具有位于其间的台阶高度，使得绝缘层140a在从第二水平部分140P2a的上表面140H2a至第一水平部分140P1a的上表面140H1a的方向上凹入。
也就是说，绝缘层140a可以包括具有位于其间的台阶高度并构成不同层的第一水平部分140P1a和第二水平部分140P2a。
第一水平部分140P1a的侧表面140S1a和第二水平部分140P2a的侧表面140S2a可以均延伸为相对于半导体基底110的上表面倾斜。第一水平部分140P1a的侧表面140S1a可以是延伸为相对于半导体基底110的上表面具有第一角度θ1的斜率的倾斜表面，第二水平部分140P2a的侧表面140S2a可以是延伸为相对于半导体基底110的上表面具有第二角度θ2的斜率的倾斜表面。第一角度θ1和第二角度θ2可以均具有在90度至180度范围内的值。在一些实施例中，第一角度θ1和第二角度θ2可以具有相同值。
第一水平部分140P1a的侧表面140S1a和钝化层130b的侧表面130Sb可以在与相对于半导体基底110的上表面的第一角度θ1对应的方向上对齐。第二水平部分140P2a的侧表面140S2a可以将第二水平部分140P2a的上表面140H2a连接至第一水平部分140P1a的上表面140H1a。导电柱156的上表面可以在与半导体基底110的上表面垂直的方向上位于比绝缘层140a的最上表面(即，第二水平部分140P2a的上表面140H2a)高的水平上。
第一水平部分140P1a的侧表面140S1a和第二水平部分140P2a的侧表面140S2a中的每个可以是延伸为随着与半导体基底110的上表面的距离增大变得更远离连接凸块160的部分的倾斜表面。
第二水平部分140P2a的侧表面140S2a可以比第一水平部分140P1a的侧表面140S1a更远离连接凸块160。因此，两个第二水平部分140P2a的彼此面对且具有连接凸块160位于其间的侧表面140S2a之间的宽度可以比两个第一水平部分140P1a的彼此面对且具有连接凸块160位于其间的侧表面140S1a之间的宽度大。
参照图2D，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。
绝缘层140a可以设置在半导体基底110的上表面上。绝缘层140a可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140a可以与连接凸块160分隔开并且可以围绕连接凸块160。
在图2D中，取代图2C的钝化层130b，示出了钝化层130a。钝化层130a可以设置在半导体基底110的上表面与绝缘层140a之间。钝化层130a可以从半导体基底110与绝缘层140a之间的空间延伸到连接垫120与导电柱156之间的空间。钝化层130a可以覆盖半导体基底110的上表面的除了连接垫120的上表面的一部分之外的全部部分。
导电柱156可以与连接垫120的上表面的、未被钝化层130a覆盖的部分接触。
钝化层130a可以覆盖半导体基底110的上表面的未被绝缘层140a和导电柱156覆盖的部分以及连接垫120的上表面的未被绝缘层140a和导电柱156覆盖的部分。
参照图2E，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。在图2E中，取代图2A的钝化层130和绝缘层140，示出了钝化层130b和绝缘层140b。
绝缘层140b可以设置在半导体基底110的上表面上。绝缘层140b可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140b可以与连接凸块160分隔开并且可以围绕连接凸块160。
钝化层130b可以设置在半导体基底110的上表面与绝缘层140b之间。
绝缘层140b可以包括作为与半导体基底110相邻的下部的第一水平部分140P1b和位于第一水平部分140P1b上的第二水平部分140P2b。第一水平部分140P1b和第二水平部分140P2b可以是绝缘层140b的设置为一体的部分。第一水平部分140P1b可以是在绝缘层140b的下部处构成一个层的部分，第二水平部分140P2b可以是在第一水平部分140P1b上构成另一层的部分。在图2E中，绝缘层140b示出为包括构成两个层的第一水平部分140P1b和第二水平部分140P2b，但是不限于此。在其他实施例中，绝缘层140b可以包括构造三层或更多层的三个或更多个水平部分。
第二水平部分140P2b的近似宽度可以具有比第一水平部分140P1b的近似宽度的值小的值。第一水平部分140P1b和第二水平部分140P2b可以具有位于其间的台阶高度，使得绝缘层140b在从第二水平部分140P2b的上表面140H2b至第一水平部分140P1b的上表面140H1b的方向上凹入。
也就是说，绝缘层140b可以包括具有位于其间的台阶高度并构成不同层的第一水平部分140P1b和第二水平部分140P2b。在一些实施例中，绝缘层140b也可以不具有位于其间的台阶高度而是仅包括构成不同层的第一水平部分140P1b和第二水平部分140P2b。
第一水平部分140P1b的侧表面140S1b和第二水平部分140P2b的侧表面140S2b可以均延伸为相对于半导体基底110的上表面倾斜。第一水平部分140P1b的侧表面140S1b可以是延伸为相对于半导体基底110的上表面具有第一角度θ1b的斜率的倾斜表面，第二水平部分140P2b的侧表面140S2b可以是延伸为相对于半导体基底110的上表面具有第二角度θ2b的上表的斜率的倾斜表面。第一角度θ1b和第二角度θ2b均可以具有在90度至180度范围内的值。在一些实施例中，第一角度θ1b和第二角度θ2b可以具有不同值。例如，第一角度θ1b可以具有比第二角度θ2b的值大的值。在一些实施例中，第一角度θ1b可以具有比第二角度θ2b的值小的值。
第一水平部分140P1b的侧表面140S1b与钝化层130b的侧表面130Sb可以在与相对于半导体基底110的上表面的第一角度θ1b对应的方向上对齐。第二水平部分140P2b的侧表面140S2b可以将第二水平部分140P2b的上表面140H2b连接至第一水平部分140P1b的上表面140H1b。导电柱156的上表面可以在与半导体基底110的上表面垂直的方向上位于比绝缘层140b的最上表面(即，第二水平部分140P2b的上表面140H2b)高的水平上。
第一水平部分140P1b的侧表面140S1b和第二水平部分140P2b的侧表面140S2b中的每个可以是延伸为随着与半导体基底110的上表面的距离增大变得更远离连接凸块160的部分的倾斜表面。
第二水平部分140P2b的侧表面140S2b可以比第一水平部分140P1b的侧表面140S1b更远离连接凸块160。因此，两个第二水平部分140P2b的彼此面对且具有连接凸块160位于其间的侧表面140S2b之间的宽度可以比两个第一水平部分140P1b的彼此面对且具有连接凸块160位于其间的侧表面140S1b之间的宽度大。
参照图2F，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。绝缘层140b可以设置在半导体基底110的上表面上。绝缘层140b可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140b可以与连接凸块160分隔开并且可以围绕连接凸块160。
在图2F中，取代图2E的钝化层130b，示出了钝化层130a。钝化层130a可以设置在半导体基底110的上表面与绝缘层140b之间。钝化层130a可以从半导体基底110的上表面与绝缘层140b之间的空间延伸到连接垫120与导电柱156之间的空间。钝化层130a可以覆盖半导体基底110的上表面的除了连接垫120的上表面的一部分之外的全部部分。
导电柱156可以与连接垫120的上表面的、未被钝化层130a覆盖的部分接触。
钝化层130a可以覆盖半导体基底110的上表面的未被绝缘层140b和导电柱156覆盖的部分以及连接垫120的上表面的未被绝缘层140b和导电柱156覆盖的部分。
参照图2G，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。在图2G中，取代图2A中的钝化层130和绝缘层140，示出了钝化层130b和绝缘层140c。
绝缘层140c可以设置在半导体基底110的上表面上。绝缘层140c可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140c可以与连接凸块160分隔开并且可以围绕连接凸块160。
钝化层130b可以设置在半导体基底110的上表面与绝缘层140c之间。
绝缘层140c可以包括作为与半导体基底110相邻的下部的第一水平部分140P1c和位于第一水平部分140P1c上的第二水平部分140P2c。第一水平部分140P1c和第二水平部分140P2c可以是绝缘层140c的设置为一体的部分。第一水平部分140P1c可以是在绝缘层140c的下部处构成一个层的部分，第二水平部分140P2c可以是在第一水平部分140P1c上构成另一层的部分。在图2G中，绝缘层140c示出为包括构成两个层的第一水平部分140P1c和第二水平部分140P2c，但是不限于此。在其他实施例中，绝缘层140c可以包括构成三层或更多层的三个或更多个水平部分。
第二水平部分140P2c的近似宽度可以具有比第一水平部分140P1c的近似宽度的值小的值。第一水平部分140P1c和第二水平部分140P2c可以具有位于其间的台阶高度，使得绝缘层140c在从第二水平部分140P2c的上表面140H2c至第一水平部分140P1c的上表面140H1c的方向上凹入。
也就是说，绝缘层140c可以包括具有位于其间的台阶高度并构造不同层的第一水平部分140P1c和第二水平部分140P2c。
第一水平部分140P1c的侧表面140S1c可以延伸为相对于半导体基底110的上表面倾斜。第一水平部分140P1c的侧表面140S1c可以是延伸为相对于半导体基底110的上表面具有在90度至180度范围内的值的特定角度的斜率的倾斜表面。
第二水平部分140P2c的侧表面140S2c可以是延伸为在第一水平部分140P1c的上表面140H1c与第二水平部分140P2c的上表面140H2c之间倒圆的倾斜表面。第二水平部分140P2c的侧表面140S2c可以被倒圆以具有朝向第二水平部分140P2c突出的凸起形状。
第一水平部分140P1c的侧表面140S1c和钝化层130b的侧表面130Sb可以在与相对于半导体基底110的上表面具有在90度至180度范围内的值的特定角度对应的方向上对齐。
导电柱156的上表面可以在与半导体基底110的上表面垂直的方向上位于比绝缘层140c的最上表面(即，第二水平部分140P2c的上表面140H2c)高的水平上。
第一水平部分140P1c的侧表面140S1c和第二水平部分140P2c的侧表面140S2c中的每个可以是延伸为随着与半导体基底110的上表面的距离增大变得更远离连接凸块160的部分的倾斜表面。
第二水平部分140P2c的侧表面140S2c可以比第一水平部分140P1c的侧表面140S1c更远离连接凸块160。因此，两个第二水平部分140P2c的彼此面对且具有连接凸块160位于其间的侧表面140S2c之间的宽度可以比两个第一水平部分140P1c的彼此面对且具有连接凸块160位于其间的侧表面140S1c之间的宽度大。
参照图2H，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。绝缘层140c可以设置在半导体基底110的上表面上。绝缘层140c可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140c可以与连接凸块160分隔开并且可以围绕连接凸块160。
在图2H中，取代图2G的钝化层130b，示出了钝化层130a。钝化层130a可以设置在半导体基底110的上表面与绝缘层140c之间。钝化层130a可以从半导体基底110的上表面与绝缘层140c之间的空间延伸到连接垫120与导电柱156之间的空间。钝化层130a可以覆盖半导体基底110的上表面的除了连接垫120的上表面的一部分之外的全部部分。
导电柱156可以与连接垫120的上表面的、未被钝化层130a覆盖的部分接触。
钝化层130a可以覆盖半导体基底110的上表面的未被绝缘层140c和导电柱156覆盖的部分以及连接垫120的上表面的未被绝缘层140c和导电柱156覆盖的部分。
参照图2I，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。在图2I中，取代图2C中的绝缘层140a，示出了绝缘层140d。
绝缘层140d可以设置在半导体基底110的上表面上。绝缘层140d可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140d可以与连接凸块160分隔开并且可以围绕连接凸块160。钝化层130b可以设置在半导体基底110的上表面与绝缘层140d之间。
绝缘层140d可以包括作为与半导体基底110相邻的下部的第一水平部分140P1d、位于第一水平部分140P1d上的第二水平部分140P2d以及位于第二水平部分140P2d上的第三水平部分140P3d。第一水平部分140P1d、第二水平部分140P2d和第三水平部分140P3d可以是绝缘层140d的设置为一体的部分。第一水平部分140P1d可以是在绝缘层140d的下部处构成一个层的部分，第三水平部分140P3d可以是在绝缘层140d的上部处构成一个层的部分，第二水平部分140P2d可以是在第一水平部分140P1d与第三水平部分140P3d之间构成另一层的部分。在图2I中，绝缘层140d示出为包括构成三个层的第一水平部分140P1d、第二水平部分140P2d和第三水平部分140P3d，但是不限于此。在其他实施例中，绝缘层140d可以包括构成四层或更多层的四个或更多个水平部分。
第三水平部分140P3d的近似宽度可以具有比第二水平部分140P2d的近似宽度的值小的值，第二水平部分140P2d的近似宽度可以具有比第一水平部分140P1d的近似宽度的值小的值。第二水平部分140P2d和第三水平部分140P3d可以具有位于其间的台阶高度，使得绝缘层140d在从第三水平部分140P3d的上表面140H3d至第二水平部分140P2d的上表面140H2d的方向上凹入，第一水平部分140P1d和第二水平部分140P2d可以具有位于其间的台阶高度，使得绝缘层140d在从第二水平部分140P2d的上表面140H2d至第一水平部分140P1d的上表面140H1d的方向上凹入。
也就是说，绝缘层140d可以包括具有位于其间的台阶高度并构造不同层的第一水平部分140P1d、第二水平部分140P2d和第三水平部分140P3d。
第一水平部分140P1d的侧表面140S1d、第二水平部分140P2d的侧表面140S2d以及第三水平部分140P3d的侧表面140S3d可以均延伸为相对于半导体基底110的上表面倾斜。在一些实施例中，第一水平部分140P1d的侧表面140S1d、第二水平部分140P2d的侧表面140S2d以及第三水平部分140P3d的侧表面140S3d可以是延伸为相对于半导体基底110的上表面具有在90度至180度范围内的值的相同角度的斜率的倾斜表面。在一些其他实施例中，第一水平部分140P1d的侧表面140S1d、第二水平部分140P2d的侧表面140S2d以及第三水平部分140P3d的侧表面140S3d可以是延伸为相对于半导体基底110的上表面具有在90度至180度范围内的值的角度的斜率的倾斜表面，在这种情况下，至少一个倾斜的表面可以延伸为具有另一角度的斜率。在一些其他实施例中，第一水平部分140P1d的侧表面140S1d、第二水平部分140P2d的侧表面140S2d以及第三水平部分140P3d的侧表面140S3d可以在与半导体基底110的上表面垂直的方向上延伸。
第一水平部分140P1d的侧表面140S1d和钝化层130b的侧表面130Sb可以在与相对于半导体基底110的上表面的相同角度对应的方向上对齐。在一些实施例中，第一水平部分140P1d的侧表面140S1d和钝化层130b的侧表面130Sb可以在与相对于半导体基底110的上表面在90度至180度范围内的相同角度对应的方向上对齐。在一些其他实施例中，第一水平部分140P1d的侧表面140S1d和钝化层130b的侧表面130Sb可以在与半导体基底110的上表面垂直的方向上对齐。
第二水平部分140P2d的侧表面140S2d可以将第二水平部分140P2d的上表面140H2d连接至第一水平部分140P1d的上表面140H1d，第三水平部分140P3d的侧表面140S3d可以将第三水平部分140P3d的上表面140H3d连接到第二水平部分140P2d的上表面140H2d。导电柱156的上表面可以在与半导体基底110的上表面垂直的方向上位于比绝缘层140d的最上表面(即，第三水平部分140P3d的上表面140H3d)高的水平上。
第一水平部分140P1d的侧表面140S1d、第二水平部分140P2d的侧表面140S2d以及第三水平部分140P3d的侧表面140S3d中的每个可以是延伸为随着与半导体基底110的上表面的距离增大变得更远离连接凸块160的部分的倾斜表面。
第三水平部分140P3d的侧表面140S3d可以比第二水平部分140P2d的侧表面140S2d更远离连接凸块160，第二水平部分140P2d的侧表面140S2d可以比第一水平部分140P1d的侧表面140S1d更远离连接凸块160。因此，两个第三水平部分140P3d的彼此面对且具有连接凸块160位于其间的侧表面140S3d之间的宽度可以比两个第二水平部分140P2d的彼此面对且具有连接凸块160位于其间的侧表面140S2d之间的宽度大，两个第二水平部分140P2d的彼此面对且具有连接凸块160位于其间的侧表面140S2d之间的宽度可以比两个第一水平部分140P1d的彼此面对且具有连接凸块160位于其间的侧表面140S1d之间的宽度大。
参照图2J，连接凸块160可以附着在设置在作为半导体基底110的上表面的有效表面上的连接垫120上。绝缘层140d可以设置在半导体基底110的上表面上。绝缘层140d可以暴露连接垫120并且可以覆盖半导体基底110的上表面的一部分。绝缘层140d可以与连接凸块160分隔开并且可以围绕连接凸块160。
在图2J中，取代图2I的钝化层130b，示出了钝化层130a。钝化层130a可以设置在半导体基底110的上表面与绝缘层140d之间。钝化层130a可以从半导体基底110的上表面与绝缘层140d之间的空间延伸到连接垫120与导电柱156之间的空间。钝化层130a可以覆盖半导体基底110的上表面的除了连接垫120的上表面的一部分之外的全部部分。
导电柱156可以与连接垫120的上表面的、未被钝化层130a覆盖的部分接触。
钝化层130a可以覆盖半导体基底110的上表面的未被绝缘层140d和导电柱156覆盖的部分以及连接垫120的上表面的未被绝缘层140d和导电柱156覆盖的部分。
以上描述了与图1的部分A中的连接凸块对应的情况，但是发明构思不限于此。在一些其他实施例中，与图1的部分A中的连接凸块相邻的连接凸块可以具有相同的结构。在这种情况下，绝缘层140的位于两个相邻的连接凸块之间的部分可以具有彼此相对的第一侧壁和第二侧壁。第一侧壁和第二侧壁中的每者可以具有如图2A至图2J中所述的结构。
图3A至图3D是示出根据实施例的半导体芯片的连接凸块的放大平面图。
参照图3A至图3D，钝化层130和绝缘层140可以与附着在连接垫120上的连接凸块160分隔开并且可以围绕连接凸块160。在图3A至图3D中，示出了设置在连接凸块160的最上端上的导电盖158。
第一水平部分140P1的侧表面140S1与第二水平部分140P2的侧表面140S2可以在半导体基底(图1和图2A的110)的上表面的水平方向上延伸为直线，并且可以围绕连接凸块160。
在图3A至图3D中，示出的是第一水平部分140P1的侧表面140S1与第二水平部分140P2的侧表面140S2中的每个设置为在半导体基底110的上表面的水平方向上具有四边形形状、五边形形状、六边形形状或八边形形状并且围绕连接凸块160，但是本实施例不限于此。
例如，第一水平部分140P1的侧表面140S1和第二水平部分140P2的侧表面140S2中的每个可以具有n角形形状(n≥4)并且可以围绕连接凸块160。
图4是示出根据实施例的包括半导体芯片的半导体封装件1000的剖视图。
参照图4，半导体封装件1000可以包括多个半导体芯片。所述多个半导体芯片可以包括第一半导体芯片100a和多个第二半导体芯片200。
在一些实施例中，第一半导体芯片100a可以是包括串并行转换电路的缓冲器芯片，多个第二半导体芯片200可以均为高带宽存储器动态随机存取存储器(HBM DRAM)半导体芯片。
第一半导体芯片100a可以通常具有与图1的半导体芯片100的结构相似的结构。第一半导体芯片100a可以包括第一半导体基底110、第一连接垫120、第一绝缘层140、以及包含第一导电柱156和第一导电盖158的第一连接凸块160。第一半导体基底110、第一连接垫120、第一绝缘层140、以及包含第一导电柱156和第一导电盖158的第一连接凸块160是与图1中示出的半导体基底110、连接垫120、绝缘层140、以及包含导电柱156和导电盖158的连接凸块160基本相同的元件，因此，省略了它们的详细描述。
第一半导体芯片100a还可以包括第一通过电极170和第二连接垫180。第一通过电极170可以将第一连接垫120连接至第二连接垫180。第一连接垫120和第二连接垫180可以分别设置在第一半导体基底110的有效表面和无效表面上。
第一通过电极170可以包括穿过第一半导体基底110的导电塞以及围绕导电塞的导电阻挡层。导电塞可以具有圆柱形形状，导电阻挡层可以具有围绕导电塞的侧壁的圆柱形形状。导电塞可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW、W或W合金，但是不限于此。导电塞可以包括，例如，Al、Au、铍(Be)、Bi、钴(Co)、Cu、铪(Hf)、In、锰(Mn)、钼(Mo)、Ni、Pb、Pd、Pt、铑(Rh)、铼(Re)、钌(Ru)、钽(Ta)、碲(Te)、钛(Ti)、W、Zn和锆(Zr)中的一种或更多种，并且可以包括一种或更多种堆叠结构。导电阻挡层可包括例如选自W、WN、WC、Ti、TiN、Ta、TaN、Ru、Co、Mn、WN、Ni和NiB中的至少一种材料，但不限于此。
过孔绝缘层可以设置在第一半导体基底110与第一通过电极170之间并且可以围绕第一通过电极170的侧壁。过孔绝缘层可以包括氧化物、氮化物、碳化物、聚合物或它们的组合。过孔绝缘层可以包括，例如，臭氧/四乙基正硅酸盐(O3/TEOS)类高纵横比工艺(HARP)氧化物。
在图4中，示出了第一通过电极170将第一连接垫120直接连接至第二连接垫180的示例，但是本实施例不限于此。在其他实施例中，第一通过电极170可以设置为具有过孔-第一结构、过孔-中间结构和过孔-最终结构中的一个。
多个第二半导体芯片200可以堆叠在第一半导体芯片100a上。
多个第二半导体芯片200均可以包括第二半导体基底210、第二顶部连接垫220、第二绝缘层240以及包含第二导电柱256和第二导电盖258的第二连接凸块260。
多个第二半导体芯片200中的每个还可以包括第二通过电极270和第二连接垫280。在一些实施例中，多个第二半导体芯片200中的最上端第二半导体芯片200可以不包括第二通过电极270和第二连接垫280。
第二半导体基底210、第二顶部连接垫220、第二绝缘层240、包括第二导电柱256和第二导电盖258的第二连接凸块260、第二通过电极270以及第二连接垫280与第一半导体基底110、第一连接垫120、第一绝缘层140、包括第一导电柱156和第一导电盖158的第一连接凸块160、第一通过电极170以及第二连接垫180基本相似。因此，在下文中省略了重复的描述，将主要描述区别。
多个第二半导体芯片200中的设置在上部中的第二半导体芯片200可以通过下第二半导体芯片200中包括的第二通过电极270电连接至第一半导体芯片100a。
绝缘粘合层350可以设置在第一半导体芯片100a与一个第二半导体芯片200之间以及两个相邻的第二半导体芯片200之间。绝缘粘合层350可以包括非导电膜(NCF)或非导电膏(NCP)。可选择地，绝缘粘合层350可以包括诸如绝缘聚合物或环氧树脂的底部填充材料。
半导体封装件1000可以包括设置在第一半导体芯片100a上以围绕多个第二半导体芯片200中的每个的侧表面以及绝缘粘合层350的侧表面的成型层300。成型层300可以包括，例如，环氧成型化合物(EMC)。
第一半导体芯片100a中包括的多个第一连接凸块160可以以第一间距布置，多个第二半导体芯片200中的每个中包括的多个第二连接凸块260可以以第二间距布置。在一些实施例中，第一间距和第二间距可以具有相同值。
图5A和图5B是示出根据实施例的半导体封装件中包括的半导体芯片的连接凸块的放大剖视图。详细地，图5A和图5B是示出图4的部分B和部分C的放大剖视图。
参照图5A、图5B和图4，第一半导体芯片100a可以包括第一钝化层130、第一绝缘层140以及包括第一导电柱156和第一导电盖158的第一连接凸块160。第一半导体芯片100a可以包括第一半导体基底110、第一连接垫120、第一绝缘层140以及包括第一导电柱156和第一导电盖158的第一连接凸块160。第二半导体芯片200可以包括第二钝化层230、第二绝缘层240以及包括第二导电柱256和第二导电盖258的第二连接凸块260。第一钝化层130是与图1的钝化层130基本相同的元件，第二钝化层230与第一钝化层130基本相似。
第一导电柱156可以包括第一基体柱152和覆盖第一基体柱152的上表面的第一覆盖柱154。第二导电柱256可以包括第二基体柱252和覆盖第二基体柱252的上表面的第二覆盖柱254。第一基体柱152是与图1的基体柱152基本相同的元件，第二基体柱252与第一基体柱152基本相似。第一覆盖柱154是与图1的覆盖柱154基本相同的元件，第二覆盖柱254与第一覆盖柱154基本相似。因此，在下文中省略了重复的描述，将主要描述区别。
第一绝缘层140可以包括与第一半导体基底110相邻的第一水平部分140P1以及位于第一水平部分140P1上的第二水平部分140P2。第一水平部分140P1和第二水平部分140P2可以是第一绝缘层140设置为一体的部分。第一水平部分140P1和第二水平部分140P2可以具有位于其间的台阶高度。也就是说，第一绝缘层140可以包括具有位于其间的台阶高度并构成不同层的第一水平部分140P1和第二水平部分140P2。换言之，第一绝缘层140可以包括构成具有位于其间的台阶高度的两个层或更多个层的两个或更多个水平部分。
第二绝缘层240可以仅由一个层构成。也就是说，第二绝缘层240可以具有由一个层构成以不具有台阶高度的单层结构。
第一导电柱156可以具有第一宽度W1和第一高度H1，第二导电柱256可以具有第二宽度W2和第二高度H2。
第一宽度W1可以具有比第二宽度W2大的值，第一高度H1可以具有比第二高度H2大的值。例如，第一宽度W1可以是15μm至40μm，第二宽度W2可以是比第一宽度W1小的范围内的10μm至30μm。例如，第一高度H1可以是10μm至30μm，第二高度H2可以是比第一高度H1小的范围内的2μm至15μm。
第一高度H1与第一宽度W1的比(即，第一导电柱156的纵横比)可以具有比第二高度H2与第二宽度W2的比(即，第二导电柱256的纵横比)高的值。例如，第一导电柱156的纵横比可以是0.5至1.5，第二导电柱256的纵横比可以是比第一导电柱156的纵横比小的范围内的0.1至1。
制造第一半导体芯片100a的工艺、制造第二半导体芯片200的工艺、制造包括第一半导体芯片100a和第二半导体芯片200的半导体封装件1000的工艺可以包括通过使用粘合层将第一半导体芯片100a和/或第二半导体芯片200固定到载体基底，然后从第一半导体芯片100a和/或第二半导体芯片200去除载体基底和粘合层的工艺。
在这样的工艺中，当第一导电柱156的纵横比大于第二导电柱256的纵横比时，粘合层的一部分残留在第一半导体芯片100a的第一绝缘层140与第一导电柱156之间的可能性会高。然而，根据本实施例的半导体封装件1000可以具有第一半导体芯片100a的第一绝缘层140具有台阶高度的单层结构，因而，可以确保第一连接凸块160与第一绝缘层140之间的空间，从而防止粘合层的一部分残留在第一连接凸块160与第一绝缘层140之间。
图6A至图6C是示出根据实施例的半导体芯片的连接凸块的放大剖视图。详细地，图6A至图6C是与图4的部分C对应的部分的放大剖视图。
参照图6A，第二钝化层230a可以设置在第二半导体基底210的上表面与第二绝缘层240之间。在图6A中，取代图5B的第二钝化层230，示出了第二钝化层230a。第二钝化层230a可以从第二半导体基底210的上表面与第二绝缘层240之间的空间延伸至第二连接垫220和第二导电柱256之间的空间。第二钝化层230a可以覆盖第二半导体基底210的上表面的除了第二连接垫220的上表面的一部分之外的全部部分。
第二导电柱256可以与第二连接垫220的上表面的未被第二钝化层230a覆盖的部分接触。第二钝化层230a可以覆盖第二半导体基底210的上表面的未被第二绝缘层240和第二导电柱256覆盖的部分以及第二连接垫220的上表面的未被第二绝缘层240和第二导电柱256覆盖的部分。
参照图6B，第二绝缘层240b可以设置在第二半导体基底210的上表面上。第二绝缘层240b可以暴露第二连接垫220并且可以覆盖第二半导体基底210的上表面的一部分。第二钝化层230b可以设置在第二半导体基底210的上表面与第二绝缘层240b之间。
在图6B中，取代图5B的第二钝化层230和第二绝缘层240，示出了第二钝化层230b和第二绝缘层240b。
第二钝化层230b和第二绝缘层240b中的每个的侧表面可以延伸为相对于第二半导体基底210的上表面倾斜。
参照图6C，第二钝化层230a可以设置在第二半导体基底210的上表面与第二绝缘层240b之间。在图6C中，取代图6B的第二钝化层230b，示出了第二钝化层230a。第二钝化层230a可以从第二半导体基底210的上表面与第二绝缘层240b之间的空间延伸至第二连接垫220与第二导电柱256之间的空间。第二钝化层230a可以覆盖第二半导体基底210的上表面的除了第二连接垫220的上表面的一部分之外的全部部分。
第二导电柱256可以与第二连接垫220的上表面的未被第二钝化层230a覆盖的部分接触。第二钝化层230a可以覆盖第二半导体基底210的上表面的未被第二绝缘层240b和第二导电柱256覆盖的部分以及第二连接垫220的上表面的未被第二绝缘层240b和第二导电柱256覆盖的部分。
此外，尽管未示出，但是对于本领域技术人员而言明显的是，图4和图5A中的第一半导体芯片100a中包括的第一钝化层130和第一绝缘层140被图2B至图2J中示出的第一钝化层130a或130b以及第一绝缘层140a、140b、140c或140d取代。
图7A至图7C是顺序地示出根据实施例的制造半导体芯片的方法的剖视图。详细地，图7A至图7C是顺序地示出制造图2A中示出的半导体芯片100的方法的剖视图。
参照图7A，可以在包括连接垫120的半导体基底110上顺序地形成预备钝化层130PL和预备绝缘层140PL。预备化钝化层130PL可以包括例如诸如氧化物或氮化物的无机材料。预备绝缘层140PL可以包括例如PSPI。
接下来，可以在半导体基底110上设置包括透光部RE、阻光部RD和条状图案部RH的掩模MK1。透光部RE可以透射从应用于光刻工艺的曝光设备辐射的光的大部分，阻光部RD可以阻挡辐射光的大部分。条状图案部RH可以包括重复布置的多个散射条状图案。条状图案部RH可以仅透射从应用于光刻工艺的曝光设备辐射的光的一部分并且可以阻挡其他光。
设置在条状图案部RH中的多个散射条状图案可以具有一维并且由多个n(n≥4)角顺序围绕的形状。在多个散射条状图案中，每个部分可以以直线形状延伸，并且可以不设置以弯曲形状延伸的部分。
参照图7B，可以通过穿过掩模MK1向半导体基底110上照射光来使预备绝缘层(图7A的140PL)的一部分曝光。
可以使预备绝缘层140PL的与掩模MK1的透光部RE对应的部分完全曝光，并且可以不使与阻光部RD对应的所有部分曝光。此外，可以使预备绝缘层140PL的与条状图案部RH对应的部分的上部的仅一部分曝光。
因此，图7A中示出的预备绝缘层140PL可以包括利用掩模MK1通过光刻工艺曝光的第一部分140EX和未被曝光的第二部分140DK。
参照图7C，可以通过去除第一部分140EX来形成包括设置为一体的第一水平部分140P1和第二水平部分140P2的绝缘层140，使得保留图7B中示出的第二部分140DK。在去除第一部分140EX的工艺中，可以一起去除预备钝化层(图7A的130PL)的一部分，因此，可以在半导体基底110与绝缘层140之间形成钝化层130。
图8A至图8C是顺序示出根据实施例的制造半导体芯片的方法的剖视图。详细地，图8A至图8C是顺序地示出制造图2B中示出的半导体芯片的方法的剖视图。
参照图8A，可以在包括连接垫120的半导体基底110上形成未覆盖连接垫120的一部分的钝化层130a。可以通过在形成了预备钝化层130PL(见图7A)之后去除预备钝化层130PL的设置在连接垫120上的一部分来形成钝化层130a。接下来，可以形成覆盖其上形成有钝化层130a的半导体基底110的预备绝缘层140PL。
参照图8B和图8C，与图7B和图7C的示例类似，可以利用掩模MK1通过光刻工艺将预备绝缘层(图8A的140PL)分为被曝光的第一部分140EX和未曝光的第二部分140DK。接下来，可以通过去除第一部分140EX来形成包括设置为一体的第一水平部分140P1和第二水平部分140P2的绝缘层140，使得保留第二部分140DK。当钝化层130a相对于去除第一部分140EX的工艺具有抗蚀刻性时，在去除第一部分140EX的工艺中钝化层130a的一部分可以不被去除。
图9A至图9G是顺序示出根据实施例的制造半导体封装件的方法的剖视图。
参照图9A，可以提供其上形成有第一连接垫120和第一通过电极170的第一预备半导体基底110p。
参照图9B，可以在第一预备半导体基底110p的上表面上形成暴露第一连接垫120而不覆盖第一连接垫120的第一绝缘层140。尽管未示出，但是可以在第一预备半导体基底110p与第一绝缘层140之间设置第一钝化层(图7C的130或图8C的130a)。可以通过上面参照图7A至图7C或图8A至图8C描述的方法来形成第一钝化层130或130a以及第一绝缘层140。
接下来，可以在第一连接垫120上形成包括第一导电柱156和第一导电盖158的第一连接凸块160。
参照图9C，为了使第一连接凸块160面对载体基底10，可以将第一预备半导体基底110p附着到载体基底10上，并且使粘合层20位于第一预备半导体基底110p与载体基底10之间。粘合层20可以填充第一绝缘层140与第一连接凸块160之间的空间并且可以围绕第一连接凸块160。
参照图9D，通过去除第一预备半导体基底(图9B的110p)的下表面的一部分，在第一半导体基底110的下表面处暴露第一通过电极170。接下来，可以在第一半导体基底110的下表面上形成连接至第一通过电极170的第二连接垫180，从而完成第一半导体芯片100a。
参照图9E，可以在第一半导体芯片100a上堆叠多个第二半导体芯片200。多个第二半导体芯片200中的每个可以通过绝缘粘合层350堆叠在第一半导体芯片100a上。
参照图9F，可以在第一半导体芯片100a上形成围绕多个第二半导体芯片200中的每个的侧表面和绝缘粘合层350的侧表面的成型层300。
参照图9G，可以通过从第一半导体芯片100a去除载体基底10和粘合层20来形成半导体封装件1000。
如上所述，第一半导体芯片100a的第一绝缘层140可以具有具备台阶高度的多层结构，因此，可以充分确保第一连接凸块160与第一绝缘层140之间的空间，从而防止粘合层20的一部分残留在第一连接凸块160与第一绝缘层140之间。
图10是示出包括根据实施例的半导体封装件的系统1的剖视图。
参照图10，系统1可以包括包含第一半导体芯片100a和多个第二半导体芯片200的半导体封装件1000，具有附着在其上的第三半导体芯片400的插入器500以及具有安装在其上的插入器500的主板600。
第三半导体芯片400可以包括第三半导体基底410、第三连接垫420、第三绝缘层440以及包括第三导电柱456和第三导电盖458的第三连接凸块460。第三半导体基底410和第三连接垫420是与图1中示出的半导体基底110和连接垫120基本相似的元件，第三绝缘层440是与图4中示出的第二绝缘层240基本相似的元件，第三连接凸块460是与图4中示出的第一连接凸块160或第二连接凸块260基本相似的元件。因此，在下文中，省略了它们的详细描述。
第三半导体芯片400可以是，例如，中央处理单元(CPU)芯片、图形处理单元(GPU)芯片或应用处理器(AP)芯片。
插入器500可以包括基体层510、设置在基体层510的上表面上的第一顶部垫520以及设置在基体层510的下表面上的第一底部垫530。
基体层510可以包括半导体、玻璃、陶瓷或塑料。例如，基体层510可以包括硅。连接到第一顶部垫520和/或第一底部垫530的布线层可以设置在基体层510的上表面和/或下表面上，将第一顶部垫520电连接到第一底部垫530的内部通过电极可以设置在基体层510中。半导体封装件1000的第一连接凸块160和第三半导体芯片400的第三连接凸块460可以连接到第一顶部垫520。
第一底部填充层380可以设置在半导体封装件1000与插入器500之间，第二底部填充层480可以设置在第三半导体芯片400与插入器500之间。第一底部填充层380和第二底部填充层480可以分别围绕第一连接凸块160和第三连接凸块460。
第一连接端子550可以附着到第一底部垫530上。第一连接端子550可以将插入器500电连接到主板600。
主板600可以包括基体板层610、设置在基体板层610的上表面上的第二顶部垫620以及设置在基体板层610的下表面上的第二底部垫630。
在一些实施例中，主板600可以是印刷电路板(PCB)。例如，主板600可以是多层PCB。基体板层610可包括选自酚醛树脂，环氧树脂和聚酰亚胺中的至少一种材料。基体板层610可包括例如选自框架阻燃剂4(FR4)、四官能环氧树脂、聚苯醚、环氧/聚苯醚、双马来酰亚胺三嗪(BT)、热量、氰酸酯、聚酰亚胺和液晶聚合物中的至少一种材料。
暴露第二顶部垫620的阻焊层可以形成在基体板层610的上表面上，暴露第二底部垫630的阻焊层(未示出)可以形成在基体板层610的下表面上。第一连接端子550可以连接到第二顶部垫620，第二连接端子650可以连接到第二底部垫630。第一连接端子550可以将第二底部垫630电连接到第二顶部垫620。连接到第二底部垫630的第二连接端子650可以执行外部连接端子的功能。
在一些实施例中，系统1可以不包括主板600，插入器500的第一连接端子550可以执行外部连接端子的功能。
根据实施例的半导体芯片可以包括绝缘层，所述绝缘层与连接凸块分隔开以围绕连接凸块并具有其中至少两个水平部分设置为具有置于其间的台阶高度的多层结构。绝缘层可以覆盖半导体基底的上表面的相对大部分，极大地确保了连接凸块的导电柱与绝缘层之间的空间。
因此，在制造半导体芯片的工艺和制造包括半导体芯片的半导体封装件的工艺中防止了由于粘合层的一部分残留在导电柱与绝缘层之间导致的缺陷，因此，确保了半导体芯片的可靠性，从而确保了包括半导体芯片的半导体封装件的可靠性。
虽然已经参照发明构思的实施例具体示出并描述了发明构思，但是将理解的是，在不脱离权利要求的精神和范围的情况下可以做出形式和细节上的各种改变。

Claims (25)

1.一种半导体装置，所述半导体装置包括：
半导体基底；
连接基体柱，位于半导体基底上；以及
绝缘层，位于半导体基底上，绝缘层包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的限定开口的侧壁包括在比连接基体柱的最上表面低的水平处的水平台阶。
2.如权利要求1所述的半导体装置，其中，绝缘层的侧壁包括位于水平台阶下方的下侧壁和位于水平台阶上方的上侧壁，下侧壁朝向连接基体柱向下倾斜，上侧壁朝向连接基体柱向下倾斜。
3.如权利要求2所述的半导体装置，其中，下侧壁通过绝缘层的下水平部分形成，上侧壁通过绝缘层的位于绝缘层的下水平部分上的上水平部分形成。
4.如权利要求2所述的半导体装置，所述半导体装置还包括：
钝化层，位于绝缘层与半导体基底之间，钝化层包括从绝缘层的下侧壁朝向半导体基底延伸的侧壁。
5.如权利要求4所述的半导体装置，其中，钝化层的侧壁朝向连接基体柱向下倾斜。
6.如权利要求4所述的半导体装置，所述半导体装置还包括：
连接垫，在连接基体柱之下位于半导体基底中，其中，绝缘层的下侧壁和钝化层两者与连接垫的一部分叠置。
7.如权利要求2所述的半导体装置，其中，下侧壁相对于半导体基底的倾斜程度大于或等于上侧壁相对于半导体基底的倾斜程度。
8.如权利要求2所述的半导体装置，其中，下侧壁相对于半导体基底的倾斜程度小于上侧壁相对于半导体基底的倾斜程度。
9.如权利要求2所述的半导体装置，其中，从绝缘层的上侧壁到水平台阶的过渡是逐渐的。
10.如权利要求2所述的半导体装置，所述半导体装置还包括：
钝化层，位于绝缘层与半导体基底之间，其中，钝化层在半导体基底上延伸到连接基体柱之下。
11.如权利要求1所述的半导体装置，其中，绝缘层的侧壁限定围绕连接基体柱的五边形形状。
12.如权利要求1所述的半导体装置，其中，绝缘层的侧壁限定围绕连接基体柱的八边形形状。
13.如权利要求2所述的半导体装置，其中，水平台阶包括第一水平台阶，半导体装置还包括位于上侧壁中的第二水平台阶。
14.如权利要求3所述的半导体装置，其中，下水平部分和上水平部分包括整体形成的绝缘层。
15.如权利要求1所述的半导体装置，其中，在水平台阶上方位于绝缘层的侧壁与连接基体柱之间的最宽空间是在水平台阶下方位于绝缘层的侧壁与连接基体柱之间的最宽空间的两倍。
16.一种半导体装置，所述半导体装置包括：
半导体基底；
微凸块结构，位于半导体基底上；
连接基体柱，包括在微凸块结构中；以及
绝缘层，位于半导体基底上，绝缘层包括位于绝缘层中的开口，连接基体柱穿过开口延伸，其中，绝缘层的位于开口的第一侧上的侧壁包括下侧壁和上侧壁，其中，下侧壁相对于半导体基底以第一角度朝向连接基体柱向下倾斜，上侧壁位于下侧壁上方并相对于半导体基底以不同于第一角度的第二角度朝向连接基体柱向下倾斜。
17.如权利要求16所述的半导体装置，所述半导体装置还包括：
水平台阶，位于绝缘层的侧壁中并位于下侧壁与上侧壁之间。
18.如权利要求16所述的半导体装置，其中，第一角度大于第二角度。
19.如权利要求16所述的半导体装置，其中，连接基体柱包括第一连接基体柱，开口包括第一开口，绝缘层的侧壁包括第一侧壁，半导体装置还包括：
第二连接基体柱，在半导体基底上与第一连接基体柱分隔开，其中，绝缘层包括第二开口，第二连接基体柱穿过第二开口延伸，第二开口通过绝缘层的与绝缘层的第一侧壁相对的第二侧壁形成。
20.如权利要求19所述的半导体装置，其中，第二侧壁包括下侧壁和上侧壁，其中，第二侧壁的下侧壁相对于半导体基底以第一角度朝向第二连接基体柱向下倾斜，第二侧壁的上侧壁位于下侧壁上并相对于半导体基底以第二角度朝向第二连接基体柱向下倾斜，所述半导体装置还包括：
水平台阶，位于绝缘层的第二侧壁中并位于第二侧壁的上侧壁与下侧壁之间。
21.如权利要求20所述的半导体装置，其中，从第二侧壁的上侧壁到第二水平台阶的过渡是逐渐的。
22.一种半导体装置，所述半导体装置包括：
半导体封装主板；
处理器芯片，位于半导体封装主板上；
插入器，位于处理器芯片与半导体封装主板之间，处理器芯片直接安装在插入器上；
缓冲器芯片，直接安装在插入器上并与处理器芯片分隔开，所述缓冲器芯片包括：第一连接基体柱，位于缓冲器芯片上，第一连接基体柱具有第一纵横比；以及绝缘层，位于缓冲器芯片上，绝缘层包括位于绝缘层中的开口，第一连接基体柱穿过开口延伸，其中，绝缘层的限定开口的侧壁包括水平台阶，所述水平台阶位于相对于绝缘层的从缓冲器芯片以最大距离突出的部分凹入的水平处；以及
高带宽动态随机存取存储器芯片，安装在缓冲器芯片上，高带宽动态随机存取存储器芯片包括具有比第一纵横比低的第二纵横比的第二连接基体柱。
23.如权利要求22所述的半导体装置，其中，绝缘层的侧壁包括第一侧壁和第二侧壁，第一侧壁位于水平台阶上方并朝向第一连接基体柱倾斜，第二侧壁位于水平台阶下方并朝向第一连接基体柱倾斜。
24.如权利要求22所述的半导体装置，其中，在水平台阶下方位于绝缘层的侧壁与第一连接基体柱之间的最宽空间是在水平台阶上方位于绝缘层的侧壁与第一连接基体柱之间的最宽空间的两倍。
25.如权利要求22所述的半导体装置，其中，第一连接基体柱的高度比第二连接基体柱的高度高，第一连接基体柱的宽度比第二连接基体柱的宽度大。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6687646B2 (ja) * 2016-02-10 2020-04-28 ウルトラメモリ株式会社 半導体装置
DE102020135088A1 (de) 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitervorrichtung
KR20220090793A (ko) 2020-12-23 2022-06-30 삼성전자주식회사 반도체 패키지

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130334656A1 (en) * 2012-06-13 2013-12-19 Samsung Electronics Co., Ltd. Electrical interconnection structures including stress buffer layers
CN107564894A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 制造半导体封装的方法
CN108172560A (zh) * 2016-11-29 2018-06-15 台湾积体电路制造股份有限公司 集成电路和用于制造集成电路的方法
CN108242437A (zh) * 2016-12-26 2018-07-03 拉碧斯半导体株式会社 半导体装置以及半导体装置的制造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181101A (ja) 1995-12-27 1997-07-11 Matsushita Electron Corp 半導体装置の製造方法
US6028011A (en) 1997-10-13 2000-02-22 Matsushita Electric Industrial Co., Ltd. Method of forming electric pad of semiconductor device and method of forming solder bump
KR20020058592A (ko) 2000-12-30 2002-07-12 박종섭 스캐터링바 래티클을 이용한 노광 방법
JP2003037129A (ja) 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
JP4210171B2 (ja) 2003-02-25 2009-01-14 京セラ株式会社 フリップチップ型ｉｃの製造方法
KR100583966B1 (ko) 2004-06-08 2006-05-26 삼성전자주식회사 재배치된 금속 배선들을 갖는 집적회로 패키지들 및 그제조방법들
KR100593745B1 (ko) 2004-12-17 2006-06-28 삼성전자주식회사 캐패시터의 스토리지 노드 형성방법
CN102282659B (zh) 2009-02-04 2013-11-20 松下电器产业株式会社 半导体基板结构及半导体装置
EP2522968B1 (en) 2009-11-30 2021-04-21 IMEC vzw Integrated circuit for spectral imaging system
KR101782503B1 (ko) * 2011-05-18 2017-09-28 삼성전자 주식회사 솔더 범프 붕괴를 억제하는 반도체 소자의 범프 형성방법
US20130320522A1 (en) 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
JP5543567B2 (ja) * 2012-10-22 2014-07-09 誠 雫石 半導体素子の製造方法
JP2015206862A (ja) 2014-04-18 2015-11-19 三菱製紙株式会社 感光性ポリイミドパターンの形成方法
CN105226007B (zh) 2014-06-13 2018-10-16 中芯国际集成电路制造(上海)有限公司 金属互连结构的制作方法
KR102382076B1 (ko) 2015-03-31 2022-04-04 엘지이노텍 주식회사 반도체 패키지
US9768135B2 (en) 2015-12-16 2017-09-19 Monolithic Power Systems, Inc. Semiconductor device having conductive bump with improved reliability
US10181448B2 (en) * 2016-03-22 2019-01-15 Advanced Semiconductor Engineering, Inc. Semiconductor devices and semiconductor packages
US10026707B2 (en) * 2016-09-23 2018-07-17 Microchip Technology Incorportated Wafer level package and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130334656A1 (en) * 2012-06-13 2013-12-19 Samsung Electronics Co., Ltd. Electrical interconnection structures including stress buffer layers
CN107564894A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 制造半导体封装的方法
CN108172560A (zh) * 2016-11-29 2018-06-15 台湾积体电路制造股份有限公司 集成电路和用于制造集成电路的方法
CN108242437A (zh) * 2016-12-26 2018-07-03 拉碧斯半导体株式会社 半导体装置以及半导体装置的制造方法

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