JP6687646B2 - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 52
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Description
誘導結合によって第1の送受信コイルと結合する第2の送受信コイル、第2の送受信コイルの両端から引き出された第2の引き出し線、および前記第2の引き出し線に接続して第2の送受信コイルとの間で信号を入出力する第2の送受信回路を複数のメモリチップ毎に有して、複数のメモリチップの積層方向の一端に配置されたインターポーザとを具備し、
複数のメモリチップは、平面視で、複数の第1の送受信回路が互いに重なる位置に配置され、これらの第1の送受信回路の周囲に第1の送受信コイルが互いに重ならない位置に配置された構造を有する半導体装置に関する。
図1は、本実施の形態による半導体装置の一例を示す一部断面図である。図1の半導体装置1では、基板5の上にはんだボール6を介してプロセッサ2が実装されている。また、基板5の上には、DRAM(Dynamic Random Access Memory)のメモリチップ11〜14が基板5に対して垂直方向に積層された積層構造(積層DRAM4)が設けられている。積層DRAM4におけるメモリチップの積層方向の一端、すなわち、メモリチップ11の上には、インターポーザ3が配置されている。インターポーザ3を設けることで、プロセッサ2で発した熱がDRAMの動作に悪影響を与えるのを防止できる。尚、半導体装置1は、例えば、プロセッサ2の周囲に、インターポーザ3と積層DRAM4とからなる構造体が複数配置された構造とすることができる。積層は、フュージョンボンディング(Fusion Bonding)によって実現されている。積層は、接着剤を使用した手法や、表面活性化常温接合等の他の手法を利用してもよい。
図6は、本実施の形態による半導体装置の一例を示す一部断面図である。図6の半導体装置101では、基板105の上に、はんだボール106を介してプロセッサ102が実装されており、また、DRAM(Dynamic Random Access Memory)の5枚のメモリチップ111,11〜14が基板105に対して垂直方向に積層された積層DRAM104が設けられている。
本実施の形態の半導体装置は、実施の形態1で述べた図1と同様に、基板の上にはんだボールを介してプロセッサが実装された構造とすることができる。この基板の上には、DRAM(Dynamic Random Access Memory)のメモリチップが基板に対して垂直方向に積層された積層構造(積層DRAM)が設けられる。また、積層DRAMにおけるメモリチップの積層方向の一端には、インターポーザが配置される。そして、プロセッサとDRAMとは、インターポーザを介して電気的に接続される。
2,102 プロセッサ
3,20 インターポーザ
4,104,204 積層DRAM
5,105 基板
6,106 はんだボール
11〜14,21〜28,111 メモリチップ
Claims (9)
- 誘導結合による通信用の第1の送受信コイル、前記第1の送受信コイルの両端から引き出された第1の引き出し線、および前記第1の引き出し線に接続して前記第1の送受信コイルとの間で信号を入出力する第1の送受信回路を各々有して積層された複数のメモリチップと、
誘導結合によって前記第1の送受信コイルと結合する第2の送受信コイル、前記第2の送受信コイルの両端から引き出された第2の引き出し線、および前記第2の引き出し線に接続して前記第2の送受信コイルとの間で信号を入出力する第2の送受信回路を前記複数のメモリチップ毎に有して、前記複数のメモリチップの積層方向の一端に配置されたインターポーザとを具備し、
前記複数のメモリチップは、平面視で、複数の前記第1の送受信回路が互いに重なる位置に配置され、これらの第1の送受信回路の周囲に前記第1の送受信コイルが互いに重ならない位置に配置された構造を有する半導体装置。 - 前記第1の送受信コイルは、前記第1の送受信回路の周囲に平面視で対称に配置される請求項1に記載の半導体装置。
- 前記第1の引き出し線の長さは、前記複数のメモリチップ間で等しい請求項1に記載の半導体装置。
- 前記第2の送受信コイルの中心軸は、それぞれ対応する前記第1の送受信コイルの中心軸に一致する請求項1に記載の半導体装置。
- 前記メモリチップ毎に配置された第2の引き出し線はいずれも等しい長さである請求項1に記載の半導体装置。
- 前記インターポーザは、積層された前記複数のメモリチップのうちで積層方向の一端に位置するメモリチップである請求項1に記載の半導体装置。
- 前記複数のメモリチップは、複数のグループ単位に分割され、各グループ単位を構成するメモリチップの前記第1の送受信コイル、前記第1の引き出し線、および前記第1の送受信回路は、平面視でそれぞれ互いに重なる位置に配置される請求項1に記載の半導体装置。
- 前記メモリチップは、それぞれ、互いに異なる識別番号を出力する演算回路と、前記識別番号をメモリチップ選択用のアドレスと比較して一致するか否かを検知する比較回路とを有し、前記アドレスの信号線は全ての前記メモリチップ間で共通する請求項7に記載の半導体装置。
- 前記インターポーザは前記アドレスを生成して出力する請求項8に記載の半導体装置。
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US10483242B2 (en) * | 2016-02-10 | 2019-11-19 | Ultramemory Inc. | Semiconductor device |
JP7278016B2 (ja) * | 2020-05-08 | 2023-05-19 | ウルトラメモリ株式会社 | 半導体装置 |
CN115398624A (zh) * | 2020-05-11 | 2022-11-25 | 超极存储器股份有限公司 | 半导体装置及其制造方法 |
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JP4131544B2 (ja) | 2004-02-13 | 2008-08-13 | 学校法人慶應義塾 | 電子回路 |
WO2007029435A1 (ja) * | 2005-09-02 | 2007-03-15 | Nec Corporation | 伝送方法、インターフェース回路、半導体装置、半導体パッケージ、半導体モジュールおよびメモリモジュール |
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JP5149554B2 (ja) * | 2007-07-17 | 2013-02-20 | 株式会社日立製作所 | 半導体装置 |
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JP4947316B2 (ja) | 2008-08-15 | 2012-06-06 | 信越化学工業株式会社 | 基板の接合方法並びに3次元半導体装置 |
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JP5559507B2 (ja) | 2009-10-09 | 2014-07-23 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びこれを備える情報処理システム |
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CN107424972A (zh) * | 2012-12-19 | 2017-12-01 | 瑞萨电子株式会社 | 半导体装置 |
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JP6434763B2 (ja) * | 2014-09-29 | 2018-12-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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Publication number | Publication date |
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CN108604586B (zh) | 2021-10-26 |
JPWO2017138106A1 (ja) | 2019-01-24 |
CN114121895A (zh) | 2022-03-01 |
US11437350B2 (en) | 2022-09-06 |
US10937765B2 (en) | 2021-03-02 |
US20210151415A1 (en) | 2021-05-20 |
US20200043899A1 (en) | 2020-02-06 |
WO2017138106A1 (ja) | 2017-08-17 |
CN108604586A (zh) | 2018-09-28 |
US10483242B2 (en) | 2019-11-19 |
US20190035768A1 (en) | 2019-01-31 |
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