CN107546134A - 制造晶片级封装的方法及由此制造的晶片级封装 - Google Patents
制造晶片级封装的方法及由此制造的晶片级封装 Download PDFInfo
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- CN107546134A CN107546134A CN201710195432.6A CN201710195432A CN107546134A CN 107546134 A CN107546134 A CN 107546134A CN 201710195432 A CN201710195432 A CN 201710195432A CN 107546134 A CN107546134 A CN 107546134A
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Abstract
制造晶片级封装的方法及由此制造的晶片级封装。提供的是一种晶片级封装及其制造方法。可以通过在虚设晶片上布置第一半导体裸片并且形成模制层和模制覆盖层来形成重构基板。可以将第二半导体裸片堆叠在所述第一半导体裸片上并且可以形成光敏介电层。可以对穿透所述光敏介电层的导电通孔进行电镀。
Description
技术领域
本公开的各种实施方式一般地可以涉及封装技术,并且更具体地,涉及制造扇出(fan out)晶片级封装(wafer level package)的方法及由此制造的晶片级封装。
背景技术
可以在诸如计算机、移动装置或数据存储部的电子产品中利用半导体封装。根据诸如智能电话的电子产品的减重量轻和小型化趋势,也已经要求半导体封装具有薄的厚度。尽管构成半导体封装的半导体芯片的大小已减小了,然而焊球的数量以及半导体封装的焊球之间的距离是固定的。为了包括具有固定距离并且具有特定数量的半导体封装的焊球,已提出了扇出封装结构。例如,已尝试了半导体芯片被注入在模制层中以形成重构晶片以及从半导体芯片延伸至模制层的布线的扇出半导体封装结构。
发明内容
根据实施方式,可以提供一种制造晶片级封装的方法。该方法可以包括以下步骤:在虚设晶片上形成覆盖第一半导体裸片(die)的模制层,选择性地去除所述模制层的边缘部分,形成覆盖其所述边缘部分被去除的所述模制层的模制覆盖层并且形成包括所述模制覆盖层、所述模制层和所述第一半导体裸片的重构基板,去除所述虚设晶片以使所述第一半导体裸片暴露,在所述第一半导体裸片上堆叠第二半导体裸片,在所述重构基板上形成覆盖所述第二半导体裸片的第一光敏介电层,形成穿透所述第一光敏介电层并且分别使所述第一半导体裸片和所述第二半导体裸片的一部分暴露的开口部分,以及形成分别填充所述开口部分的导电通孔(vias)。
根据实施方式,可以提供一种晶片级封装。该晶片级封装可以包括:模制层,该模制层围绕第一半导体裸片的表面和侧面;重构基板,该重构基板包括覆盖所述模制层的表面的模制覆盖层;第一光敏介电层,该第一光敏介电层形成在所述重构基板上以覆盖所述第二半导体裸片;以及导电通孔,该导电通孔穿透所述第一光敏介电层并且分别连接至所述第一半导体裸片和所述第二半导体裸片的一部分。
根据实施方式,可以提供一种晶片级封装。该晶片级封装可以包括基板;半导体裸片,该半导体裸片堆叠在所述基板上以形成阶梯(stepped)形状;底部填充物,该底部填充物填充所述半导体裸片的一部分与所述基板之间的空间;光敏介电层,该光敏介电层覆盖所述半导体裸片;以及导电通孔,该导电通孔穿透所述第一光敏介电层并且连接至所述半导体裸片的一部分。
附图说明
图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11和图12是例示了根据实施方式的扇出晶片级封装制造工艺的示例的表示的视图。
图13是例示了根据实施方式的晶片级封装的示例的表示的视图。
图14是例示了根据实施方式的晶片级封装的示例的表示的视图。
图15是例示了根据实施方式的采用包括封装的存储卡的电子系统的示例的表示的框图。
图16是例示了根据实施方式的包括封装的电子系统的示例的表示的框图。
具体实施方式
实施方式的描述中使用的术语对应于考虑到它们在实施方式中的功能而选择的单词,并且可以根据实施方式所属于的本领域的普通技术人员将术语的含义解释为不同的。如果被详细地定义,则可以根据定义对术语进行解释。除非另外定义,否则本文所使用的术语(包括技术和科学术语)具有与由实施方式所属于的本领域的普通技术人员所通常理解的相同的含义。在实施方式的以下描述中,应理解,术语“第一”和“第二”、“顶部”和“底部或下部”旨在标识构件,而不用于定义仅构件它本身或者意指特定顺序。
半导体封装可以包括诸如半导体裸片或芯片的电子器件,并且半导体裸片或芯片可以包括来自集成有电子电路的半导体基板的裸片或芯片的切割或加工形式。半导体芯片可以是存储器芯片,其中存储器集成电路诸如动态随机存取存储器(DRAM)器件、静态随机存取存储器(SRAM)器件、闪速存储器器件、磁随机存取存储器(MRAM)器件、电阻式随机存取存储器(ReRAM)器件、铁电随机存取存储器(FeRAM)器件或相变随机存取存储器(PcRAM)器件。另选地,半导体裸片或芯片可以是在半导体基板上集成了逻辑电路的逻辑裸片或ASIC芯片。
封装基板是用于将半导体芯片电连接至外部的其它器件的基板,并且与半导体基板不同封装基板可以在介电材料层的基板主体中包括电路迹线。封装基板可以具有印刷电路板(PCB)的形式。可以将半导体封装应用于诸如移动装置、生物或保健相关电子装置以及到人体的可穿戴电子装置的信息通信装置。
相同的附图标记在本说明书中自始至终指代相同的元件。因此,即使未参照一附图提及或者描述附图标记,也可以参照另一附图提及或者描述该附图标记。另外,即使未在一附图中例示附图标记,也可以参照另一附图提及或者描述它。
各种实施方式可以致力于制造晶片级封装的方法及由此制造的晶片级封装。
图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11和图12是例示了根据实施方式的扇出晶片级封装制造工艺的示例的表示的视图。
参照图1,分离层20可以形成在虚设晶片10上。分离层20可以形成在虚设晶片10的表面11上。虚设晶片10可以具有侧边缘12。虚设晶片10可以是硅晶片。虚设晶片10可以是由透明材料制成的晶片,例如,可以是玻璃晶片。分离层20可以包括使得其它构件能够接合在其上并与其分离的粘合层,例如,可以包括临时粘合层。
可以在虚设晶片10的表面11上布置多个第一半导体裸片100。第一半导体裸片100中的每一个可以通过分离层20附接至虚设晶片10。可以将第一半导体裸片100中的每一个布置在虚设晶片10上,使得第一半导体裸片100的第一表面102面对虚设晶片10的表面11,并且与第一表面102相反的第二表面104面对与虚设晶片10的第一表面11面对的方向相同的方向。
第一半导体裸片100中的每一个可以包括第一器件基板120、第一器件焊盘160和第一钝化层140。第一器件基板120可以包括多个单元元件。这些单元元件中的每一个可以包括例如存储器元件、逻辑元件或控制元件中的至少一个。第一器件焊盘160可以穿透第一钝化层140并且电连接至这些单元元件中的至少一个。可以将第一钝化层140和第一器件焊盘160布置在第一器件基板120上。
模制层200可以形成在虚设晶片10上。模制层200可以形成在虚设晶片10上以覆盖第一半导体裸片100。模制层200可以包括例如环氧模制化合物(EMC)。模制层200可以被形成为覆盖第一半导体裸片100中的每一个的第二表面104以及将第二表面104连接至第一表面102的侧表面103,从而围绕第一半导体裸片100中的每一个。模制层200可以被形成为填充形成在第一半导体裸片100之间的间隙。模制层200可以不延伸以覆盖第一半导体裸片100的第一表面102。可以将模制层200模制在虚设晶片10上以覆盖第一半导体裸片100,并且可以将第一半导体裸片100植入(impregnated)在模制层200中,使得第一表面102从模制层200被暴露。
可以将模制层200模制为具有与虚设晶片10的平面形状基本上相同的平面形状。可以将模制层200模制为使得模制层200的边际侧边缘202被布置到虚设晶片10的边际侧边缘12。可以将模制层200模制为具有与虚设晶片10的边际轮廓形状基本上相同的边际轮廓形状,例如,如平面上看到的晶片形状。
参照图2,可以选择性地去除模制层(图1的200)的边际边缘部分201。通过去除模制层的边际边缘部分201而形成的边缘裁切模制层200T可以使虚设晶片10或分离层20的边际边缘部分的表面区域13暴露。可以将通过去除模制层的边际边缘部分201而形成的边缘裁切模制层200T的侧边缘203回拉到从模制层200的初始侧边缘202向内部凹进的位置。裁切模制层200T的裁切侧边缘203以及虚设晶片10的侧边缘12可以形成阶梯形状。
参照图3,模制覆盖层300可以被形成为覆盖边缘裁切模制层200T。模制覆盖层300可以被形成为阻止模制层200T不受外部的影响。模制覆盖层300可以被形成为覆盖边缘裁切模制层200T的裁切侧边缘203,并且覆盖和屏蔽边缘裁切模制层200T的第一表面(例如,上表面204),所述第一表面连接至裁切侧边缘203。与边缘裁切模制层200T的第一表面相反的第二表面(例如,下表面205)与分离层20接触,并且可以不被模制覆盖层300直接覆盖。
模制覆盖层300可以由与构成模制层200T的材料不同的材料组成。模制覆盖层300可以包括介电材料。可以通过涂覆液体介电材料而形成模制覆盖层300。可以通过将介电材料的膜附接至边缘裁切模制层200T而形成模制覆盖层300。介电材料可以包括聚合物材料。介电材料可以包括聚酰亚胺(PI)成分或环氧树脂成分。模制层200T可以包括填料(filler)材料,使得模制形状被稳定地维持而不变形。模制覆盖层300可以由不包括诸如硅石填料的填料颗粒的层形成。通过比较,模制层200T可以由包括填料材料分布在诸如环氧树脂的树脂中的模制材料的层形成。
嵌入在边缘裁切模制层200T、模制层200T和模制覆盖层300中的第一半导体裸片100可以构成重构基板30结构。模制覆盖层300的外侧面302可以是重构基板30的外侧面。重构基板30的边际轮廓形状可以与虚设晶片10的边际轮廓形状基本上相同,例如,可以具有如平面上看到的晶片形状。模制覆盖层300的外侧面302和虚设晶片10的侧边缘12可以形成布置的侧面,使得模制覆盖层300和虚设晶片10彼此具有基本上相同的大小和形状。
参照图4,虚设晶片10可以与重构基板30分离。可以使第一半导体裸片100中的每一个的第一器件焊盘160以及第一半导体裸片100中的每一个的第一表面102暴露于重构基板30的第一表面31。可以通过削弱分离层20的粘合强度来使重构基板30与虚设晶片10去接合。因为分离层20包括临时粘合层,所以可以通过对该临时粘合层施加紫外线(UV)辐射或热来削弱粘合强度。
参照图5,可以将第二半导体裸片400安装在重构基板30的第一表面31上。可以将第二半导体裸片400中的每一个堆叠在重构基板30上以与第一半导体裸片100中的每一个的第一表面102接触。可以经由第一粘合层501将第二半导体裸片400中的每一个堆叠在各个对应的第一半导体裸片100上。第一粘合层501可以作为具有将第二半导体裸片400充分地永久性地附接至第一半导体裸片100的粘合剂成分的永久粘合层而形成。第一粘合层501可以是被维持在封装中而无需去除的永久粘合层。第一粘合层501使得第二半导体裸片400能够同时附接至第一半导体裸片100的第一表面102并且附接至模制层200T的第二表面205。
可以将第二半导体裸片400中的每一个布置在偏移位置(即,相对于第一半导体裸片100中的每一个的横向移位位置)上。可以将第二半导体裸片400中的每一个布置为使第一半导体裸片100中的每一个的第一器件焊盘160暴露,并且与第一半导体裸片100中的每一个部分地交叠。可以按照级联形状堆叠第二半导体裸片400中的每一个以及第一半导体裸片100中的每一个。图5例示了第二半导体裸片400和第一半导体裸片100被堆叠为形成阶梯形状的情况。另外,第二半导体裸片400和第一半导体裸片100可以交叉并堆叠以形成如平面上看到的交叉形状。
第二半导体裸片400中的每一个可以包括第二器件基板420、第二器件焊盘460和第二钝化层440。第二器件基板420可以包括多个单元元件。这些单元元件中的每一个可以包括至少存储器元件、逻辑元件或控制元件。第二器件焊盘460可以穿透第二钝化层440并且电连接至这些单元元件中的至少一个。可以将第二钝化层440和第二器件焊盘460布置在第二器件基板420上。可以将第二半导体裸片400布置为使得第二器件焊盘460面对与第一半导体裸片100的第一器件焊盘160面对的方向相同的方向。
参照图6,可以将第三半导体裸片402中的每一个分别堆叠在第二半导体裸片400中的每一个上。可以利用第二粘合层503将第三半导体裸片402中的每一个堆叠在第二半导体裸片400上。可以利用第三粘合层505将第四半导体裸片404中的每一个堆叠在第三半导体裸片402中的每一个上。第二粘合层503可以将第三半导体裸片402充分地永久地附接至第二半导体裸片400,并且第三粘合层505可以将第四半导体裸片404充分地永久地附接至第三半导体裸片402。
第三半导体裸片402中的每一个可以位于相对于第二半导体裸片400中的每一个的偏移位置上。也就是说,第三半导体裸片402可以位于从第二半导体裸片400横向移位的位置上。第四半导体裸片404中的每一个可以位于相对于第三半导体裸片402中的每一个的偏移位置上。也就是说,第四半导体裸片404可以位于从第三半导体裸片402横向移位的位置上。可以连续地堆叠第一半导体裸片100、第二半导体裸片400、第三半导体裸片402和第四半导体裸片404以位移并形成阶梯形状或级联形状。
可以将第三半导体裸片402布置为使第二半导体裸片400的第二器件焊盘460暴露,并且与第二半导体裸片400部分地交叠。第三半导体裸片402中的每一个可以包括第三器件基板422、第三器件焊盘462和第三钝化层442。第四半导体裸片404中的每一个可以包括第四器件基板424、第四器件焊盘464和第四钝化层444。
第三器件基板422中的每一个以及第四器件基板424中的每一个可以包括多个单元元件。这些单元元件中的每一个可以包括例如至少存储器元件、逻辑元件或控制元件。第三器件焊盘462和第四器件焊盘464分别可以穿透第三钝化层442和第四钝化层444,并且分别电连接至至少一单元元件。
可以将第三钝化层442和第三器件焊盘462布置在第三器件基板422上。可以将第四钝化层444和第四器件焊盘464布置在第四器件基板424上。可以将第三半导体裸片402布置为使得第三器件焊盘462面对与第一半导体裸片100的第一器件焊盘160面对的方向相同的方向。可以将第四半导体裸片404布置为使得第四器件焊盘464面对与第一半导体裸片100的第一器件焊盘160面对的方向相同的方向。可以将第四半导体裸片404堆叠在第三半导体裸片420上以使第三器件焊盘462暴露。还可以将附加的半导体裸片堆叠在第四半导体裸片404上。
参照图6,在第三半导体裸片402和第四半导体裸片404的横向突出部分与模制层200T的第二表面205之间可以存在空间601。
参照图7,底部填充物600可以被形成为填充第三半导体裸片402和第四半导体裸片404的横向突出部分与模制层200T的第二表面205之间的空间601。底部填充物600可以通过喷射介电材料、环氧树脂材料或聚合材料而形成。
参照图8,覆盖并掩埋第二半导体裸片400、第三半导体裸片402和第四半导体裸片404的第一光敏介电层700可以形成在重构基板30上。因为半导体裸片402和第四半导体裸片404的横向突出部分与模制层200T的第二表面205之间的空间601被提前填充有底部填充物600,所以第一光敏介电层700可以被形成为与底部填充物600接触。因为底部填充物600填充空间601,所以第一光敏介电层700不必穿透到空间601中,从而防止空间601未被填充的空隙故障。
可以将第一光敏介电层700设置为绝缘层。可以通过在重构基板30上层压或者涂覆诸如光敏聚酰亚胺(PI)或光敏聚苯并恶唑的光敏聚合物材料来形成第一光敏介电层700。因为第一光敏介电层700包含光敏剂,所以可以改变第一光敏介电层700的特性,使得由诸如紫外线(UV)射线的光源暴露的一部分的溶解度变得与未暴露部分的溶解度不同。第一光敏介电层700可以被形成为整体上具有平坦表面。
当第二半导体裸片400、第三半导体裸片402和第四半导体裸片404被第一光敏介电层700覆盖和掩埋时,可以通过第一粘合层501、第二粘合层503和第三粘合层505来使第二半导体裸片400、第三半导体裸片402和第四半导体裸片404维持在附接且固定状态下。因为第二半导体裸片400、第三半导体裸片402和第四半导体裸片404由具有永久粘合强度的第一粘合层501、第二粘合层503和第三粘合层505固定,所以能够在第一光敏介电层700被形成时有效地防止半导体裸片的位置变化的现象。
参照图9,第一开口部分701、703、705和707可以形成在第一光敏介电层700中,所述第一开口部分701、703、705和707使半导体裸片100、400、402和404的表面的一部分(即,器件焊盘160、460、462和464)暴露。第一开口部分701、703、705和707中的每一个可以形成为穿透第一光敏介电层700并且分别与器件焊盘160、460、462和464中的每一个对齐的基本上垂直的孔。第一开口部分第一孔701可以作为使第一半导体裸片100的第一器件焊盘160暴露的孔而形成。第一开口部分第二孔703可以作为使第二半导体裸片400的第二器件焊盘460暴露的孔而形成。第一开口部分第三孔705可以作为使第三半导体裸片462的第三器件焊盘462暴露的孔而形成。第一开口部分第四孔707可以作为使第四半导体裸片404的第四器件焊盘464暴露的孔而形成。
可以通过使第一光敏介电层700的一些部分直接暴露在诸如UV射线的光源下并且使第一光敏介电层700显影而形成第一开口部分701、703、705和707。因为能够对第一光敏介电层700直接应用光刻工艺,所以能够省略形成用于使第一光敏介电层700图案化的附加光致抗蚀剂材料。另外,因为重构基板30具有诸如硅晶片的晶片形状,所以能够利用用于对硅晶片进行加工的设备(例如,硅晶片加工设备)来形成第一开口部分701、703、705和707。因此,能够使第一开口部分701、703、705和707中的每一个图案化为具有更精细直径的孔。
参照图10,导电通孔801、803、805和807可以被形成为填充第一开口部分701、703、705和707中的每一个。导电通孔801、803、805和807中的每一个可以被形成为包括各种导电材料。导电通孔801、803、805和807中的每一个可以被形成为包括诸如具有高导电性的铜(Cu)的金属材料的层。
可以利用电镀工艺来形成导电通孔801、803、805和807。可以通过将其中形成有第一开口部分701、703、705和707的生成物插入到包含电镀溶液的电镀槽中来执行电镀工艺,并且可以对导电通孔801、803、805和807进行电镀。同时,因为模制层200T被模制覆盖层300和第一光敏介电层700覆盖并且与电镀溶液隔离,所以能够有效地防止电镀溶液被可以被包含在模制层200T中的杂质污染。构成模制层200T的环氧模制化合物(EMC)材料可以包含填料。填料会污染电镀溶液。例如,用作填料的硅石颗粒会污染电镀溶液。因为模制层200T被模制覆盖层300和第一光敏介电层700密封,所以能够从根本上防止由颗粒导致的对溶液的污染。因为模制覆盖层300不包含填料,所以能够防止由填料对电镀溶液的污染。
第一导电通孔801可以作为连接至第一半导体裸片100的第一器件焊盘160的垂直连接件而形成。第二导电通孔803可以作为连接至第二半导体裸片400的第二器件焊盘460的垂直连接件而形成。第三导电通孔805可以作为连接至第三半导体裸片402的第三器件焊盘462的垂直连接件而形成。第四导电通孔807可以作为连接至第四半导体裸片404的第四器件焊盘464的垂直连接件而形成。
参照图11,第二光敏介电层900可以形成在第一光敏介电层700上。第二光敏介电层900可以形成在其中形成有导电通孔801、803、805和807的第一光敏介电层700上。可以将第二光敏介电层900设置为具有与第一光敏介电层700的厚度不同(例如,更薄)的厚度的绝缘层。可以通过在第一光敏介电层700上层压或者涂覆诸如光敏聚酰亚胺(PI)或光敏聚苯并恶唑的光敏聚合物材料来形成第二光敏介电层900。因为第二光敏介电层900包含光敏剂,所以可以改变第二光敏介电层900的特性,使得通过诸如紫外线(UV)射线的光源暴露的一部分的溶解度变得与未暴露部分的溶解度不同。
可以通过使第二光敏介电层900的一部分直接暴露在诸如UV射线的光源下并且使第二光敏介电层900显影来形成多个第二开口部分901。可以按照用于分别连接至导电通孔801、803、805和807的再分布层(RDL)图案的凹面形状来形成第二开口部分901中的每一个。
可以通过用导电材料填充第二开口部分901来形成RDL图案850。RDL图案850中的每一个可以被形成为包括各种导电材料。RDL图案850中的每一个可以被形成为包括诸如具有高导电性的铜(Cu)的金属材料的层。可以利用电镀工艺来形成RDL图案850。可以通过将其中形成有第二开口部分901的生成物插入到包含电镀溶液的电镀槽中来执行电镀工艺。这时,因为模制层200T部分被模制覆盖层300以及第一光敏介电层700和第二光敏介电层900覆盖并且与电镀溶液隔离,所以能够有效地防止电镀溶液被可以被包含在模制层200T中的杂质污染。
第三光敏介电层950可以被形成为覆盖RDL图案850和第二光敏介电层900。可以通过层压或者涂覆包含光敏成分的聚合物材料的层来形成第三光敏介电层950。可以通过使第三光敏介电层950的一部分直接暴露在诸如UV射线的光源下并且使第三光敏介电层950显影来形成第三开口部分951。第三开口部分951中的每一个可以被形成为使RDL图案850的一些部分暴露以提供连接部分851。
参照图12,外部连接件990可以形成在RDL图案850的连接部分851中,连接部分851由第三光敏介电层950暴露。诸如焊球的外部连接件990中的每一个可以附接至RDL图案850的经暴露的连接部分851中的每一个。附接有外部连接件990的生成的封装结构1可以具有如下结构:第一半导体裸片100被掩埋在重构基板30中,第二半导体裸片400在与第一半导体裸片100一起形成阶梯形状的同时被堆叠在重构结构30上,并且第三半导体裸片402和第四半导体裸片404在形成阶梯形状的同时被顺序地堆叠在第二半导体裸片400上。
底部填充物600可以被形成为填充第三半导体裸片402和第四半导体裸片404的一部分与重构基板30之间的空间,并且第一粘合层501可以同时将第二半导体裸片400永久地附接至第一半导体裸片100和模制层200T。模制层200T可以包括包含分布在其中的填料的树脂,并且模制覆盖层300可以包括不包含填料的介电材料层。
图13是例示了根据实施方式的晶片级封装2的示例的表示的视图。
参照图13,可以将如参照图1、图2、图3、图4、图5、图6、图7、图8、图9、图10、图11和图12所描述的封装结构单取并分成单独的封装结构2。封装结构2可以包括掩埋第二半导体裸片400上的第三半导体裸片402和第四半导体裸片404的第一光敏介电层700,以及穿透第一光敏介电层700并且分别连接至第一半导体裸片100、第二半导体裸片400、第三半导体裸片402和第四半导体裸片404的导电通孔801、803、805和807。
封装结构2可以包括被堆叠在第一光敏介电层700上的第二光敏介电层900和第三光敏介电层950,并且包括由第二光敏介电层900围绕的RDL图案850。封装结构2可以包括充分地穿透第三光敏层950并且连接至RDL图案850的外部连接件990。
构成封装结构2的重构基板30可以包括掩埋第一半导体裸片100的模制层200T以及覆盖模制层200T的表面的至少一部分的模制覆盖层300。模制覆盖层300可以被形成为覆盖表面,例如,模制层200T的第一表面204。模制覆盖层300可以不延伸至模制层200T的切割侧表面207,其通过被分成单独的封装结构2来暴露,并且可以通过模制覆盖层300来使模制层200T的切割侧表面207暴露。
参照图13,尽管重构基板30包括第一半导体裸片100的情况被用作示例,然而能够实现第一半导体裸片100被省略、第二半导体裸片400、第三半导体裸片420和第四半导体裸片404在形成阶梯形状的同时被堆叠在基板上并且底部填充物600填充第三半导体裸片402和第四半导体裸片404的一部分与基板之间的空间的封装结构。
图14是例示了根据实施方式的晶片级封装3的示例的表示的视图。
参照图14,晶片级封装3可以包括围绕第一半导体裸片2100的表面和侧面的模制层2200T,以及包括覆盖模制层2200T的表面2204的模制覆盖层2300的重构基板2030。模制覆盖层2300可以包括与模制层2200T不同的材料。模制层2200T可以包括包含填料材料(例如,环氧模制化合物(EMC))的树脂材料。模制覆盖层2300可以包括不包含填料材料的介电材料的层。可以将第二半导体裸片2400堆叠在第一半导体裸片2100上以形成阶梯形状。第二半导体裸片2400可以通过永久粘合层2501附接至第一半导体裸片2100,并且可以同时附接至模制层2200T的另一表面2205。
第一光敏介电层2700可以形成在重构基板2030上以覆盖第二半导体裸片2400,并且可以布置穿透第一光敏介电层2700并且连接至第一半导体裸片2100的第一导电通孔2801。可以将第二导电通孔2803布置为充分地穿透第一光敏介电层2700并且连接至第二半导体裸片2400。可以将第二光敏介电层2900布置在第一光敏介电层2700上,并且可以将通过第二光敏介电层2900分成图案的再分布层(RDL)图案2850布置为分别连接至第一导电通孔2801和第二导电通孔2803。可以将第三光敏介电层2950布置在第二光敏介电层2900上,并且可以将外部连接件2990布置为充分地穿透第三光敏介电层2950并且分别连接至RDL图案2850。
图15是例示了根据实施方式的包括有包括至少一个半导体封装的存储卡7800的电子系统的示例的表示的框图。存储卡7800包括存储器7810(诸如非易失性存储器器件)和存储器控制器7820。存储器7810和存储器控制器7820可以存储数据或者读取存储的数据。存储器7810和/或存储控制器7820包括布置在根据实施方式的嵌入式封装中的一个或更多个半导体芯片。
存储器7810可以包括适用本公开的实施方式的技术的非易失性存储器器件。存储器控制器7820可以控制存储器7810,使得响应于来自主机7830的读取/写入请求所存储的数据被读出或者数据被存储。
图16是例示了根据实施方式的包括至少一个封装的电子系统8710的示例的表示的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过提供数据用来移动的路径的总线8715彼此联接。
在实施方式中,控制器8711可以包括一个或更多个微处理器、数字信号处理器、微控制器和/或能够执行与这些组件相同的功能的逻辑器件。控制器8711或存储器8713可以包括根据本公开的实施方式的半导体封装中的一个或更多个。输入/输出装置8712可以包括在键区、键盘、显示装置、触摸屏等当中选择的至少一个。存储器8713是用于存储数据的装置。存储器8713可以存储数据和/或要由控制器8711执行的命令等。
存储器8713可以包括诸如DRAM的易失性存储器器件和/或诸如闪速存储器的非易失性存储器器件。例如,可以将闪速存储器安装到诸如移动终端或台式计算机的信息处理系统。闪速存储器可以构成固态磁盘(SSD)。在这种情况下,电子系统8710可以在闪速存储器系统中稳定地存储大量数据。
电子系统8710还可以包括被配置为向通信网络发送数据并且从通信网络接收数据的接口8714。接口8714可以是有线型或无线型。例如,接口8714可以包括天线或者有线或无线收发器。
电子系统8710可以实现为执行各种功能的移动系统、个人计算机、工业计算机或逻辑系统。例如,移动系统可以是以下项中的任一个:个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统以及信息发送/接收系统。
如果电子系统8710是能够执行无线通信的设备,则可以在诸如CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDMA(宽带码分多址)、CDMA2000、LTE(长期演进)和Wibro(无线宽带互联网)的通信系统中使用电子系统8710。
已经出于例示性目的公开了本公开的实施方式。本领域技术人员将了解,在不脱离本公开和所附权利要求的范围和精神的情况下,各种修改、添加和替换是可能的。
相关申请的交叉引用
本申请要求于2016年6月27日提交的韩国申请第10-2016-0080125号的优先权,通过引用将其整体地并入本文。
Claims (20)
1.一种晶片级封装,该晶片级封装包括:
模制层,该模制层围绕第一半导体裸片的表面和侧面;
重构基板,该重构基板包括覆盖所述模制层的表面的模制覆盖层;
第二半导体裸片,该第二半导体裸片被堆叠在所述第一半导体裸片上;
第一光敏介电层,该第一光敏介电层形成在所述重构基板上以覆盖所述第二半导体裸片;以及
导电通孔,该导电通孔穿透所述第一光敏介电层并且分别连接至所述第一半导体裸片的一部分和所述第二半导体裸片的一部分。
2.根据权利要求1所述的晶片级封装,其中,所述第一半导体裸片包括:
第一器件基板;
第一钝化层,该第一钝化层被布置在所述第一器件基板上;以及
穿透所述第一钝化层并被暴露的第一器件焊盘,该第一器件焊盘连接至所述第一器件基板。
3.根据权利要求2所述的晶片级封装,其中,所述第二半导体裸片被布置在所述第一半导体裸片上以使所述第一器件焊盘暴露。
4.根据权利要求3所述的晶片级封装,其中,所述第二半导体裸片包括:
第二器件基板;
第二钝化层,该第二钝化层被布置在所述第二器件基板上;以及
穿透所述第二钝化层并被暴露的第二器件焊盘,该第二器件焊盘连接至所述第二器件基板,
其中,所述第二半导体裸片被布置在所述第一半导体裸片上,使得所述第二器件焊盘面对与所述第一器件焊盘面对的方向相同的方向。
5.根据权利要求1所述的晶片级封装,该晶片级封装还包括堆叠在所述第二半导体裸片上以形成阶梯形状的第三半导体裸片和第四半导体裸片。
6.根据权利要求5所述的晶片级封装,该晶片级封装还包括底部填充物,所述底部填充物填充所述第三半导体裸片的一部分和所述第四半导体裸片的一部分与所述重构基板的所述模制层之间的空间。
7.根据权利要求1所述的晶片级封装,其中,所述第二半导体裸片通过永久粘合层充分地同时附接至所述第一半导体裸片和所述模制层。
8.根据权利要求1所述的晶片级封装,该晶片级封装还包括:
第二光敏介电层,该第二光敏介电层被布置在所述第一光敏介电层上;以及
再分布层图案,该再分布层图案分别连接至所述导电通孔。
9.根据权利要求1所述的晶片级封装,其中,所述模制层和所述模制覆盖层由彼此不同的材料形成。
10.根据权利要求9所述的晶片级封装,
其中,所述模制层包括树脂,所述树脂包含分布在其中的填料,并且
其中,所述模制覆盖层包括排除所述填料的介电材料层。
11.一种晶片级封装,该晶片级封装包括:
基板;
半导体裸片,该半导体裸片被堆叠在所述基板上以形成阶梯形状;
底部填充物,该底部填充物填充所述半导体裸片的一部分与所述基板之间的空间;
光敏介电层,该光敏介电层覆盖所述半导体裸片;以及
导电通孔,该导电通孔穿透第一光敏介电层并且连接至所述半导体裸片的一部分。
12.一种制造晶片级封装的方法,该方法包括以下步骤:
在虚设晶片上形成覆盖第一半导体裸片的模制层;
选择性地去除所述模制层的边缘部分;
通过形成模制覆盖层以在选择性地去除所述模制层的所述边缘部分之后覆盖所述模制层来形成包括所述模制覆盖层、所述模制层和所述第一半导体裸片的重构基板;
去除所述虚设晶片以使所述第一半导体裸片暴露;
在暴露的所述第一半导体裸片上堆叠第二半导体裸片;
在所述重构基板上形成覆盖所述第二半导体裸片的第一光敏介电层;
形成开口部分,所述开口部分穿透所述第一光敏介电层并且分别使所述第一半导体裸片的一部分和所述第二半导体裸片的一部分暴露;以及
形成填充所述开口部分的导电通孔。
13.根据权利要求12所述的方法,该方法还包括以下步骤:在所述第二半导体裸片上堆叠第三半导体裸片和第四半导体裸片以形成阶梯形状。
14.根据权利要求13所述的方法,该方法还包括以下步骤:形成填充所述第三半导体裸片的一部分和所述第四半导体裸片的一部分与所述重构基板的所述模制层之间的空间的底部填充物。
15.根据权利要求12所述的方法,其中,所述模制层和所述模制覆盖层包括彼此不同的材料。
16.根据权利要求15所述的方法,
其中,所述模制层包括树脂,所述树脂包含分布在其中的填充材料,并且
其中,所述模制覆盖层包括不包含填充材料的介电材料。
17.根据权利要求12所述的方法,其中,形成开口部分的步骤包括以下步骤:
使所述第一光敏介电层的一部分暴露;以及
使暴露的所述部分显影。
18.根据权利要求12所述的方法,该方法还包括以下步骤:
在所述第一光敏介电层上形成第二光敏介电层;以及
形成分别连接至所述导电通孔的再分布层图案。
19.一种制造晶片级封装的方法,该方法包括以下步骤:
形成围绕第一半导体裸片的表面和侧面的模制层;
形成覆盖所述模制层的表面和侧面的模制覆盖层;
在所述第一半导体裸片上堆叠第二半导体裸片以使所述第一半导体裸片的一部分暴露;以及
形成覆盖所述第二半导体裸片的第一光敏介电层,
其中,所述模制覆盖层和所述第一光敏介电层对所述模制层进行密封。
20.根据权利要求19所述的方法,该方法还包括以下步骤:在所述第二半导体裸片上堆叠第三半导体裸片和第四半导体裸片以形成阶梯形状。
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CN110060984A (zh) * | 2018-01-18 | 2019-07-26 | 爱思开海力士有限公司 | 包括多芯片层叠物的半导体封装及其制造方法 |
CN112956023A (zh) * | 2021-02-05 | 2021-06-11 | 长江存储科技有限责任公司 | 倒装芯片堆叠结构及其形成方法 |
WO2022165749A1 (en) * | 2021-02-05 | 2022-08-11 | Yangtze Memory Technologies Co., Ltd. | Flip-chip stacking structures and methods for forming the same |
CN112956023B (zh) * | 2021-02-05 | 2023-09-12 | 长江存储科技有限责任公司 | 倒装芯片堆叠结构及其形成方法 |
CN115050655A (zh) * | 2021-03-09 | 2022-09-13 | 爱思开海力士有限公司 | 层叠封装及其制造方法 |
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US20170373041A1 (en) | 2017-12-28 |
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